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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [cache.ld] - Blame information for rev 1777

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Line No. Rev Author Line
1 622 simons
MEMORY
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        {
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        except : ORIGIN = 0x00000000, LENGTH = 0x00002000
4 970 simons
        flash  : ORIGIN = 0xf0000000, LENGTH = 0x00200000
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        ram    : ORIGIN = 0x00002000, LENGTH = 0x001fe000
6 622 simons
        }
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SECTIONS
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{
10 970 simons
      .reset :
11 622 simons
        {
12 970 simons
        *(.reset)
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         _src_beg = .;
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        } > flash
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      .text :
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        AT ( ADDR (.reset) + SIZEOF (.reset) )
17 622 simons
        {
18 970 simons
        _dst_beg = .;
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        *(.text)
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        } > ram
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      .data :
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        AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )
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        {
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        *(.data)
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        *(.rodata)
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        _dst_end = .;
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        } > ram
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      .bss :
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        {
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        *(.bss)
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        } > ram
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      .stack  ALIGN(0x10) (NOLOAD):
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        {
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        *(.stack)
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        _ram_end = .;
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        } > ram
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}

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