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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [cache_asm.S] - Blame information for rev 970

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Line No. Rev Author Line
1 621 simons
#include "spr_defs.h"
2 970 simons
#include "board.h"
3 621 simons
 
4
#define IC_ENABLE 0
5
#define DC_ENABLE 0
6
 
7 970 simons
#define MC_CSR          (0x00)
8
#define MC_POC          (0x04)
9
#define MC_BA_MASK      (0x08)
10
#define MC_CSC(i)       (0x10 + (i) * 8)
11
#define MC_TMS(i)       (0x14 + (i) * 8)
12
 
13
 
14
        .extern _main
15
 
16 621 simons
        .global _ic_enable
17
        .global _ic_disable
18
        .global _dc_enable
19
        .global _dc_disable
20
        .global _dc_inv
21
        .global _ic_inv_test
22
        .global _dc_inv_test
23
 
24 970 simons
        .section .stack
25
        .space 0x1000
26
_stack:
27
 
28
              .section .reset, "ax"
29
 
30
        .org    0x100
31
_reset_vector:
32
        l.addi  r2,r0,0x0
33
        l.addi  r3,r0,0x0
34
        l.addi  r4,r0,0x0
35
        l.addi  r5,r0,0x0
36
        l.addi  r6,r0,0x0
37
        l.addi  r7,r0,0x0
38
        l.addi  r8,r0,0x0
39
        l.addi  r9,r0,0x0
40
        l.addi  r10,r0,0x0
41
        l.addi  r11,r0,0x0
42
        l.addi  r12,r0,0x0
43
        l.addi  r13,r0,0x0
44
        l.addi  r14,r0,0x0
45
        l.addi  r15,r0,0x0
46
        l.addi  r16,r0,0x0
47
        l.addi  r17,r0,0x0
48
        l.addi  r18,r0,0x0
49
        l.addi  r19,r0,0x0
50
        l.addi  r20,r0,0x0
51
        l.addi  r21,r0,0x0
52
        l.addi  r22,r0,0x0
53
        l.addi  r23,r0,0x0
54
        l.addi  r24,r0,0x0
55
        l.addi  r25,r0,0x0
56
        l.addi  r26,r0,0x0
57
        l.addi  r27,r0,0x0
58
        l.addi  r28,r0,0x0
59
        l.addi  r29,r0,0x0
60
        l.addi  r30,r0,0x0
61
        l.addi  r31,r0,0x0
62
 
63
        l.movhi r3,hi(start)
64
        l.ori   r3,r3,lo(start)
65
        l.jr    r3
66
        l.nop
67
start:
68
        l.jal   _init_mc
69
        l.nop
70
 
71
        l.movhi r1,hi(_stack)
72
        l.ori   r1,r1,lo(_stack)
73
 
74
        /* Copy data section */
75
        l.movhi r3,hi(_src_beg)
76
        l.ori   r3,r3,lo(_src_beg)
77
        l.movhi r4,hi(_dst_beg)
78
        l.ori   r4,r4,lo(_dst_beg)
79
        l.movhi r5,hi(_dst_end)
80
        l.ori   r5,r5,lo(_dst_end)
81
        l.sub   r5,r5,r4
82
        l.sfeqi r5,0
83
        l.bf    2f
84
        l.nop
85
1:      l.lwz   r6,0(r3)
86
        l.sw    0(r4),r6
87
        l.addi  r3,r3,4
88
        l.addi  r4,r4,4
89
        l.addi  r5,r5,-4
90
        l.sfgtsi r5,0
91
        l.bf    1b
92
        l.nop
93
2:
94
        l.movhi r2,hi(_main)
95
        l.ori   r2,r2,lo(_main)
96
        l.jr    r2
97
        l.nop
98
 
99
_init_mc:
100
 
101
        l.movhi r3,hi(MC_BASE_ADDR)
102
        l.ori   r3,r3,lo(MC_BASE_ADDR)
103
 
104
        l.addi  r4,r3,MC_CSC(0)
105
        l.movhi r5,hi(FLASH_BASE_ADDR)
106
        l.srai  r5,r5,6
107
        l.ori   r5,r5,0x0025
108
        l.sw    0(r4),r5
109
 
110
        l.addi  r4,r3,MC_TMS(0)
111
        l.movhi r5,hi(FLASH_TMS_VAL)
112
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
113
        l.sw    0(r4),r5
114
 
115
        l.addi  r4,r3,MC_BA_MASK
116
        l.addi  r5,r0,MC_MASK_VAL
117
        l.sw    0(r4),r5
118
 
119
        l.addi  r4,r3,MC_CSR
120
        l.movhi r5,hi(MC_CSR_VAL)
121
        l.ori   r5,r5,lo(MC_CSR_VAL)
122
        l.sw    0(r4),r5
123
 
124
        l.addi  r4,r3,MC_TMS(1)
125
        l.movhi r5,hi(SDRAM_TMS_VAL)
126
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
127
        l.sw    0(r4),r5
128
 
129
        l.addi  r4,r3,MC_CSC(1)
130
        l.movhi r5,hi(SDRAM_BASE_ADDR)
131
        l.srai  r5,r5,6
132
        l.ori   r5,r5,0x0411
133
        l.sw    0(r4),r5
134
 
135
        l.jr    r9
136
        l.nop
137
 
138
 
139
        .section .text
140
 
141 621 simons
_ic_enable:
142
        /* Disable IC */
143
        l.mfspr r13,r0,SPR_SR
144
        l.addi  r11,r0,-1
145
        l.xori  r11,r11,SPR_SR_ICE
146
        l.and   r11,r13,r11
147
        l.mtspr r0,r11,SPR_SR
148
 
149
        /* Invalidate IC */
150
        l.addi  r13,r0,0
151
        l.addi  r11,r0,8192
152
1:
153
        l.mtspr r0,r13,SPR_ICBIR
154
        l.sfne  r13,r11
155
        l.bf    1b
156
        l.addi  r13,r13,16
157
 
158
        /* Enable IC */
159
        l.mfspr r13,r0,SPR_SR
160
        l.ori   r13,r13,SPR_SR_ICE
161
        l.mtspr r0,r13,SPR_SR
162
        l.nop
163
        l.nop
164
        l.nop
165
        l.nop
166
        l.nop
167
 
168
        l.jr    r9
169
        l.nop
170
 
171
_ic_disable:
172
        /* Disable IC */
173
        l.mfspr r13,r0,SPR_SR
174
        l.addi  r11,r0,-1
175
        l.xori  r11,r11,SPR_SR_ICE
176
        l.and   r11,r13,r11
177
        l.mtspr r0,r11,SPR_SR
178
 
179
        l.jr    r9
180
        l.nop
181
 
182
_dc_enable:
183
        /* Disable DC */
184
        l.mfspr r13,r0,SPR_SR
185
        l.addi  r11,r0,-1
186
        l.xori  r11,r11,SPR_SR_DCE
187
        l.and   r11,r13,r11
188
        l.mtspr r0,r11,SPR_SR
189
 
190
        /* Flush DC */
191
        l.addi  r13,r0,0
192
        l.addi  r11,r0,8192
193
1:
194
        l.mtspr r0,r13,SPR_DCBIR
195
        l.sfne  r13,r11
196
        l.bf    1b
197
        l.addi  r13,r13,16
198
 
199
        /* Enable DC */
200
        l.mfspr r13,r0,SPR_SR
201
        l.ori   r13,r13,SPR_SR_DCE
202
        l.mtspr r0,r13,SPR_SR
203
 
204
        l.jr    r9
205
        l.nop
206
 
207
_dc_disable:
208
        /* Disable DC */
209
        l.mfspr r13,r0,SPR_SR
210
        l.addi  r11,r0,-1
211
        l.xori  r11,r11,SPR_SR_DCE
212
        l.and   r11,r13,r11
213
        l.mtspr r0,r11,SPR_SR
214
 
215
        l.jr    r9
216
        l.nop
217
 
218
_dc_inv:
219
        l.mfspr r4,r0,SPR_SR
220
        l.addi  r5,r0,-1
221
        l.xori  r5,r5,SPR_SR_DCE
222
        l.and   r5,r4,r5
223
        l.mtspr r0,r5,SPR_SR
224
        l.mtspr r0,r3,SPR_DCBIR
225
        l.mtspr r0,r4,SPR_SR
226
        l.jr    r9
227
        l.nop
228
 
229
        .align  0x10
230
_ic_inv_test:
231
        l.movhi r7,hi(_ic_test_1)
232
        l.ori   r7,r7,lo(_ic_test_1)
233
        l.addi  r3,r0,0
234
        l.addi  r4,r0,0
235
        l.addi  r5,r0,0
236
        l.nop
237
        l.nop
238
        l.nop
239
 
240
_ic_test_1:
241
3:      l.addi  r3,r3,1
242
 
243
        l.sfeqi r4,0x01
244
        l.bnf   1f
245
        l.nop
246
 
247
        l.mfspr r8,r0,SPR_SR
248
        l.addi  r11,r0,-1
249
        l.xori  r11,r11,SPR_SR_ICE
250
        l.and   r11,r8,r11
251
        l.mtspr r0,r11,SPR_SR
252
        l.mtspr r0,r7,SPR_ICBIR
253
        l.mtspr r0,r8,SPR_SR
254
        l.bf    2f
255
        l.nop
256
 
257
1:      l.lwz   r6,0(r7)
258
        l.addi  r6,r6,1
259
        l.sw    0(r7),r6
260
 
261
2:      l.addi  r5,r5,1
262
        l.sfeqi r5,10
263
        l.bnf   3b
264
        l.xori  r4,r4,0x01
265
 
266
        l.addi  r11,r3,0
267
        l.jr    r9
268
        l.nop
269
 
270
_dc_inv_test:
271
        l.movhi r4,hi(0x08040201)
272
        l.ori   r4,r4,lo(0x08040201)
273
        l.sw    0x00(r3),r4
274
        l.slli  r4,r4,1
275
        l.sw    0x14(r3),r4
276
        l.slli  r4,r4,1
277
        l.sw    0x28(r3),r4
278
 
279
        l.addi  r8,r9,0
280
        l.jal   _dc_enable
281
        l.nop
282
        l.addi  r9,r8,0
283
 
284
        l.lbz   r4,0x03(r3)
285
        l.lhz   r5,0x16(r3)
286
        l.add   r4,r4,r5
287
        l.lwz   r5,0x28(r3)
288
        l.add   r4,r4,r5
289
 
290
        l.mfspr r6,r0,SPR_SR
291
        l.addi  r5,r0,-1
292
        l.xori  r5,r5,SPR_SR_DCE
293
        l.and   r5,r6,r5
294
        l.mtspr r0,r5,SPR_SR
295
        l.addi  r7,r3,0x10
296
        l.mtspr r0,r7,SPR_DCBIR
297
 
298
        l.lwz   r5,0(r3)
299
        l.slli  r5,r5,3
300
        l.sw    0x00(r3),r5
301
        l.slli  r5,r5,1
302
        l.sw    0x14(r3),r5
303
        l.slli  r5,r5,1
304
        l.sw    0x28(r3),r5
305
 
306
        l.mtspr r0,r6,SPR_SR
307
 
308
        l.lbz   r5,0x03(r3)
309
        l.add   r4,r4,r5
310
        l.lhz   r5,0x16(r3)
311
        l.add   r4,r4,r5
312
        l.lwz   r5,0x28(r3)
313
        l.add   r4,r4,r5
314
 
315
        l.addi  r5,r0,-1
316
        l.xori  r5,r5,SPR_SR_DCE
317
        l.and   r5,r6,r5
318
        l.mtspr r0,r5,SPR_SR
319
 
320
        l.addi  r11,r4,0x0
321
1:
322
        l.jr  r9
323
        l.nop

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