OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [eth.c] - Blame information for rev 258

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 258 erez
/* Ethernet test */
2
 
3
#include "support.h"
4
 
5
typedef struct FILE FILE;
6
 
7
#include "../peripheral/fields.h"
8
#include "../peripheral/dma.h"
9
#include "../peripheral/ethernet.h"
10
 
11
#define ETH_BASE 0x88000000LU
12
#define DMA_BASE 0x90000000LU
13
 
14
typedef volatile unsigned long *REGISTER;
15
 
16
REGISTER eth_moder = (unsigned long *)(ETH_BASE + ETH_MODER),
17
        eth_int_source = (unsigned long *)(ETH_BASE + ETH_INT_SOURCE),
18
        eth_int_mask = (unsigned long *)(ETH_BASE + ETH_INT_MASK),
19
        eth_ipgt = (unsigned long *)(ETH_BASE + ETH_IPGT),
20
        eth_ipgr1 = (unsigned long *)(ETH_BASE + ETH_IPGR1),
21
        eth_ipgr2 = (unsigned long *)(ETH_BASE + ETH_IPGR2),
22
        eth_packetlen = (unsigned long *)(ETH_BASE + ETH_PACKETLEN),
23
        eth_collconf = (unsigned long *)(ETH_BASE + ETH_COLLCONF),
24
        eth_rx_bd_adr = (unsigned long *)(ETH_BASE + ETH_RX_BD_ADR),
25
        eth_controlmoder = (unsigned long *)(ETH_BASE + ETH_CTRLMODER),
26
        eth_miimoder = (unsigned long *)(ETH_BASE + ETH_MIIMODER),
27
        eth_miicommand = (unsigned long *)(ETH_BASE + ETH_MIICOMMAND),
28
        eth_miiaddress = (unsigned long *)(ETH_BASE + ETH_MIIADDRESS),
29
        eth_miitx_data = (unsigned long *)(ETH_BASE + ETH_MIITX_DATA),
30
        eth_miirx_data = (unsigned long *)(ETH_BASE + ETH_MIIRX_DATA),
31
        eth_miistatus = (unsigned long *)(ETH_BASE + ETH_MIISTATUS),
32
        eth_mac_addr0 = (unsigned long *)(ETH_BASE + ETH_MAC_ADDR0),
33
        eth_mac_addr1 = (unsigned long *)(ETH_BASE + ETH_MAC_ADDR1),
34
        eth_bd_base = (unsigned long *)(ETH_BASE + ETH_BD_BASE),
35
        dma_csr = (unsigned long *)(DMA_BASE + DMA_CSR),
36
        dma_int_msk_a = (unsigned long *)(DMA_BASE + DMA_INT_MSK_A),
37
        dma_int_msk_b = (unsigned long *)(DMA_BASE + DMA_INT_MSK_B),
38
        dma_int_src_a = (unsigned long *)(DMA_BASE + DMA_INT_SRC_A),
39
        dma_int_src_b = (unsigned long *)(DMA_BASE + DMA_INT_SRC_B),
40
        dma_ch0_csr = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_CSR),
41
        dma_ch0_sz = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_SZ),
42
        dma_ch0_a0 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_A0),
43
        dma_ch0_am0 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_AM0),
44
        dma_ch0_a1 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_A1),
45
        dma_ch0_am1 = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_AM1),
46
        dma_ch0_desc = (unsigned long *)(DMA_BASE + DMA_CH_BASE + DMA_CH_DESC);
47
 
48
struct DMA_DESCRIPTOR
49
{
50
        unsigned long csr;
51
        unsigned long adr0;
52
        unsigned long adr1;
53
        unsigned long next;
54
};
55
 
56
void transmit_one_packet( void )
57
{
58
        unsigned i;
59
        unsigned char packet[1003];
60
        struct DMA_DESCRIPTOR desc;
61
 
62
        /* Initialize packet */
63
        for ( i = 0; i < sizeof(packet); ++ i )
64
                packet[i] = (unsigned char)i;
65
 
66
        /* Set Ethernet BD size */
67
        *eth_bd_base = sizeof(packet) << ETH_TX_BD_LENGTH_OFFSET;
68
 
69
        /* Set dma stuff */
70
        desc.csr = 1600; /* transfer size; Ethernet will stop the DMA after packet is sent */
71
        desc.adr0 = (unsigned long)packet;
72
        desc.adr1 = ETH_BASE + ETH_DMA_RX_TX;
73
        desc.csr |= FLAG_MASK( DMA_DESC_CSR, EOL ) | FLAG_MASK( DMA_DESC_CSR, INC_SRC );
74
        desc.next = 0xDEADDEADUL; /* just to help debugging */
75
        *dma_ch0_sz = 1UL << DMA_CH_SZ_CHK_SZ_OFFSET; /* Chunk size = 1 word */
76
        *dma_ch0_desc = (unsigned long)&desc; /* Tell DMA channel where the descriptor is */
77
 
78
        /* Start DMA (it will wait for request from Ethernet) */
79
        *dma_ch0_csr = FLAG_MASK( DMA_CH_CSR, CH_EN ) /* Enable channel */ |
80
                FLAG_MASK( DMA_CH_CSR, USE_ED ) /* Use linked lists */ |
81
                FLAG_MASK( DMA_CH_CSR, MODE ) /* Wait for HW handshake */ |
82
                FLAG_MASK( DMA_CH_CSR, DST_SEL ) /* Interface 1 is the destination (meaningless for simulation) */;
83
 
84
        /* Start Ethernet */
85
        *eth_bd_base |= FLAG_MASK( ETH_TX_BD, READY ); /* signal BD as ready */
86
        *eth_moder |= FLAG_MASK( ETH_MODER, TXEN ) | FLAG_MASK( ETH_MODER, DMAEN );
87
 
88
        /* Now wait till DMA finishes */
89
        while ( TEST_FLAG( *dma_ch0_csr, DMA_CH_CSR, BUSY ) )
90
                ;
91
}
92
 
93
 
94
int main()
95
{
96
        printf( "Starting Ethernet test\n" );
97
 
98
        transmit_one_packet();
99
 
100
        printf( "Ending Ethernet test\n" );
101
 
102
        exit( 0 );
103
}
104
 
105
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.