OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [except.S] - Blame information for rev 342

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 342 markom 
/* Support file for c based tests */
2 
 
3 
        .section .except
4 
        .extern _reset_support
5 
        .extern _c_reset
6 
        .extern _excpt_buserr
7 
        .extern _excpt_dpfault
8 
        .extern _excpt_ipfault
9 
        .extern _excpt_lpint
10 
        .extern _excpt_align
11 
        .extern _excpt_illinsn
12 
        .extern _excpt_hpint
13 
        .extern _excpt_dtlbmiss
14 
        .extern _excpt_itlbmiss
15 
        .extern _excpt_range
16 
        .extern _excpt_syscall
17 
        .extern _excpt_break
18 
        .extern _excpt_trap
19 
 
20 
 
21 
        .org    0x100
22 
_reset_vector:
23 
        l.nop
24 
        l.nop
25 
        l.addi  r1,r0,0x7f00
26 
        l.jal   _reset
27 
        l.nop
28 
 
29 
        .org    0x200
30 
_buserr_vector:
31 
        l.addi  r1,r1,-116
32 
        l.sw    0x18(r1),r9
33 
        l.jal   store_regs
34 
        l.nop
35 
        l.movhi r9,hi(end_except)
36 
        l.ori   r9,r0,lo(end_except)
37 
        l.lwz   r10,_excpt_buserr(r0)
38 
        l.jr    r10
39 
        l.nop
40 
 
41 
        .org    0x300
42 
_dpfault_vector:
43 
        l.addi  r1,r1,-116
44 
        l.sw    0x18(r1),r9
45 
        l.jal   store_regs
46 
        l.nop
47 
        l.movhi r9,hi(end_except)
48 
        l.ori   r9,r0,lo(end_except)
49 
        l.lwz   r10,lo(_excpt_dpfault)(r0)
50 
        l.jr    r10
51 
        l.nop
52 
 
53 
        .org    0x400
54 
_ipfault_vector:
55 
        l.addi  r1,r1,-116
56 
        l.sw    0x18(r1),r9
57 
        l.jal   store_regs
58 
        l.nop
59 
        l.movhi r9,hi(end_except)
60 
        l.ori   r9,r0,lo(end_except)
61 
        l.lwz   r10,_excpt_ipfault(r0)
62 
        l.jr    r10
63 
        l.nop
64 
 
65 
        .org    0x500
66 
_lpint_vector:
67 
        l.addi  r1,r1,-116
68 
        l.sw    0x18(r1),r9
69 
        l.jal   store_regs
70 
        l.nop
71 
        l.movhi r9,hi(end_except)
72 
        l.ori   r9,r0,lo(end_except)
73 
        l.lwz   r10,_excpt_lpint(r0)
74 
        l.jr    r10
75 
        l.nop
76 
 
77 
        .org    0x600
78 
_align_vector:
79 
        l.addi  r1,r1,-116
80 
        l.sw    0x18(r1),r9
81 
        l.jal   store_regs
82 
        l.nop
83 
        l.movhi r9,hi(end_except)
84 
        l.ori   r9,r0,lo(end_except)
85 
        l.lwz   r10,_excpt_align(r0)
86 
        l.jr    r10
87 
        l.nop
88 
 
89 
        .org    0x700
90 
_illinsn_vector:
91 
        l.addi  r1,r1,-116
92 
        l.sw    0x18(r1),r9
93 
        l.jal   store_regs
94 
        l.nop
95 
        l.movhi r9,hi(end_except)
96 
        l.ori   r9,r0,lo(end_except)
97 
        l.lwz   r10,_excpt_illinsn(r0)
98 
        l.jr    r10
99 
        l.nop
100 
 
101 
        .org    0x800
102 
_hpint_vector:
103 
        l.addi  r1,r1,-116
104 
        l.sw    0x18(r1),r9
105 
        l.jal   store_regs
106 
        l.nop
107 
        l.movhi r9,hi(end_except)
108 
        l.ori   r9,r0,lo(end_except)
109 
        l.lwz   r10,_excpt_hpint(r0)
110 
        l.jr    r10
111 
        l.nop
112 
 
113 
        .org    0x900
114 
_dtlbmiss_vector:
115 
        l.addi  r1,r1,-116
116 
        l.sw    0x18(r1),r9
117 
        l.jal   store_regs
118 
        l.nop
119 
        l.movhi r9,hi(end_except)
120 
        l.ori   r9,r0,lo(end_except)
121 
        l.lwz   r10,_excpt_dtlbmiss(r0)
122 
        l.jr    r10
123 
        l.nop
124 
 
125 
        .org    0xa00
126 
_itlbmiss_vector:
127 
        l.addi  r1,r1,-116
128 
        l.sw    0x18(r1),r9
129 
        l.jal   store_regs
130 
        l.nop
131 
        l.movhi r9,hi(end_except)
132 
        l.ori   r9,r0,lo(end_except)
133 
        l.lwz   r10,_excpt_itlbmiss(r0)
134 
        l.jr    r10
135 
        l.nop
136 
 
137 
        .org    0xb00
138 
_range_vector:
139 
        l.addi  r1,r1,-116
140 
        l.sw    0x18(r1),r9
141 
        l.jal   store_regs
142 
        l.nop
143 
        l.movhi r9,hi(end_except)
144 
        l.ori   r9,r0,lo(end_except)
145 
        l.lwz   r10,_excpt_range(r0)
146 
        l.jr    r10
147 
        l.nop
148 
 
149 
        .org    0xc00
150 
_syscall_vector:
151 
        l.addi  r1,r1,-116
152 
        l.sw    0x18(r1),r9
153 
        l.jal   store_regs
154 
        l.nop
155 
        l.movhi r9,hi(end_except)
156 
        l.ori   r9,r0,lo(end_except)
157 
        l.lwz   r10,_excpt_syscall(r0)
158 
        l.jr    r10
159 
        l.nop
160 
 
161 
        .org    0xd00
162 
_break_vector:
163 
        l.addi  r1,r1,-116
164 
        l.sw    0x18(r1),r9
165 
        l.jal   store_regs
166 
        l.nop
167 
        l.movhi r9,hi(end_except)
168 
        l.ori   r9,r0,lo(end_except)
169 
        l.lwz   r10,_excpt_break(r0)
170 
        l.jr    r10
171 
        l.nop
172 
 
173 
        .org    0xe00
174 
_trap_vector:
175 
        l.addi  r1,r1,-116
176 
        l.sw    0x18(r1),r9
177 
        l.jal   store_regs
178 
        l.nop
179 
        l.movhi r9,hi(end_except)
180 
        l.ori   r9,r0,lo(end_except)
181 
        l.lwz   r10,_excpt_trap(r0)
182 
        l.jr    r10
183 
        l.nop
184 
 
185 
store_regs:
186 
        l.sw    0x00(r1),r3
187 
        l.sw    0x04(r1),r4
188 
        l.sw    0x08(r1),r5
189 
        l.sw    0x0c(r1),r6
190 
        l.sw    0x10(r1),r7
191 
        l.sw    0x14(r1),r8
192 
        l.sw    0x1c(r1),r10
193 
        l.sw    0x20(r1),r11
194 
        l.sw    0x24(r1),r12
195 
        l.sw    0x28(r1),r13
196 
        l.sw    0x2c(r1),r14
197 
        l.sw    0x30(r1),r15
198 
        l.sw    0x34(r1),r16
199 
        l.sw    0x38(r1),r17
200 
        l.sw    0x3c(r1),r18
201 
        l.sw    0x40(r1),r19
202 
        l.sw    0x44(r1),r20
203 
        l.sw    0x48(r1),r21
204 
        l.sw    0x4c(r1),r22
205 
        l.sw    0x50(r1),r23
206 
        l.sw    0x54(r1),r24
207 
        l.sw    0x58(r1),r25
208 
        l.sw    0x5c(r1),r26
209 
        l.sw    0x60(r1),r27
210 
        l.sw    0x64(r1),r28
211 
        l.sw    0x68(r1),r29
212 
        l.sw    0x6c(r1),r30
213 
        l.sw    0x70(r1),r31
214 
        l.jalr  r9
215 
        l.nop
216 
 
217 
end_except:
218 
        l.lwz   r3,0x00(r1)
219 
        l.lwz   r4,0x04(r1)
220 
        l.lwz   r5,0x08(r1)
221 
        l.lwz   r6,0x0c(r1)
222 
        l.lwz   r7,0x10(r1)
223 
        l.lwz   r8,0x14(r1)
224 
        l.lwz   r9,0x18(r1)
225 
        l.lwz   r10,0x1c(r1)
226 
        l.lwz   r11,0x20(r1)
227 
        l.lwz   r12,0x24(r1)
228 
        l.lwz   r13,0x28(r1)
229 
        l.lwz   r14,0x2c(r1)
230 
        l.lwz   r15,0x30(r1)
231 
        l.lwz   r16,0x34(r1)
232 
        l.lwz   r17,0x38(r1)
233 
        l.lwz   r18,0x3c(r1)
234 
        l.lwz   r19,0x40(r1)
235 
        l.lwz   r20,0x44(r1)
236 
        l.lwz   r21,0x48(r1)
237 
        l.lwz   r22,0x4c(r1)
238 
        l.lwz   r23,0x50(r1)
239 
        l.lwz   r24,0x54(r1)
240 
        l.lwz   r25,0x58(r1)
241 
        l.lwz   r26,0x5c(r1)
242 
        l.lwz   r27,0x60(r1)
243 
        l.lwz   r28,0x64(r1)
244 
        l.lwz   r29,0x68(r1)
245 
        l.lwz   r30,0x6c(r1)
246 
        l.lwz   r31,0x70(r1)
247 
        l.addi  r1,r1,116
248 
        l.rfe
249 
        l.nop

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.