OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [int_test.S] - Blame information for rev 956

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 576 markom 
/* Within the test we'll use following global variables:
2 
 
3 
   r16 interrupt counter
4 
   r17 current tick timer comparison counter
5 
   r18 sanity counter
6 
   r19 loop counter
7 
   r20 temp value of SR reg
8 
   r21 temp value of TTMR reg.
9 
   r23 RAM_START
10 
 
11 
   r25-r31 used by int handler
12 
 
13 
   The test do the following:
14 
   We set up the tick timer to trigger once and then we trigger interrupts incrementally
15 
   on every cycle in the specified test program; on interrupt handler we check if data computed
16 
   so far exactly matches precalculated values. If interrupt has returned incorreclty, we can
17 
   detect this using assertion routine at the end.
18 
*/
19 
 
20 
#include "spr_defs.h"
21 
#define  RAM_START 0x40000000
22 
 
23 956 simons 
.section .except, "ax"
24 576 markom 
.org 0x100
25 
  l.j     _main
26 
  l.nop
27 
 
28 600 simons 
.org 0x500
29 576 markom 
#
30 600 simons 
# Tick timer exception handler
31 576 markom 
#
32 
 
33 
  l.addi  r31,r3,0
34 
# get interrupted program pc
35 
  l.mfspr r25,r0,SPR_EPCR_BASE
36 
 
37 
# calculate instruction address
38 
  l.movhi r26,hi(_ie_start)
39 
  l.ori   r26,r26,lo(_ie_start)
40 
  l.addi  r3,r25,0    #print insn index
41 
  l.nop   2
42 
  l.sub   r25,r25,r26
43 
  l.addi  r3,r25,0    #print insn index
44 
  l.nop   2
45 
 
46 
  l.addi  r3,r31,0    # restore r3
47 
  l.sfeqi r25, 0x00
48 
  l.bf    _i00
49 
  l.sfeqi r25, 0x04
50 
  l.bf    _i04
51 
  l.sfeqi r25, 0x08
52 
  l.bf    _i08
53 
  l.sfeqi r25, 0x0c
54 
  l.bf    _i0c
55 
  l.sfeqi r25, 0x10
56 
  l.bf    _i10
57 
  l.sfeqi r25, 0x14
58 
  l.bf    _i14
59 
  l.sfeqi r25, 0x18
60 
  l.bf    _i18
61 
  l.sfeqi r25, 0x1c
62 
  l.bf    _i1c
63 
  l.sfeqi r25, 0x20
64 
  l.bf    _i20
65 
  l.sfeqi r25, 0x24
66 
  l.bf    _i24
67 
  l.sfeqi r25, 0x28
68 
  l.bf    _i28
69 
  l.sfeqi r25, 0x2c
70 
  l.bf    _i2c
71 
  l.sfeqi r25, 0x30
72 
  l.bf    _i30
73 
  l.sfeqi r25, 0x34
74 
  l.bf    _i34
75 
  l.sfeqi r25, 0x38
76 
  l.bf    _i38
77 
  l.nop
78 
 
79 
# value not defined
80 
_die:
81 
  l.nop   2             #print r3
82 
 
83 
  l.addi  r3,r0,0xeeee
84 
  l.nop   2
85 
  l.addi  r3,r0,1
86 
  l.nop   1
87 
1:
88 
  l.j     1b
89 
  l.nop
90 
 
91 
.section  .text
92 
_main:
93 
        l.nop
94 600 simons 
  l.addi  r3,r0,SPR_SR_SM
95 
  l.mtspr r0,r3,SPR_SR
96 576 markom 
        l.nop
97 
 
98 
#
99 
# set tick counter to initial 3 cycles
100 
#
101 
  l.addi r16,r0,0
102 
  l.addi r17,r0,1
103 
  l.addi r18,r0,0
104 
  l.addi r19,r0,0
105 
  l.addi r22,r0,0
106 
 
107 
  l.movhi r23,hi(RAM_START)
108 
  l.ori   r23,r23,lo(RAM_START)
109 
 
110 600 simons 
# Set r20 to hold enable tick exception
111 576 markom 
        l.mfspr r20,r0,SPR_SR
112 600 simons 
        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
113 576 markom 
 
114 
# Set r21 to hold value of TTMR
115 
        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
116 
        l.add  r21,r5,r17
117 
 
118 
#
119 
# MAIN LOOP
120 
#
121 
_main_loop:
122 
# reinitialize memory and registers
123 
  l.addi  r3,r0,0xaaaa
124 
  l.addi  r9,r0,0xbbbb
125 
  l.sw    0(r23),r3
126 
  l.sw    4(r23),r9
127 
  l.sw    8(r23),r3
128 
 
129 
# Reinitializes tick timer
130 
  l.addi  r17,r17,1
131 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
132 
  l.mtspr r0,r21,SPR_TTMR               # set TTMR
133 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
134 
        l.addi  r21,r21,1
135 
 
136 
# Enable exceptions and interrupts
137 
        l.mtspr r0,r20,SPR_SR   # set SR
138 
 
139 
##### TEST CODE #####
140 
_ie_start:
141 
  l.movhi r3,0x1234         #00
142 
  l.sw    0(r23),r3         #04
143 
  l.movhi r3,hi(RAM_START)  #08
144 
  l.lwz   r3,0(r3)          #0c
145 
  l.movhi r3,hi(RAM_START)  #10
146 
  l.addi  r3,r3,4           #14
147 
  l.j     1f                #18
148 
  l.lwz   r3,0(r3)          #1c
149 
  l.addi  r3,r3,1           #20
150 
1:
151 
  l.sfeqi r3,0xdead         #24
152 
  l.jal   2f                #28
153 
  l.addi  r3,r0,0x5678      #2c
154 
 
155 
_return_addr:
156 
2:
157 
  l.bf    _die              #30
158 
  l.sw    8(r23),r3         #34
159 
_ie_end:
160 
  l.nop                     #38
161 
##### END OF TEST CODE #####
162 
 
163 
# do some testing
164 
 
165 
  l.j     _main_loop
166 
  l.nop
167 
 
168 
_i00:
169 
  l.sfeqi r3,0xaaaa
170 
  l.bnf   _die
171 
  l.nop
172 
  l.j     _resume
173 
  l.nop
174 
_i04:
175 
  l.movhi  r26,0x1234
176 
  l.sfeq   r3,r26
177 
  l.bnf   _die
178 
  l.nop
179 
  l.lwz   r26,0(r23)
180 
  l.sfeqi r26,0xaaaa
181 
  l.bnf   _die
182 
  l.nop
183 
  l.j     _resume
184 
  l.nop
185 
_i08:
186 
  l.movhi r26,0x1234
187 
  l.sfeq  r3,r26
188 
  l.bnf   _die
189 
  l.nop
190 
  l.lwz   r27,0(r23)
191 
  l.sfeq  r27,r26
192 
  l.bnf   _die
193 
  l.nop
194 
  l.j     _resume
195 
  l.nop
196 
_i0c:
197 
  l.sfeq  r3,r23
198 
  l.bnf   _die
199 
  l.nop
200 
  l.j     _resume
201 
  l.nop
202 
_i10:
203 
  l.movhi r26,0x1234
204 
  l.sfeq  r26,r3
205 
  l.bnf   _die
206 
  l.nop
207 
  l.j     _resume
208 
  l.nop
209 
_i14:
210 
  l.sfeq  r3,r23
211 
  l.bnf   _die
212 
  l.nop
213 
  l.j     _resume
214 
  l.nop
215 
_i18:
216 
  l.addi  r26,r23,4
217 
  l.sfeq  r3,r26
218 
  l.bnf   _die
219 
  l.nop
220 
  l.j     _resume
221 
  l.nop
222 
_i1c:
223 
  l.j     _die
224 
  l.nop
225 
_i20:
226 
  l.j     _die
227 
  l.nop
228 
_i24:
229 
  l.mfspr r26,r0,SPR_ESR_BASE
230 
  l.addi  r30,r3,0
231 
  l.addi  r3,r26,0
232 
  l.nop   2
233 
  l.addi  r3,r30,0
234 
  l.andi  r26,r26,SPR_SR_F
235 
  l.sfeq  r26,r0
236 619 markom 
  l.bnf   _die
237 576 markom 
  l.nop
238 
  l.sfeqi  r3,0xbbbb
239 
  l.bnf   _die
240 
  l.nop
241 
  l.j     _resume
242 
  l.nop
243 
_i28:
244 
  l.mfspr r26,r0,SPR_ESR_BASE
245 
  l.addi  r30,r3,0
246 
  l.addi  r3,r26,0
247 
  l.nop   2
248 
  l.addi  r3,r30,0
249 
  l.andi  r26,r26,SPR_SR_F
250 
  l.sfeq  r26,r0
251 
  l.bnf    _die
252 
  l.nop
253 
  l.sfeqi  r22,1
254 
  l.bf     _resume
255 
  l.addi   r22,r0,1
256 
  l.sfeqi  r9,0xbbbb
257 
  l.bnf   _die
258 
  l.nop
259 
  l.j     _resume
260 
  l.nop
261 
_i2c:
262 
  l.movhi  r26,hi(_return_addr)
263 
  l.ori    r26,r26,lo(_return_addr)
264 
  l.sfeq   r9,r26
265 
  l.bnf   _die
266 
  l.nop
267 
  l.sfeqi  r3,0xbbbb
268 
  l.bnf   _die
269 
  l.nop
270 
  l.j     _resume
271 
  l.nop
272 
_i30:
273 
  l.sfeqi  r3,0x5678
274 
  l.bnf   _die
275 
  l.nop
276 
  l.j     _resume
277 
  l.nop
278 
_i34:
279 
  l.sfeqi  r3,0x5678
280 
  l.bnf   _die
281 
  l.nop
282 
  l.lwz    r26,8(r23)
283 
  l.sfeqi  r26,0xaaaa
284 
  l.bnf   _die
285 
  l.nop
286 
  l.j     _resume
287 
  l.nop
288 
_i38:
289 
  l.lwz    r26,8(r23)
290 
  l.sfeqi  r26,0x5678
291 
  l.bnf   _die
292 
  l.nop
293 
#
294 
# mark finished ok
295 
#
296 
  l.movhi r3,hi(0xdeaddead)
297 
  l.ori   r3,r3,lo(0xdeaddead)
298 
  l.nop   2
299 
  l.addi  r3,r0,0
300 
  l.nop   1
301 
_ok:
302 
  l.j     _ok
303 
  l.nop
304 
 
305 
_resume:
306 
  l.mfspr  r27,r0,SPR_ESR_BASE
307 600 simons 
  l.addi   r26,r0,SPR_SR_TEE
308 576 markom 
  l.addi   r28,r0,-1
309 
  l.xor    r26,r26,r28
310 
  l.and    r26,r26,r27
311 
  l.mtspr  r0,r26,SPR_ESR_BASE
312 
 
313 
  l.rfe
314 
  l.addi    r3,r3,5         # should not be executed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.