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/* This file is part of test microkernel for OpenRISC 1000. */
/* (C) 2000 Damjan Lampret, lampret@opencores.org */
 
#include "spr_defs.h"
#include "../board.h"
 
#define MC_CSR          (0x00)
#define MC_POC          (0x04)
#define MC_BA_MASK      (0x08)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
 
 
/*
 * Context is saved to area pointed by pointer in R3. Original
 * R3 is at memory location 0 and task's PC is at memory location 4.
 */
#define SAVEREGS                                        \
        l.lwz   r3,0(r3);                               \
        l.sw    4(r3),r1;                               \
        l.sw    8(r3),r2;                               \
        l.lwz   r2,0(r0);       /* saving original r3*/ \
        l.sw    12(r3),r2;                              \
        l.sw    16(r3),r4;                              \
        l.sw    20(r3),r5;                              \
        l.sw    24(r3),r6;                              \
        l.sw    28(r3),r7;                              \
        l.sw    32(r3),r8;                              \
        l.sw    36(r3),r9;                              \
        l.sw    40(r3),r10;                             \
        l.sw    44(r3),r11;                             \
        l.sw    48(r3),r12;                             \
        l.sw    52(r3),r13;                             \
        l.sw    56(r3),r14;                             \
        l.sw    60(r3),r15;                             \
        l.sw    64(r3),r16;                             \
        l.sw    68(r3),r17;                             \
        l.sw    72(r3),r18;                             \
        l.sw    76(r3),r19;                             \
        l.sw    80(r3),r20;                             \
        l.sw    84(r3),r21;                             \
        l.sw    88(r3),r22;                             \
        l.sw    92(r3),r23;                             \
        l.sw    96(r3),r24;                             \
        l.sw    100(r3),r25;                            \
        l.sw    104(r3),r26;                            \
        l.sw    108(r3),r27;                            \
        l.sw    112(r3),r28;                            \
        l.sw    116(r3),r29;                            \
        l.sw    120(r3),r30;                            \
        l.sw    124(r3),r31;                            \
        l.lwz   r2,4(r0);       /* saving original PC*/ \
        l.sw    0(r3),r2;                               \
                                                        \
        l.mfspr r2,r0,SPR_ESR_BASE;                             \
        l.sw    128(r3),r2      /* saving SR */
 
/*
 * Pointer to context is in R3. All registers are loaded and execution is
 * transfered to the loaded context's task
 */
#define LOADREGS_N_GO                           \
        l.lwz   r3,0(r3);                       \
        l.lwz   r2,0(r3);       /* prepare PC*/ \
        l.mtspr r0,r2,SPR_EPCR_BASE;            \
                                                \
        l.lwz   r2,128(r3);     /* prepare SR*/ \
        l.mtspr r0,r2,SPR_ESR_BASE;                     \
                                                \
        l.lwz   r1,4(r3);                       \
        l.lwz   r2,8(r3);                       \
        l.lwz   r4,16(r3);                      \
        l.lwz   r5,20(r3);                      \
        l.lwz   r6,24(r3);                      \
        l.lwz   r7,28(r3);                      \
        l.lwz   r8,32(r3);                      \
        l.lwz   r9,36(r3);                      \
        l.lwz   r10,40(r3);                     \
        l.lwz   r11,44(r3);                     \
        l.lwz   r12,48(r3);                     \
        l.lwz   r13,52(r3);                     \
        l.lwz   r14,56(r3);                     \
        l.lwz   r15,60(r3);                     \
        l.lwz   r16,64(r3);                     \
        l.lwz   r17,68(r3);                     \
        l.lwz   r18,72(r3);                     \
        l.lwz   r19,76(r3);                     \
        l.lwz   r20,80(r3);                     \
        l.lwz   r21,84(r3);                     \
        l.lwz   r22,88(r3);                     \
        l.lwz   r23,92(r3);                     \
        l.lwz   r24,96(r3);                     \
        l.lwz   r25,100(r3);                    \
        l.lwz   r26,104(r3);                    \
        l.lwz   r27,108(r3);                    \
        l.lwz   r28,112(r3);                    \
        l.lwz   r29,116(r3);                    \
        l.lwz   r30,120(r3);                    \
        l.lwz   r31,124(r3);                    \
                                                \
        l.lwz   r3,12(r3);      /* prepare r3*/ \
                                                \
        l.rfe;                  /* Call task */ \
        l.nop
 
/*
 * All registers are loaded from save area.
 */
#define LOADREGS                                \
        l.lwz   r3,0(r3);                       \
        l.lwz   r2,0(r3);       /* prepare PC*/ \
        l.mtspr r0,r2,SPR_EPCR_BASE;            \
                                                \
        l.lwz   r2,128(r3);     /* prepare SR*/ \
        l.mtspr r0,r2,SPR_ESR_BASE;                     \
                                                \
        l.lwz   r1,4(r3);                       \
        l.lwz   r2,8(r3);                       \
        l.lwz   r4,16(r3);                      \
        l.lwz   r5,20(r3);                      \
        l.lwz   r6,24(r3);                      \
        l.lwz   r7,28(r3);                      \
        l.lwz   r8,32(r3);                      \
        l.lwz   r9,36(r3);                      \
        l.lwz   r10,40(r3);                     \
        l.lwz   r11,44(r3);                     \
        l.lwz   r12,48(r3);                     \
        l.lwz   r13,52(r3);                     \
        l.lwz   r14,56(r3);                     \
        l.lwz   r15,60(r3);                     \
        l.lwz   r16,64(r3);                     \
        l.lwz   r17,68(r3);                     \
        l.lwz   r18,72(r3);                     \
        l.lwz   r19,76(r3);                     \
        l.lwz   r20,80(r3);                     \
        l.lwz   r21,84(r3);                     \
        l.lwz   r22,88(r3);                     \
        l.lwz   r23,92(r3);                     \
        l.lwz   r24,96(r3);                     \
        l.lwz   r25,100(r3);                    \
        l.lwz   r26,104(r3);                    \
        l.lwz   r27,108(r3);                    \
        l.lwz   r28,112(r3);                    \
        l.lwz   r29,116(r3);                    \
        l.lwz   r30,120(r3);                    \
        l.lwz   r31,124(r3);                    \
                                                \
        l.lwz   r3,12(r3);      /* prepare r3*/
 
/*
 * Set new PC in saved context
 */
#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG)   \
        l.lwz   AREA,0(AREA);                   \
        l.movhi TMPREG,hi(SUBROUTINE);          \
        l.addi  TMPREG,r0,lo(SUBROUTINE);       \
        l.sw    0(AREA),TMPREG;
 
/*
 * Printf via or1ksim hook
 */
#if KERNEL_OUTPUT
#define PRINTF(REG,STR)                         \
        l.movhi REG,hi(STR);                    \
        l.addi  REG,r0,lo(STR);                 \
        l.nop   NOP_PRINTF
#else
#define PRINTF(REG,STR)
#endif
 
/*
 * Reset Exception handler
 */
.org 0x100
_reset_vector:
 
  l.movhi r3,hi(MC_BASE_ADDR)
  l.ori   r3,r3,lo(MC_BASE_ADDR)
 
  l.addi  r4,r3,MC_CSC(0)
  l.movhi r5,hi(FLASH_BASE_ADDR)
  l.srai  r5,r5,6
  l.ori   r5,r5,0x0025
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_TMS(0)
  l.movhi r5,hi(FLASH_TMS_VAL)
  l.ori   r5,r5,lo(FLASH_TMS_VAL)
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_BA_MASK
  l.addi  r5,r0,MC_MASK_VAL
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_CSR
  l.movhi r5,hi(MC_CSR_VAL)
  l.ori   r5,r5,lo(MC_CSR_VAL)
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_TMS(1)
  l.movhi r5,hi(SDRAM_TMS_VAL)
  l.ori   r5,r5,lo(SDRAM_TMS_VAL)
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_CSC(1)
  l.movhi r5,hi(SDRAM_BASE_ADDR)
  l.srai  r5,r5,6
  l.ori   r5,r5,0x0411
  l.sw    0(r4),r5
 
  l.jr    r9
  l.nop
 
  /* Copy data section */
  l.movhi r3,hi(_src_beg)
  l.ori   r3,r3,lo(_src_beg)
  l.addi  r4,r0,0x200
  l.movhi r5,hi(_except_end)
  l.ori   r5,r5,lo(_except_end)
  l.movhi r6,hi(_except_beg)
  l.ori   r6,r6,lo(_except_beg)
  l.sub   r5,r6,r5
1:
  l.lwz   r6,0(r3)
  l.sw    0(r4),r6
  l.addi  r3,r3,4
  l.addi  r4,r4,4
  l.addi  r5,r5,-4
  l.sfgtsi r5,0
  l.bf    1b
  l.nop
 
  l.movhi r4,hi(_dst_beg)
  l.ori   r4,r4,lo(_dst_beg)
  l.movhi r5,hi(_dst_end)
  l.ori   r5,r5,lo(_dst_end)
  l.sub   r5,r5,r4
  l.sfeqi r5,0
  l.bf    2f
  l.nop
1:
  l.lwz   r6,0(r3)
  l.sw    0(r4),r6
  l.addi  r3,r3,4
  l.addi  r4,r4,4
  l.addi  r5,r5,-4
  l.sfgtsi r5,0
  l.bf          1b
  l.nop
 
2:
 
 
  l.movhi r2,hi(_reset)
  l.ori   r2,r2,lo(_reset)
  l.jr    r2
  l.nop
 
/*
 * Switch to a new context pointed by _task_context
 */
.global _dispatch
.align 4
_dispatch:
        /* load user task GPRs and PC */
        l.movhi r3,hi(_task_context)
        l.addi  r3,r0,lo(_task_context)
        LOADREGS_N_GO
 
.section .except, "ax"
 
/*
 * Bus Error Exception handler
 */
.org 0x0200
_buserr:
        l.nop
        l.sw    0(r0),r3        /* Save r3 */
        PRINTF(r3, _buserr_str)
_hang:
        l.j     _hang
        l.nop
 
_buserr_str:
        .ascii  "Bus error exception.\n\000"
 
/*
 * External Interrupt Exception handler
 */
.org 0x800
_extint:
        l.nop
        l.sw    0(r0),r3        /* Save r3 */
        PRINTF(r3,_extint_str)
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPCR */
        l.sw    4(r0),r3        /* and save it */
 
        /* now save user task context */
        l.movhi r3,hi(_task_context)
        l.addi  r3,r0,lo(_task_context)
        SAVEREGS
 
        /* set kernel context's PC to kernel's scheduler */
        l.movhi r3,hi(_kernel_context)
        l.addi  r3,r0,lo(_kernel_context)
        SET_CONTEXTPC(r3,_int_main,r4)
 
        /* load kernel context */
        l.movhi r3,hi(_kernel_context)
        l.addi  r3,r0,lo(_kernel_context)
        LOADREGS
 
        l.movhi r3,hi(_int_main)
        l.addi  r3,r0,lo(_int_main)
        l.jr    r3
        l.nop
 
_extint_str:
        .ascii  "External interrupt exception.\n\000"
 
/*
 * System Call Exception handler
 */
.org 0x0c00
_syscall:
        l.nop
        l.sw    0(r0),r3        /* Save r3 */
        PRINTF(r3,_syscall_str)
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPCR */
        l.addi  r3,r3,4         /* increment because EPCR instruction was already executed */
        l.sw    4(r0),r3        /* and save it */
 
        /* now save user task context */
        l.movhi r3,hi(_task_context)
        l.addi  r3,r0,lo(_task_context)
        SAVEREGS
 
        /* set kernel context's PC to kernel's syscall entry */
        l.movhi r3,hi(_kernel_context)
        l.addi  r3,r0,lo(_kernel_context)
        SET_CONTEXTPC(r3,_kernel_syscall,r4)
 
        /* load kernel context */
        l.movhi r3,hi(_kernel_context)
        l.addi  r3,r0,lo(_kernel_context)
        LOADREGS_N_GO
 
_syscall_str:
        .ascii  "System call exception.\n\000"
 
 

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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [uos/] [except_or32.S] - Blame information for rev 1646

Line No.	Rev	Author	Line
1	222	markom	`/* This file is part of test microkernel for OpenRISC 1000. */`
2			`/* (C) 2000 Damjan Lampret, lampret@opencores.org */`
3
4			`#include "spr_defs.h"`
5	970	simons	`#include "../board.h"`
6	222	markom
7	970	simons	`#define MC_CSR (0x00)`
8			`#define MC_POC (0x04)`
9			`#define MC_BA_MASK (0x08)`
10			`#define MC_CSC(i) (0x10 + (i) * 8)`
11			`#define MC_TMS(i) (0x14 + (i) * 8)`
12
13
14	222	markom	`/*`
15			`* Context is saved to area pointed by pointer in R3. Original`
16			`* R3 is at memory location 0 and task's PC is at memory location 4.`
17			`*/`
18			`#define SAVEREGS \`
19			`l.lwz r3,0(r3); \`
20			`l.sw 4(r3),r1; \`
21			`l.sw 8(r3),r2; \`
22			`l.lwz r2,0(r0); /* saving original r3*/ \`
23			`l.sw 12(r3),r2; \`
24			`l.sw 16(r3),r4; \`
25			`l.sw 20(r3),r5; \`
26			`l.sw 24(r3),r6; \`
27			`l.sw 28(r3),r7; \`
28			`l.sw 32(r3),r8; \`
29			`l.sw 36(r3),r9; \`
30			`l.sw 40(r3),r10; \`
31			`l.sw 44(r3),r11; \`
32			`l.sw 48(r3),r12; \`
33			`l.sw 52(r3),r13; \`
34			`l.sw 56(r3),r14; \`
35			`l.sw 60(r3),r15; \`
36			`l.sw 64(r3),r16; \`
37			`l.sw 68(r3),r17; \`
38			`l.sw 72(r3),r18; \`
39			`l.sw 76(r3),r19; \`
40			`l.sw 80(r3),r20; \`
41			`l.sw 84(r3),r21; \`
42			`l.sw 88(r3),r22; \`
43			`l.sw 92(r3),r23; \`
44			`l.sw 96(r3),r24; \`
45			`l.sw 100(r3),r25; \`
46			`l.sw 104(r3),r26; \`
47			`l.sw 108(r3),r27; \`
48			`l.sw 112(r3),r28; \`
49			`l.sw 116(r3),r29; \`
50			`l.sw 120(r3),r30; \`
51			`l.sw 124(r3),r31; \`
52			`l.lwz r2,4(r0); /* saving original PC*/ \`
53			`l.sw 0(r3),r2; \`
54			`\`
55			`l.mfspr r2,r0,SPR_ESR_BASE; \`
56			`l.sw 128(r3),r2 /* saving SR */`
57
58			`/*`
59			`* Pointer to context is in R3. All registers are loaded and execution is`
60			`* transfered to the loaded context's task`
61			`*/`
62			`#define LOADREGS_N_GO \`
63			`l.lwz r3,0(r3); \`
64			`l.lwz r2,0(r3); /* prepare PC*/ \`
65			`l.mtspr r0,r2,SPR_EPCR_BASE; \`
66			`\`
67			`l.lwz r2,128(r3); /* prepare SR*/ \`
68			`l.mtspr r0,r2,SPR_ESR_BASE; \`
69			`\`
70			`l.lwz r1,4(r3); \`
71			`l.lwz r2,8(r3); \`
72			`l.lwz r4,16(r3); \`
73			`l.lwz r5,20(r3); \`
74			`l.lwz r6,24(r3); \`
75			`l.lwz r7,28(r3); \`
76			`l.lwz r8,32(r3); \`
77			`l.lwz r9,36(r3); \`
78			`l.lwz r10,40(r3); \`
79			`l.lwz r11,44(r3); \`
80			`l.lwz r12,48(r3); \`
81			`l.lwz r13,52(r3); \`
82			`l.lwz r14,56(r3); \`
83			`l.lwz r15,60(r3); \`
84			`l.lwz r16,64(r3); \`
85			`l.lwz r17,68(r3); \`
86			`l.lwz r18,72(r3); \`
87			`l.lwz r19,76(r3); \`
88			`l.lwz r20,80(r3); \`
89			`l.lwz r21,84(r3); \`
90			`l.lwz r22,88(r3); \`
91			`l.lwz r23,92(r3); \`
92			`l.lwz r24,96(r3); \`
93			`l.lwz r25,100(r3); \`
94			`l.lwz r26,104(r3); \`
95			`l.lwz r27,108(r3); \`
96			`l.lwz r28,112(r3); \`
97			`l.lwz r29,116(r3); \`
98			`l.lwz r30,120(r3); \`
99			`l.lwz r31,124(r3); \`
100			`\`
101			`l.lwz r3,12(r3); /* prepare r3*/ \`
102			`\`
103			`l.rfe; /* Call task */ \`
104			`l.nop`
105
106			`/*`
107			`* All registers are loaded from save area.`
108			`*/`
109			`#define LOADREGS \`
110			`l.lwz r3,0(r3); \`
111			`l.lwz r2,0(r3); /* prepare PC*/ \`
112			`l.mtspr r0,r2,SPR_EPCR_BASE; \`
113			`\`
114			`l.lwz r2,128(r3); /* prepare SR*/ \`
115			`l.mtspr r0,r2,SPR_ESR_BASE; \`
116			`\`
117			`l.lwz r1,4(r3); \`
118			`l.lwz r2,8(r3); \`
119			`l.lwz r4,16(r3); \`
120			`l.lwz r5,20(r3); \`
121			`l.lwz r6,24(r3); \`
122			`l.lwz r7,28(r3); \`
123			`l.lwz r8,32(r3); \`
124			`l.lwz r9,36(r3); \`
125			`l.lwz r10,40(r3); \`
126			`l.lwz r11,44(r3); \`
127			`l.lwz r12,48(r3); \`
128			`l.lwz r13,52(r3); \`
129			`l.lwz r14,56(r3); \`
130			`l.lwz r15,60(r3); \`
131			`l.lwz r16,64(r3); \`
132			`l.lwz r17,68(r3); \`
133			`l.lwz r18,72(r3); \`
134			`l.lwz r19,76(r3); \`
135			`l.lwz r20,80(r3); \`
136			`l.lwz r21,84(r3); \`
137			`l.lwz r22,88(r3); \`
138			`l.lwz r23,92(r3); \`
139			`l.lwz r24,96(r3); \`
140			`l.lwz r25,100(r3); \`
141			`l.lwz r26,104(r3); \`
142			`l.lwz r27,108(r3); \`
143			`l.lwz r28,112(r3); \`
144			`l.lwz r29,116(r3); \`
145			`l.lwz r30,120(r3); \`
146			`l.lwz r31,124(r3); \`
147			`\`
148			`l.lwz r3,12(r3); /* prepare r3*/`
149
150			`/*`
151			`* Set new PC in saved context`
152			`*/`
153			`#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG) \`
154			`l.lwz AREA,0(AREA); \`
155			`l.movhi TMPREG,hi(SUBROUTINE); \`
156			`l.addi TMPREG,r0,lo(SUBROUTINE); \`
157			`l.sw 0(AREA),TMPREG;`
158
159			`/*`
160			`* Printf via or1ksim hook`
161			`*/`
162			`#if KERNEL_OUTPUT`
163			`#define PRINTF(REG,STR) \`
164			`l.movhi REG,hi(STR); \`
165			`l.addi REG,r0,lo(STR); \`
166	511	markom	`l.nop NOP_PRINTF`
167	222	markom	`#else`
168			`#define PRINTF(REG,STR)`
169			`#endif`
170
171			`/*`
172			`* Reset Exception handler`
173			`*/`
174			`.org 0x100`
175			`_reset_vector:`
176	970	simons
177			`l.movhi r3,hi(MC_BASE_ADDR)`
178			`l.ori r3,r3,lo(MC_BASE_ADDR)`
179
180			`l.addi r4,r3,MC_CSC(0)`
181			`l.movhi r5,hi(FLASH_BASE_ADDR)`
182			`l.srai r5,r5,6`
183			`l.ori r5,r5,0x0025`
184			`l.sw 0(r4),r5`
185
186			`l.addi r4,r3,MC_TMS(0)`
187			`l.movhi r5,hi(FLASH_TMS_VAL)`
188			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
189			`l.sw 0(r4),r5`
190
191			`l.addi r4,r3,MC_BA_MASK`
192			`l.addi r5,r0,MC_MASK_VAL`
193			`l.sw 0(r4),r5`
194
195			`l.addi r4,r3,MC_CSR`
196			`l.movhi r5,hi(MC_CSR_VAL)`
197			`l.ori r5,r5,lo(MC_CSR_VAL)`
198			`l.sw 0(r4),r5`
199
200			`l.addi r4,r3,MC_TMS(1)`
201			`l.movhi r5,hi(SDRAM_TMS_VAL)`
202			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
203			`l.sw 0(r4),r5`
204
205			`l.addi r4,r3,MC_CSC(1)`
206			`l.movhi r5,hi(SDRAM_BASE_ADDR)`
207			`l.srai r5,r5,6`
208			`l.ori r5,r5,0x0411`
209			`l.sw 0(r4),r5`
210
211			`l.jr r9`
212			`l.nop`
213
214			`/* Copy data section */`
215			`l.movhi r3,hi(_src_beg)`
216			`l.ori r3,r3,lo(_src_beg)`
217			`l.addi r4,r0,0x200`
218			`l.movhi r5,hi(_except_end)`
219			`l.ori r5,r5,lo(_except_end)`
220			`l.movhi r6,hi(_except_beg)`
221			`l.ori r6,r6,lo(_except_beg)`
222			`l.sub r5,r6,r5`
223			`1:`
224			`l.lwz r6,0(r3)`
225			`l.sw 0(r4),r6`
226			`l.addi r3,r3,4`
227			`l.addi r4,r4,4`
228			`l.addi r5,r5,-4`
229			`l.sfgtsi r5,0`
230			`l.bf 1b`
231			`l.nop`
232
233			`l.movhi r4,hi(_dst_beg)`
234			`l.ori r4,r4,lo(_dst_beg)`
235			`l.movhi r5,hi(_dst_end)`
236			`l.ori r5,r5,lo(_dst_end)`
237			`l.sub r5,r5,r4`
238			`l.sfeqi r5,0`
239			`l.bf 2f`
240			`l.nop`
241			`1:`
242			`l.lwz r6,0(r3)`
243			`l.sw 0(r4),r6`
244			`l.addi r3,r3,4`
245			`l.addi r4,r4,4`
246			`l.addi r5,r5,-4`
247			`l.sfgtsi r5,0`
248			`l.bf 1b`
249			`l.nop`
250
251			`2:`
252
253
254	511	markom	`l.movhi r2,hi(_reset)`
255			`l.ori r2,r2,lo(_reset)`
256			`l.jr r2`
257			`l.nop`
258	222	markom
259			`/*`
260	970	simons	`* Switch to a new context pointed by _task_context`
261			`*/`
262			`.global _dispatch`
263			`.align 4`
264			`_dispatch:`
265			`/* load user task GPRs and PC */`
266			`l.movhi r3,hi(_task_context)`
267			`l.addi r3,r0,lo(_task_context)`
268			`LOADREGS_N_GO`
269
270			`.section .except, "ax"`
271
272			`/*`
273	222	markom	`* Bus Error Exception handler`
274			`*/`
275			`.org 0x0200`
276			`_buserr:`
277			`l.nop`
278			`l.sw 0(r0),r3 /* Save r3 */`
279			`PRINTF(r3, _buserr_str)`
280			`_hang:`
281			`l.j _hang`
282			`l.nop`
283
284			`_buserr_str:`
285			`.ascii "Bus error exception.\n\000"`
286
287			`/*`
288			`* External Interrupt Exception handler`
289			`*/`
290			`.org 0x800`
291			`_extint:`
292			`l.nop`
293			`l.sw 0(r0),r3 /* Save r3 */`
294			`PRINTF(r3,_extint_str)`
295			`l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */`
296			`l.sw 4(r0),r3 /* and save it */`
297
298			`/* now save user task context */`
299			`l.movhi r3,hi(_task_context)`
300			`l.addi r3,r0,lo(_task_context)`
301			`SAVEREGS`
302
303			`/* set kernel context's PC to kernel's scheduler */`
304			`l.movhi r3,hi(_kernel_context)`
305			`l.addi r3,r0,lo(_kernel_context)`
306			`SET_CONTEXTPC(r3,_int_main,r4)`
307
308			`/* load kernel context */`
309			`l.movhi r3,hi(_kernel_context)`
310			`l.addi r3,r0,lo(_kernel_context)`
311			`LOADREGS`
312	511	markom
313			`l.movhi r3,hi(_int_main)`
314			`l.addi r3,r0,lo(_int_main)`
315			`l.jr r3`
316	222	markom	`l.nop`
317
318			`_extint_str:`
319			`.ascii "External interrupt exception.\n\000"`
320
321			`/*`
322			`* System Call Exception handler`
323			`*/`
324			`.org 0x0c00`
325			`_syscall:`
326			`l.nop`
327			`l.sw 0(r0),r3 /* Save r3 */`
328			`PRINTF(r3,_syscall_str)`
329			`l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */`
330			`l.addi r3,r3,4 /* increment because EPCR instruction was already executed */`
331			`l.sw 4(r0),r3 /* and save it */`
332
333			`/* now save user task context */`
334			`l.movhi r3,hi(_task_context)`
335			`l.addi r3,r0,lo(_task_context)`
336			`SAVEREGS`
337
338			`/* set kernel context's PC to kernel's syscall entry */`
339			`l.movhi r3,hi(_kernel_context)`
340			`l.addi r3,r0,lo(_kernel_context)`
341			`SET_CONTEXTPC(r3,_kernel_syscall,r4)`
342
343			`/* load kernel context */`
344			`l.movhi r3,hi(_kernel_context)`
345			`l.addi r3,r0,lo(_kernel_context)`
346			`LOADREGS_N_GO`
347
348			`_syscall_str:`
349			`.ascii "System call exception.\n\000"`
350
351