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1275 |
phoenix |
#ifndef _ASM_IA64_PAL_H
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#define _ASM_IA64_PAL_H
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#ifdef __KERNEL__
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/*
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* Processor Abstraction Layer definitions.
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*
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* This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
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* chapter 11 IA-64 Processor Abstraction Layer
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*
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* Copyright (C) 1998-2001 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Stephane Eranian <eranian@hpl.hp.com>
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* Copyright (C) 1999 VA Linux Systems
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* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
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* Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
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*
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* 99/10/01 davidm Make sure we pass zero for reserved parameters.
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* 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
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* 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
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* 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
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* 00/05/25 eranian Support for stack calls, and static physical calls
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* 00/06/18 eranian Support for stacked physical calls
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*/
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/*
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* Note that some of these calls use a static-register only calling
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* convention which has nothing to do with the regular calling
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* convention.
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*/
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#define PAL_CACHE_FLUSH 1 /* flush i/d cache */
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#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
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#define PAL_CACHE_INIT 3 /* initialize i/d cache */
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#define PAL_CACHE_SUMMARY 4 /* get summary of cache heirarchy */
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#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
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#define PAL_PTCE_INFO 6 /* purge TLB info */
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#define PAL_VM_INFO 7 /* return supported virtual memory features */
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#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
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#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
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#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
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#define PAL_DEBUG_INFO 11 /* get number of debug registers */
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#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
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#define PAL_FREQ_BASE 13 /* base frequency of the platform */
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#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
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#define PAL_PERF_MON_INFO 15 /* return performance monitor info */
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#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
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#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
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#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
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#define PAL_RSE_INFO 19 /* return rse information */
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#define PAL_VERSION 20 /* return version of PAL code */
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#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
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#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
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#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
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#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
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#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
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#define PAL_MC_RESUME 26 /* Return to interrupted process */
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#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
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#define PAL_HALT 28 /* enter the low power HALT state */
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#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
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#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
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#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
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#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
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#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
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#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
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#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
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#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
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#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
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#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
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#define PAL_PREFETCH_VISIBILITY 41
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#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
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#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
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#define PAL_TEST_PROC 258 /* perform late processor self-test */
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#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
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#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
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#define PAL_VM_TR_READ 261 /* read contents of translation register */
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/fpu.h>
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/*
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* Data types needed to pass information into PAL procedures and
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* interpret information returned by them.
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*/
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/* Return status from the PAL procedure */
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typedef s64 pal_status_t;
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#define PAL_STATUS_SUCCESS 0 /* No error */
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#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
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#define PAL_STATUS_EINVAL (-2) /* Invalid argument */
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#define PAL_STATUS_ERROR (-3) /* Error */
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#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
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* specified level and type of
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* cache without sideeffects
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* and "restrict" was 1
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*/
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/* Processor cache level in the heirarchy */
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typedef u64 pal_cache_level_t;
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#define PAL_CACHE_LEVEL_L0 0 /* L0 */
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#define PAL_CACHE_LEVEL_L1 1 /* L1 */
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#define PAL_CACHE_LEVEL_L2 2 /* L2 */
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/* Processor cache type at a particular level in the heirarchy */
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typedef u64 pal_cache_type_t;
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#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
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#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
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#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
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#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
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#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
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/* Processor cache line size in bytes */
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typedef int pal_cache_line_size_t;
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/* Processor cache line state */
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typedef u64 pal_cache_line_state_t;
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#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
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#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
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#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
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#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
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typedef struct pal_freq_ratio {
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u64 den : 32, num : 32; /* numerator & denominator */
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} itc_ratio, proc_ratio;
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typedef union pal_cache_config_info_1_s {
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struct {
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u64 u : 1, /* 0 Unified cache ? */
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at : 2, /* 2-1 Cache mem attr*/
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reserved : 5, /* 7-3 Reserved */
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associativity : 8, /* 16-8 Associativity*/
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line_size : 8, /* 23-17 Line size */
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stride : 8, /* 31-24 Stride */
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store_latency : 8, /*39-32 Store latency*/
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load_latency : 8, /* 47-40 Load latency*/
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store_hints : 8, /* 55-48 Store hints*/
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load_hints : 8; /* 63-56 Load hints */
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} pcci1_bits;
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u64 pcci1_data;
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} pal_cache_config_info_1_t;
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typedef union pal_cache_config_info_2_s {
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struct {
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u64 cache_size : 32, /*cache size in bytes*/
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alias_boundary : 8, /* 39-32 aliased addr
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* separation for max
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* performance.
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*/
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tag_ls_bit : 8, /* 47-40 LSb of addr*/
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tag_ms_bit : 8, /* 55-48 MSb of addr*/
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reserved : 8; /* 63-56 Reserved */
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} pcci2_bits;
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u64 pcci2_data;
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} pal_cache_config_info_2_t;
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typedef struct pal_cache_config_info_s {
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pal_status_t pcci_status;
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pal_cache_config_info_1_t pcci_info_1;
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pal_cache_config_info_2_t pcci_info_2;
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u64 pcci_reserved;
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} pal_cache_config_info_t;
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#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
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#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
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#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
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#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
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#define pcci_stride pcci_info_1.pcci1_bits.stride
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#define pcci_line_size pcci_info_1.pcci1_bits.line_size
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#define pcci_assoc pcci_info_1.pcci1_bits.associativity
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#define pcci_cache_attr pcci_info_1.pcci1_bits.at
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#define pcci_unified pcci_info_1.pcci1_bits.u
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#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
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#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
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#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
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#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
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/* Possible values for cache attributes */
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#define PAL_CACHE_ATTR_WT 0 /* Write through cache */
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#define PAL_CACHE_ATTR_WB 1 /* Write back cache */
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#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
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* back depending on TLB
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* memory attributes
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*/
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/* Possible values for cache hints */
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#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
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#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
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#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
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/* Processor cache protection information */
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typedef union pal_cache_protection_element_u {
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u32 pcpi_data;
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struct {
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u32 data_bits : 8, /* # data bits covered by
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* each unit of protection
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*/
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tagprot_lsb : 6, /* Least -do- */
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tagprot_msb : 6, /* Most Sig. tag address
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* bit that this
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* protection covers.
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*/
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prot_bits : 6, /* # of protection bits */
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method : 4, /* Protection method */
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t_d : 2; /* Indicates which part
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* of the cache this
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* protection encoding
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* applies.
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*/
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} pcp_info;
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} pal_cache_protection_element_t;
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#define pcpi_cache_prot_part pcp_info.t_d
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#define pcpi_prot_method pcp_info.method
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#define pcpi_prot_bits pcp_info.prot_bits
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#define pcpi_tagprot_msb pcp_info.tagprot_msb
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#define pcpi_tagprot_lsb pcp_info.tagprot_lsb
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#define pcpi_data_bits pcp_info.data_bits
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/* Processor cache part encodings */
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#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
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#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
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#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
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* more significant )
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*/
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#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
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* more significant )
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*/
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#define PAL_CACHE_PROT_PART_MAX 6
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typedef struct pal_cache_protection_info_s {
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pal_status_t pcpi_status;
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pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
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} pal_cache_protection_info_t;
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| 254 |
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| 255 |
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/* Processor cache protection method encodings */
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#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
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#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
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#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
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#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
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| 262 |
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/* Processor cache line identification in the heirarchy */
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typedef union pal_cache_line_id_u {
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u64 pclid_data;
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struct {
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u64 cache_type : 8, /* 7-0 cache type */
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level : 8, /* 15-8 level of the
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* cache in the
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* heirarchy.
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*/
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way : 8, /* 23-16 way in the set
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*/
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part : 8, /* 31-24 part of the
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* cache
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*/
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reserved : 32; /* 63-32 is reserved*/
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} pclid_info_read;
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struct {
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u64 cache_type : 8, /* 7-0 cache type */
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level : 8, /* 15-8 level of the
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* cache in the
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* heirarchy.
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*/
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way : 8, /* 23-16 way in the set
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*/
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part : 8, /* 31-24 part of the
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* cache
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*/
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mesi : 8, /* 39-32 cache line
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* state
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*/
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start : 8, /* 47-40 lsb of data to
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* invert
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*/
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length : 8, /* 55-48 #bits to
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* invert
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*/
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trigger : 8; /* 63-56 Trigger error
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* by doing a load
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* after the write
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*/
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} pclid_info_write;
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} pal_cache_line_id_u_t;
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#define pclid_read_part pclid_info_read.part
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#define pclid_read_way pclid_info_read.way
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#define pclid_read_level pclid_info_read.level
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#define pclid_read_cache_type pclid_info_read.cache_type
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|
|
#define pclid_write_trigger pclid_info_write.trigger
|
| 312 |
|
|
#define pclid_write_length pclid_info_write.length
|
| 313 |
|
|
#define pclid_write_start pclid_info_write.start
|
| 314 |
|
|
#define pclid_write_mesi pclid_info_write.mesi
|
| 315 |
|
|
#define pclid_write_part pclid_info_write.part
|
| 316 |
|
|
#define pclid_write_way pclid_info_write.way
|
| 317 |
|
|
#define pclid_write_level pclid_info_write.level
|
| 318 |
|
|
#define pclid_write_cache_type pclid_info_write.cache_type
|
| 319 |
|
|
|
| 320 |
|
|
/* Processor cache line part encodings */
|
| 321 |
|
|
#define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
|
| 322 |
|
|
#define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
|
| 323 |
|
|
#define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
|
| 324 |
|
|
#define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
|
| 325 |
|
|
#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
|
| 326 |
|
|
* protection
|
| 327 |
|
|
*/
|
| 328 |
|
|
typedef struct pal_cache_line_info_s {
|
| 329 |
|
|
pal_status_t pcli_status; /* Return status of the read cache line
|
| 330 |
|
|
* info call.
|
| 331 |
|
|
*/
|
| 332 |
|
|
u64 pcli_data; /* 64-bit data, tag, protection bits .. */
|
| 333 |
|
|
u64 pcli_data_len; /* data length in bits */
|
| 334 |
|
|
pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
|
| 335 |
|
|
|
| 336 |
|
|
} pal_cache_line_info_t;
|
| 337 |
|
|
|
| 338 |
|
|
|
| 339 |
|
|
/* Machine Check related crap */
|
| 340 |
|
|
|
| 341 |
|
|
/* Pending event status bits */
|
| 342 |
|
|
typedef u64 pal_mc_pending_events_t;
|
| 343 |
|
|
|
| 344 |
|
|
#define PAL_MC_PENDING_MCA (1 << 0)
|
| 345 |
|
|
#define PAL_MC_PENDING_INIT (1 << 1)
|
| 346 |
|
|
|
| 347 |
|
|
/* Error information type */
|
| 348 |
|
|
typedef u64 pal_mc_info_index_t;
|
| 349 |
|
|
|
| 350 |
|
|
#define PAL_MC_INFO_PROCESSOR 0 /* Processor */
|
| 351 |
|
|
#define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
|
| 352 |
|
|
#define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
|
| 353 |
|
|
#define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
|
| 354 |
|
|
#define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
|
| 355 |
|
|
#define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
|
| 356 |
|
|
#define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
|
| 357 |
|
|
#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
|
| 358 |
|
|
* dependent
|
| 359 |
|
|
*/
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
typedef struct pal_process_state_info_s {
|
| 363 |
|
|
u64 reserved1 : 2,
|
| 364 |
|
|
rz : 1, /* PAL_CHECK processor
|
| 365 |
|
|
* rendezvous
|
| 366 |
|
|
* successful.
|
| 367 |
|
|
*/
|
| 368 |
|
|
|
| 369 |
|
|
ra : 1, /* PAL_CHECK attempted
|
| 370 |
|
|
* a rendezvous.
|
| 371 |
|
|
*/
|
| 372 |
|
|
me : 1, /* Distinct multiple
|
| 373 |
|
|
* errors occurred
|
| 374 |
|
|
*/
|
| 375 |
|
|
|
| 376 |
|
|
mn : 1, /* Min. state save
|
| 377 |
|
|
* area has been
|
| 378 |
|
|
* registered with PAL
|
| 379 |
|
|
*/
|
| 380 |
|
|
|
| 381 |
|
|
sy : 1, /* Storage integrity
|
| 382 |
|
|
* synched
|
| 383 |
|
|
*/
|
| 384 |
|
|
|
| 385 |
|
|
|
| 386 |
|
|
co : 1, /* Continuable */
|
| 387 |
|
|
ci : 1, /* MC isolated */
|
| 388 |
|
|
us : 1, /* Uncontained storage
|
| 389 |
|
|
* damage.
|
| 390 |
|
|
*/
|
| 391 |
|
|
|
| 392 |
|
|
|
| 393 |
|
|
hd : 1, /* Non-essential hw
|
| 394 |
|
|
* lost (no loss of
|
| 395 |
|
|
* functionality)
|
| 396 |
|
|
* causing the
|
| 397 |
|
|
* processor to run in
|
| 398 |
|
|
* degraded mode.
|
| 399 |
|
|
*/
|
| 400 |
|
|
|
| 401 |
|
|
tl : 1, /* 1 => MC occurred
|
| 402 |
|
|
* after an instr was
|
| 403 |
|
|
* executed but before
|
| 404 |
|
|
* the trap that
|
| 405 |
|
|
* resulted from instr
|
| 406 |
|
|
* execution was
|
| 407 |
|
|
* generated.
|
| 408 |
|
|
* (Trap Lost )
|
| 409 |
|
|
*/
|
| 410 |
|
|
mi : 1, /* More information available
|
| 411 |
|
|
* call PAL_MC_ERROR_INFO
|
| 412 |
|
|
*/
|
| 413 |
|
|
pi : 1, /* Precise instruction pointer */
|
| 414 |
|
|
pm : 1, /* Precise min-state save area */
|
| 415 |
|
|
|
| 416 |
|
|
dy : 1, /* Processor dynamic
|
| 417 |
|
|
* state valid
|
| 418 |
|
|
*/
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
in : 1, /* 0 = MC, 1 = INIT */
|
| 422 |
|
|
rs : 1, /* RSE valid */
|
| 423 |
|
|
cm : 1, /* MC corrected */
|
| 424 |
|
|
ex : 1, /* MC is expected */
|
| 425 |
|
|
cr : 1, /* Control regs valid*/
|
| 426 |
|
|
pc : 1, /* Perf cntrs valid */
|
| 427 |
|
|
dr : 1, /* Debug regs valid */
|
| 428 |
|
|
tr : 1, /* Translation regs
|
| 429 |
|
|
* valid
|
| 430 |
|
|
*/
|
| 431 |
|
|
rr : 1, /* Region regs valid */
|
| 432 |
|
|
ar : 1, /* App regs valid */
|
| 433 |
|
|
br : 1, /* Branch regs valid */
|
| 434 |
|
|
pr : 1, /* Predicate registers
|
| 435 |
|
|
* valid
|
| 436 |
|
|
*/
|
| 437 |
|
|
|
| 438 |
|
|
fp : 1, /* fp registers valid*/
|
| 439 |
|
|
b1 : 1, /* Preserved bank one
|
| 440 |
|
|
* general registers
|
| 441 |
|
|
* are valid
|
| 442 |
|
|
*/
|
| 443 |
|
|
b0 : 1, /* Preserved bank zero
|
| 444 |
|
|
* general registers
|
| 445 |
|
|
* are valid
|
| 446 |
|
|
*/
|
| 447 |
|
|
gr : 1, /* General registers
|
| 448 |
|
|
* are valid
|
| 449 |
|
|
* (excl. banked regs)
|
| 450 |
|
|
*/
|
| 451 |
|
|
dsize : 16, /* size of dynamic
|
| 452 |
|
|
* state returned
|
| 453 |
|
|
* by the processor
|
| 454 |
|
|
*/
|
| 455 |
|
|
|
| 456 |
|
|
reserved2 : 11,
|
| 457 |
|
|
cc : 1, /* Cache check */
|
| 458 |
|
|
tc : 1, /* TLB check */
|
| 459 |
|
|
bc : 1, /* Bus check */
|
| 460 |
|
|
rc : 1, /* Register file check */
|
| 461 |
|
|
uc : 1; /* Uarch check */
|
| 462 |
|
|
|
| 463 |
|
|
} pal_processor_state_info_t;
|
| 464 |
|
|
|
| 465 |
|
|
typedef struct pal_cache_check_info_s {
|
| 466 |
|
|
u64 op : 4, /* Type of cache
|
| 467 |
|
|
* operation that
|
| 468 |
|
|
* caused the machine
|
| 469 |
|
|
* check.
|
| 470 |
|
|
*/
|
| 471 |
|
|
level : 2, /* Cache level */
|
| 472 |
|
|
reserved1 : 2,
|
| 473 |
|
|
dl : 1, /* Failure in data part
|
| 474 |
|
|
* of cache line
|
| 475 |
|
|
*/
|
| 476 |
|
|
tl : 1, /* Failure in tag part
|
| 477 |
|
|
* of cache line
|
| 478 |
|
|
*/
|
| 479 |
|
|
dc : 1, /* Failure in dcache */
|
| 480 |
|
|
ic : 1, /* Failure in icache */
|
| 481 |
|
|
mesi : 3, /* Cache line state */
|
| 482 |
|
|
mv : 1, /* mesi valid */
|
| 483 |
|
|
way : 5, /* Way in which the
|
| 484 |
|
|
* error occurred
|
| 485 |
|
|
*/
|
| 486 |
|
|
wiv : 1, /* Way field valid */
|
| 487 |
|
|
reserved2 : 10,
|
| 488 |
|
|
|
| 489 |
|
|
index : 20, /* Cache line index */
|
| 490 |
|
|
reserved3 : 2,
|
| 491 |
|
|
|
| 492 |
|
|
is : 1, /* instruction set (1 == ia32) */
|
| 493 |
|
|
iv : 1, /* instruction set field valid */
|
| 494 |
|
|
pl : 2, /* privilege level */
|
| 495 |
|
|
pv : 1, /* privilege level field valid */
|
| 496 |
|
|
mcc : 1, /* Machine check corrected */
|
| 497 |
|
|
tv : 1, /* Target address
|
| 498 |
|
|
* structure is valid
|
| 499 |
|
|
*/
|
| 500 |
|
|
rq : 1, /* Requester identifier
|
| 501 |
|
|
* structure is valid
|
| 502 |
|
|
*/
|
| 503 |
|
|
rp : 1, /* Responder identifier
|
| 504 |
|
|
* structure is valid
|
| 505 |
|
|
*/
|
| 506 |
|
|
pi : 1; /* Precise instruction pointer
|
| 507 |
|
|
* structure is valid
|
| 508 |
|
|
*/
|
| 509 |
|
|
} pal_cache_check_info_t;
|
| 510 |
|
|
|
| 511 |
|
|
typedef struct pal_tlb_check_info_s {
|
| 512 |
|
|
|
| 513 |
|
|
u64 tr_slot : 8, /* Slot# of TR where
|
| 514 |
|
|
* error occurred
|
| 515 |
|
|
*/
|
| 516 |
|
|
trv : 1, /* tr_slot field is valid */
|
| 517 |
|
|
reserved1 : 1,
|
| 518 |
|
|
level : 2, /* TLB level where failure occurred */
|
| 519 |
|
|
reserved2 : 4,
|
| 520 |
|
|
dtr : 1, /* Fail in data TR */
|
| 521 |
|
|
itr : 1, /* Fail in inst TR */
|
| 522 |
|
|
dtc : 1, /* Fail in data TC */
|
| 523 |
|
|
itc : 1, /* Fail in inst. TC */
|
| 524 |
|
|
op : 4, /* Cache operation */
|
| 525 |
|
|
reserved3 : 30,
|
| 526 |
|
|
|
| 527 |
|
|
is : 1, /* instruction set (1 == ia32) */
|
| 528 |
|
|
iv : 1, /* instruction set field valid */
|
| 529 |
|
|
pl : 2, /* privilege level */
|
| 530 |
|
|
pv : 1, /* privilege level field valid */
|
| 531 |
|
|
mcc : 1, /* Machine check corrected */
|
| 532 |
|
|
tv : 1, /* Target address
|
| 533 |
|
|
* structure is valid
|
| 534 |
|
|
*/
|
| 535 |
|
|
rq : 1, /* Requester identifier
|
| 536 |
|
|
* structure is valid
|
| 537 |
|
|
*/
|
| 538 |
|
|
rp : 1, /* Responder identifier
|
| 539 |
|
|
* structure is valid
|
| 540 |
|
|
*/
|
| 541 |
|
|
pi : 1; /* Precise instruction pointer
|
| 542 |
|
|
* structure is valid
|
| 543 |
|
|
*/
|
| 544 |
|
|
} pal_tlb_check_info_t;
|
| 545 |
|
|
|
| 546 |
|
|
typedef struct pal_bus_check_info_s {
|
| 547 |
|
|
u64 size : 5, /* Xaction size */
|
| 548 |
|
|
ib : 1, /* Internal bus error */
|
| 549 |
|
|
eb : 1, /* External bus error */
|
| 550 |
|
|
cc : 1, /* Error occurred
|
| 551 |
|
|
* during cache-cache
|
| 552 |
|
|
* transfer.
|
| 553 |
|
|
*/
|
| 554 |
|
|
type : 8, /* Bus xaction type*/
|
| 555 |
|
|
sev : 5, /* Bus error severity*/
|
| 556 |
|
|
hier : 2, /* Bus hierarchy level */
|
| 557 |
|
|
reserved1 : 1,
|
| 558 |
|
|
bsi : 8, /* Bus error status
|
| 559 |
|
|
* info
|
| 560 |
|
|
*/
|
| 561 |
|
|
reserved2 : 22,
|
| 562 |
|
|
|
| 563 |
|
|
is : 1, /* instruction set (1 == ia32) */
|
| 564 |
|
|
iv : 1, /* instruction set field valid */
|
| 565 |
|
|
pl : 2, /* privilege level */
|
| 566 |
|
|
pv : 1, /* privilege level field valid */
|
| 567 |
|
|
mcc : 1, /* Machine check corrected */
|
| 568 |
|
|
tv : 1, /* Target address
|
| 569 |
|
|
* structure is valid
|
| 570 |
|
|
*/
|
| 571 |
|
|
rq : 1, /* Requester identifier
|
| 572 |
|
|
* structure is valid
|
| 573 |
|
|
*/
|
| 574 |
|
|
rp : 1, /* Responder identifier
|
| 575 |
|
|
* structure is valid
|
| 576 |
|
|
*/
|
| 577 |
|
|
pi : 1; /* Precise instruction pointer
|
| 578 |
|
|
* structure is valid
|
| 579 |
|
|
*/
|
| 580 |
|
|
} pal_bus_check_info_t;
|
| 581 |
|
|
|
| 582 |
|
|
typedef struct pal_reg_file_check_info_s {
|
| 583 |
|
|
u64 id : 4, /* Register file identifier */
|
| 584 |
|
|
op : 4, /* Type of register
|
| 585 |
|
|
* operation that
|
| 586 |
|
|
* caused the machine
|
| 587 |
|
|
* check.
|
| 588 |
|
|
*/
|
| 589 |
|
|
reg_num : 7, /* Register number */
|
| 590 |
|
|
rnv : 1, /* reg_num valid */
|
| 591 |
|
|
reserved2 : 38,
|
| 592 |
|
|
|
| 593 |
|
|
is : 1, /* instruction set (1 == ia32) */
|
| 594 |
|
|
iv : 1, /* instruction set field valid */
|
| 595 |
|
|
pl : 2, /* privilege level */
|
| 596 |
|
|
pv : 1, /* privilege level field valid */
|
| 597 |
|
|
mcc : 1, /* Machine check corrected */
|
| 598 |
|
|
reserved3 : 3,
|
| 599 |
|
|
pi : 1; /* Precise instruction pointer
|
| 600 |
|
|
* structure is valid
|
| 601 |
|
|
*/
|
| 602 |
|
|
} pal_reg_file_check_info_t;
|
| 603 |
|
|
|
| 604 |
|
|
typedef struct pal_uarch_check_info_s {
|
| 605 |
|
|
u64 sid : 5, /* Structure identification */
|
| 606 |
|
|
level : 3, /* Level of failure */
|
| 607 |
|
|
array_id : 4, /* Array identification */
|
| 608 |
|
|
op : 4, /* Type of
|
| 609 |
|
|
* operation that
|
| 610 |
|
|
* caused the machine
|
| 611 |
|
|
* check.
|
| 612 |
|
|
*/
|
| 613 |
|
|
way : 6, /* Way of structure */
|
| 614 |
|
|
wv : 1, /* way valid */
|
| 615 |
|
|
xv : 1, /* index valid */
|
| 616 |
|
|
reserved1 : 8,
|
| 617 |
|
|
index : 8, /* Index or set of the uarch
|
| 618 |
|
|
* structure that failed.
|
| 619 |
|
|
*/
|
| 620 |
|
|
reserved2 : 24,
|
| 621 |
|
|
|
| 622 |
|
|
is : 1, /* instruction set (1 == ia32) */
|
| 623 |
|
|
iv : 1, /* instruction set field valid */
|
| 624 |
|
|
pl : 2, /* privilege level */
|
| 625 |
|
|
pv : 1, /* privilege level field valid */
|
| 626 |
|
|
mcc : 1, /* Machine check corrected */
|
| 627 |
|
|
tv : 1, /* Target address
|
| 628 |
|
|
* structure is valid
|
| 629 |
|
|
*/
|
| 630 |
|
|
rq : 1, /* Requester identifier
|
| 631 |
|
|
* structure is valid
|
| 632 |
|
|
*/
|
| 633 |
|
|
rp : 1, /* Responder identifier
|
| 634 |
|
|
* structure is valid
|
| 635 |
|
|
*/
|
| 636 |
|
|
pi : 1; /* Precise instruction pointer
|
| 637 |
|
|
* structure is valid
|
| 638 |
|
|
*/
|
| 639 |
|
|
} pal_uarch_check_info_t;
|
| 640 |
|
|
|
| 641 |
|
|
typedef union pal_mc_error_info_u {
|
| 642 |
|
|
u64 pmei_data;
|
| 643 |
|
|
pal_processor_state_info_t pme_processor;
|
| 644 |
|
|
pal_cache_check_info_t pme_cache;
|
| 645 |
|
|
pal_tlb_check_info_t pme_tlb;
|
| 646 |
|
|
pal_bus_check_info_t pme_bus;
|
| 647 |
|
|
pal_reg_file_check_info_t pme_reg_file;
|
| 648 |
|
|
pal_uarch_check_info_t pme_uarch;
|
| 649 |
|
|
} pal_mc_error_info_t;
|
| 650 |
|
|
|
| 651 |
|
|
#define pmci_proc_unknown_check pme_processor.uc
|
| 652 |
|
|
#define pmci_proc_bus_check pme_processor.bc
|
| 653 |
|
|
#define pmci_proc_tlb_check pme_processor.tc
|
| 654 |
|
|
#define pmci_proc_cache_check pme_processor.cc
|
| 655 |
|
|
#define pmci_proc_dynamic_state_size pme_processor.dsize
|
| 656 |
|
|
#define pmci_proc_gpr_valid pme_processor.gr
|
| 657 |
|
|
#define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
|
| 658 |
|
|
#define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
|
| 659 |
|
|
#define pmci_proc_fp_valid pme_processor.fp
|
| 660 |
|
|
#define pmci_proc_predicate_regs_valid pme_processor.pr
|
| 661 |
|
|
#define pmci_proc_branch_regs_valid pme_processor.br
|
| 662 |
|
|
#define pmci_proc_app_regs_valid pme_processor.ar
|
| 663 |
|
|
#define pmci_proc_region_regs_valid pme_processor.rr
|
| 664 |
|
|
#define pmci_proc_translation_regs_valid pme_processor.tr
|
| 665 |
|
|
#define pmci_proc_debug_regs_valid pme_processor.dr
|
| 666 |
|
|
#define pmci_proc_perf_counters_valid pme_processor.pc
|
| 667 |
|
|
#define pmci_proc_control_regs_valid pme_processor.cr
|
| 668 |
|
|
#define pmci_proc_machine_check_expected pme_processor.ex
|
| 669 |
|
|
#define pmci_proc_machine_check_corrected pme_processor.cm
|
| 670 |
|
|
#define pmci_proc_rse_valid pme_processor.rs
|
| 671 |
|
|
#define pmci_proc_machine_check_or_init pme_processor.in
|
| 672 |
|
|
#define pmci_proc_dynamic_state_valid pme_processor.dy
|
| 673 |
|
|
#define pmci_proc_operation pme_processor.op
|
| 674 |
|
|
#define pmci_proc_trap_lost pme_processor.tl
|
| 675 |
|
|
#define pmci_proc_hardware_damage pme_processor.hd
|
| 676 |
|
|
#define pmci_proc_uncontained_storage_damage pme_processor.us
|
| 677 |
|
|
#define pmci_proc_machine_check_isolated pme_processor.ci
|
| 678 |
|
|
#define pmci_proc_continuable pme_processor.co
|
| 679 |
|
|
#define pmci_proc_storage_intergrity_synced pme_processor.sy
|
| 680 |
|
|
#define pmci_proc_min_state_save_area_regd pme_processor.mn
|
| 681 |
|
|
#define pmci_proc_distinct_multiple_errors pme_processor.me
|
| 682 |
|
|
#define pmci_proc_pal_attempted_rendezvous pme_processor.ra
|
| 683 |
|
|
#define pmci_proc_pal_rendezvous_complete pme_processor.rz
|
| 684 |
|
|
|
| 685 |
|
|
|
| 686 |
|
|
#define pmci_cache_level pme_cache.level
|
| 687 |
|
|
#define pmci_cache_line_state pme_cache.mesi
|
| 688 |
|
|
#define pmci_cache_line_state_valid pme_cache.mv
|
| 689 |
|
|
#define pmci_cache_line_index pme_cache.index
|
| 690 |
|
|
#define pmci_cache_instr_cache_fail pme_cache.ic
|
| 691 |
|
|
#define pmci_cache_data_cache_fail pme_cache.dc
|
| 692 |
|
|
#define pmci_cache_line_tag_fail pme_cache.tl
|
| 693 |
|
|
#define pmci_cache_line_data_fail pme_cache.dl
|
| 694 |
|
|
#define pmci_cache_operation pme_cache.op
|
| 695 |
|
|
#define pmci_cache_way_valid pme_cache.wv
|
| 696 |
|
|
#define pmci_cache_target_address_valid pme_cache.tv
|
| 697 |
|
|
#define pmci_cache_way pme_cache.way
|
| 698 |
|
|
#define pmci_cache_mc pme_cache.mc
|
| 699 |
|
|
|
| 700 |
|
|
#define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
|
| 701 |
|
|
#define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
|
| 702 |
|
|
#define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
|
| 703 |
|
|
#define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
|
| 704 |
|
|
#define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
|
| 705 |
|
|
#define pmci_tlb_mc pme_tlb.mc
|
| 706 |
|
|
|
| 707 |
|
|
#define pmci_bus_status_info pme_bus.bsi
|
| 708 |
|
|
#define pmci_bus_req_address_valid pme_bus.rq
|
| 709 |
|
|
#define pmci_bus_resp_address_valid pme_bus.rp
|
| 710 |
|
|
#define pmci_bus_target_address_valid pme_bus.tv
|
| 711 |
|
|
#define pmci_bus_error_severity pme_bus.sev
|
| 712 |
|
|
#define pmci_bus_transaction_type pme_bus.type
|
| 713 |
|
|
#define pmci_bus_cache_cache_transfer pme_bus.cc
|
| 714 |
|
|
#define pmci_bus_transaction_size pme_bus.size
|
| 715 |
|
|
#define pmci_bus_internal_error pme_bus.ib
|
| 716 |
|
|
#define pmci_bus_external_error pme_bus.eb
|
| 717 |
|
|
#define pmci_bus_mc pme_bus.mc
|
| 718 |
|
|
|
| 719 |
|
|
/*
|
| 720 |
|
|
* NOTE: this min_state_save area struct only includes the 1KB
|
| 721 |
|
|
* architectural state save area. The other 3 KB is scratch space
|
| 722 |
|
|
* for PAL.
|
| 723 |
|
|
*/
|
| 724 |
|
|
|
| 725 |
|
|
typedef struct pal_min_state_area_s {
|
| 726 |
|
|
u64 pmsa_nat_bits; /* nat bits for saved GRs */
|
| 727 |
|
|
u64 pmsa_gr[15]; /* GR1 - GR15 */
|
| 728 |
|
|
u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
|
| 729 |
|
|
u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
|
| 730 |
|
|
u64 pmsa_pr; /* predicate registers */
|
| 731 |
|
|
u64 pmsa_br0; /* branch register 0 */
|
| 732 |
|
|
u64 pmsa_rsc; /* ar.rsc */
|
| 733 |
|
|
u64 pmsa_iip; /* cr.iip */
|
| 734 |
|
|
u64 pmsa_ipsr; /* cr.ipsr */
|
| 735 |
|
|
u64 pmsa_ifs; /* cr.ifs */
|
| 736 |
|
|
u64 pmsa_xip; /* previous iip */
|
| 737 |
|
|
u64 pmsa_xpsr; /* previous psr */
|
| 738 |
|
|
u64 pmsa_xfs; /* previous ifs */
|
| 739 |
|
|
u64 pmsa_br1; /* branch register 1 */
|
| 740 |
|
|
u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
|
| 741 |
|
|
} pal_min_state_area_t;
|
| 742 |
|
|
|
| 743 |
|
|
|
| 744 |
|
|
struct ia64_pal_retval {
|
| 745 |
|
|
/*
|
| 746 |
|
|
* A zero status value indicates call completed without error.
|
| 747 |
|
|
* A negative status value indicates reason of call failure.
|
| 748 |
|
|
* A positive status value indicates success but an
|
| 749 |
|
|
* informational value should be printed (e.g., "reboot for
|
| 750 |
|
|
* change to take effect").
|
| 751 |
|
|
*/
|
| 752 |
|
|
s64 status;
|
| 753 |
|
|
u64 v0;
|
| 754 |
|
|
u64 v1;
|
| 755 |
|
|
u64 v2;
|
| 756 |
|
|
};
|
| 757 |
|
|
|
| 758 |
|
|
/*
|
| 759 |
|
|
* Note: Currently unused PAL arguments are generally labeled
|
| 760 |
|
|
* "reserved" so the value specified in the PAL documentation
|
| 761 |
|
|
* (generally 0) MUST be passed. Reserved parameters are not optional
|
| 762 |
|
|
* parameters.
|
| 763 |
|
|
*/
|
| 764 |
|
|
extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
|
| 765 |
|
|
extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
|
| 766 |
|
|
extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
|
| 767 |
|
|
extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
|
| 768 |
|
|
|
| 769 |
|
|
extern void ia64_save_scratch_fpregs(struct ia64_fpreg *);
|
| 770 |
|
|
extern void ia64_load_scratch_fpregs(struct ia64_fpreg *);
|
| 771 |
|
|
|
| 772 |
|
|
#define PAL_CALL(iprv,a0,a1,a2,a3) do { \
|
| 773 |
|
|
struct ia64_fpreg fr[6]; \
|
| 774 |
|
|
ia64_save_scratch_fpregs(fr); \
|
| 775 |
|
|
iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
|
| 776 |
|
|
ia64_load_scratch_fpregs(fr); \
|
| 777 |
|
|
} while (0)
|
| 778 |
|
|
|
| 779 |
|
|
#define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do { \
|
| 780 |
|
|
struct ia64_fpreg fr[6]; \
|
| 781 |
|
|
ia64_save_scratch_fpregs(fr); \
|
| 782 |
|
|
iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
|
| 783 |
|
|
ia64_load_scratch_fpregs(fr); \
|
| 784 |
|
|
} while (0)
|
| 785 |
|
|
|
| 786 |
|
|
#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
|
| 787 |
|
|
struct ia64_fpreg fr[6]; \
|
| 788 |
|
|
ia64_save_scratch_fpregs(fr); \
|
| 789 |
|
|
iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
|
| 790 |
|
|
ia64_load_scratch_fpregs(fr); \
|
| 791 |
|
|
} while (0)
|
| 792 |
|
|
|
| 793 |
|
|
#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
|
| 794 |
|
|
struct ia64_fpreg fr[6]; \
|
| 795 |
|
|
ia64_save_scratch_fpregs(fr); \
|
| 796 |
|
|
iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);\
|
| 797 |
|
|
ia64_load_scratch_fpregs(fr); \
|
| 798 |
|
|
} while (0)
|
| 799 |
|
|
|
| 800 |
|
|
#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
|
| 801 |
|
|
struct ia64_fpreg fr[6]; \
|
| 802 |
|
|
ia64_save_scratch_fpregs(fr); \
|
| 803 |
|
|
iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
|
| 804 |
|
|
ia64_load_scratch_fpregs(fr); \
|
| 805 |
|
|
} while (0)
|
| 806 |
|
|
|
| 807 |
|
|
typedef int (*ia64_pal_handler) (u64, ...);
|
| 808 |
|
|
extern ia64_pal_handler ia64_pal;
|
| 809 |
|
|
extern void ia64_pal_handler_init (void *);
|
| 810 |
|
|
|
| 811 |
|
|
extern ia64_pal_handler ia64_pal;
|
| 812 |
|
|
|
| 813 |
|
|
extern pal_cache_config_info_t l0d_cache_config_info;
|
| 814 |
|
|
extern pal_cache_config_info_t l0i_cache_config_info;
|
| 815 |
|
|
extern pal_cache_config_info_t l1_cache_config_info;
|
| 816 |
|
|
extern pal_cache_config_info_t l2_cache_config_info;
|
| 817 |
|
|
|
| 818 |
|
|
extern pal_cache_protection_info_t l0d_cache_protection_info;
|
| 819 |
|
|
extern pal_cache_protection_info_t l0i_cache_protection_info;
|
| 820 |
|
|
extern pal_cache_protection_info_t l1_cache_protection_info;
|
| 821 |
|
|
extern pal_cache_protection_info_t l2_cache_protection_info;
|
| 822 |
|
|
|
| 823 |
|
|
extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
|
| 824 |
|
|
pal_cache_type_t);
|
| 825 |
|
|
|
| 826 |
|
|
extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
|
| 827 |
|
|
pal_cache_type_t);
|
| 828 |
|
|
|
| 829 |
|
|
|
| 830 |
|
|
extern void pal_error(int);
|
| 831 |
|
|
|
| 832 |
|
|
|
| 833 |
|
|
/* Useful wrappers for the current list of pal procedures */
|
| 834 |
|
|
|
| 835 |
|
|
typedef union pal_bus_features_u {
|
| 836 |
|
|
u64 pal_bus_features_val;
|
| 837 |
|
|
struct {
|
| 838 |
|
|
u64 pbf_reserved1 : 29;
|
| 839 |
|
|
u64 pbf_req_bus_parking : 1;
|
| 840 |
|
|
u64 pbf_bus_lock_mask : 1;
|
| 841 |
|
|
u64 pbf_enable_half_xfer_rate : 1;
|
| 842 |
|
|
u64 pbf_reserved2 : 22;
|
| 843 |
|
|
u64 pbf_disable_xaction_queueing : 1;
|
| 844 |
|
|
u64 pbf_disable_resp_err_check : 1;
|
| 845 |
|
|
u64 pbf_disable_berr_check : 1;
|
| 846 |
|
|
u64 pbf_disable_bus_req_internal_err_signal : 1;
|
| 847 |
|
|
u64 pbf_disable_bus_req_berr_signal : 1;
|
| 848 |
|
|
u64 pbf_disable_bus_init_event_check : 1;
|
| 849 |
|
|
u64 pbf_disable_bus_init_event_signal : 1;
|
| 850 |
|
|
u64 pbf_disable_bus_addr_err_check : 1;
|
| 851 |
|
|
u64 pbf_disable_bus_addr_err_signal : 1;
|
| 852 |
|
|
u64 pbf_disable_bus_data_err_check : 1;
|
| 853 |
|
|
} pal_bus_features_s;
|
| 854 |
|
|
} pal_bus_features_u_t;
|
| 855 |
|
|
|
| 856 |
|
|
extern void pal_bus_features_print (u64);
|
| 857 |
|
|
|
| 858 |
|
|
/* Provide information about configurable processor bus features */
|
| 859 |
|
|
static inline s64
|
| 860 |
|
|
ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
|
| 861 |
|
|
pal_bus_features_u_t *features_status,
|
| 862 |
|
|
pal_bus_features_u_t *features_control)
|
| 863 |
|
|
{
|
| 864 |
|
|
struct ia64_pal_retval iprv;
|
| 865 |
|
|
PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
|
| 866 |
|
|
if (features_avail)
|
| 867 |
|
|
features_avail->pal_bus_features_val = iprv.v0;
|
| 868 |
|
|
if (features_status)
|
| 869 |
|
|
features_status->pal_bus_features_val = iprv.v1;
|
| 870 |
|
|
if (features_control)
|
| 871 |
|
|
features_control->pal_bus_features_val = iprv.v2;
|
| 872 |
|
|
return iprv.status;
|
| 873 |
|
|
}
|
| 874 |
|
|
|
| 875 |
|
|
/* Enables/disables specific processor bus features */
|
| 876 |
|
|
static inline s64
|
| 877 |
|
|
ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
|
| 878 |
|
|
{
|
| 879 |
|
|
struct ia64_pal_retval iprv;
|
| 880 |
|
|
PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
|
| 881 |
|
|
return iprv.status;
|
| 882 |
|
|
}
|
| 883 |
|
|
|
| 884 |
|
|
/* Get detailed cache information */
|
| 885 |
|
|
static inline s64
|
| 886 |
|
|
ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
|
| 887 |
|
|
{
|
| 888 |
|
|
struct ia64_pal_retval iprv;
|
| 889 |
|
|
|
| 890 |
|
|
PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
|
| 891 |
|
|
|
| 892 |
|
|
if (iprv.status == 0) {
|
| 893 |
|
|
conf->pcci_status = iprv.status;
|
| 894 |
|
|
conf->pcci_info_1.pcci1_data = iprv.v0;
|
| 895 |
|
|
conf->pcci_info_2.pcci2_data = iprv.v1;
|
| 896 |
|
|
conf->pcci_reserved = iprv.v2;
|
| 897 |
|
|
}
|
| 898 |
|
|
return iprv.status;
|
| 899 |
|
|
|
| 900 |
|
|
}
|
| 901 |
|
|
|
| 902 |
|
|
/* Get detailed cche protection information */
|
| 903 |
|
|
static inline s64
|
| 904 |
|
|
ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
|
| 905 |
|
|
{
|
| 906 |
|
|
struct ia64_pal_retval iprv;
|
| 907 |
|
|
|
| 908 |
|
|
PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
|
| 909 |
|
|
|
| 910 |
|
|
if (iprv.status == 0) {
|
| 911 |
|
|
prot->pcpi_status = iprv.status;
|
| 912 |
|
|
prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
|
| 913 |
|
|
prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
|
| 914 |
|
|
prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
|
| 915 |
|
|
prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
|
| 916 |
|
|
prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
|
| 917 |
|
|
prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
|
| 918 |
|
|
}
|
| 919 |
|
|
return iprv.status;
|
| 920 |
|
|
}
|
| 921 |
|
|
|
| 922 |
|
|
/*
|
| 923 |
|
|
* Flush the processor instruction or data caches. *PROGRESS must be
|
| 924 |
|
|
* initialized to zero before calling this for the first time..
|
| 925 |
|
|
*/
|
| 926 |
|
|
static inline s64
|
| 927 |
|
|
ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
|
| 928 |
|
|
{
|
| 929 |
|
|
struct ia64_pal_retval iprv;
|
| 930 |
|
|
PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
|
| 931 |
|
|
if (vector)
|
| 932 |
|
|
*vector = iprv.v0;
|
| 933 |
|
|
*progress = iprv.v1;
|
| 934 |
|
|
return iprv.status;
|
| 935 |
|
|
}
|
| 936 |
|
|
|
| 937 |
|
|
|
| 938 |
|
|
/* Initialize the processor controlled caches */
|
| 939 |
|
|
static inline s64
|
| 940 |
|
|
ia64_pal_cache_init (u64 level, u64 cache_type, u64 restrict)
|
| 941 |
|
|
{
|
| 942 |
|
|
struct ia64_pal_retval iprv;
|
| 943 |
|
|
PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, restrict);
|
| 944 |
|
|
return iprv.status;
|
| 945 |
|
|
}
|
| 946 |
|
|
|
| 947 |
|
|
/* Initialize the tags and data of a data or unified cache line of
|
| 948 |
|
|
* processor controlled cache to known values without the availability
|
| 949 |
|
|
* of backing memory.
|
| 950 |
|
|
*/
|
| 951 |
|
|
static inline s64
|
| 952 |
|
|
ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
|
| 953 |
|
|
{
|
| 954 |
|
|
struct ia64_pal_retval iprv;
|
| 955 |
|
|
PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
|
| 956 |
|
|
return iprv.status;
|
| 957 |
|
|
}
|
| 958 |
|
|
|
| 959 |
|
|
|
| 960 |
|
|
/* Read the data and tag of a processor controlled cache line for diags */
|
| 961 |
|
|
static inline s64
|
| 962 |
|
|
ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
|
| 963 |
|
|
{
|
| 964 |
|
|
struct ia64_pal_retval iprv;
|
| 965 |
|
|
PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
|
| 966 |
|
|
return iprv.status;
|
| 967 |
|
|
}
|
| 968 |
|
|
|
| 969 |
|
|
/* Return summary information about the heirarchy of caches controlled by the processor */
|
| 970 |
|
|
static inline s64
|
| 971 |
|
|
ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
|
| 972 |
|
|
{
|
| 973 |
|
|
struct ia64_pal_retval iprv;
|
| 974 |
|
|
PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
|
| 975 |
|
|
if (cache_levels)
|
| 976 |
|
|
*cache_levels = iprv.v0;
|
| 977 |
|
|
if (unique_caches)
|
| 978 |
|
|
*unique_caches = iprv.v1;
|
| 979 |
|
|
return iprv.status;
|
| 980 |
|
|
}
|
| 981 |
|
|
|
| 982 |
|
|
/* Write the data and tag of a processor-controlled cache line for diags */
|
| 983 |
|
|
static inline s64
|
| 984 |
|
|
ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
|
| 985 |
|
|
{
|
| 986 |
|
|
struct ia64_pal_retval iprv;
|
| 987 |
|
|
PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
|
| 988 |
|
|
return iprv.status;
|
| 989 |
|
|
}
|
| 990 |
|
|
|
| 991 |
|
|
|
| 992 |
|
|
/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
|
| 993 |
|
|
static inline s64
|
| 994 |
|
|
ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
|
| 995 |
|
|
u64 *buffer_size, u64 *buffer_align)
|
| 996 |
|
|
{
|
| 997 |
|
|
struct ia64_pal_retval iprv;
|
| 998 |
|
|
PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
|
| 999 |
|
|
if (buffer_size)
|
| 1000 |
|
|
*buffer_size = iprv.v0;
|
| 1001 |
|
|
if (buffer_align)
|
| 1002 |
|
|
*buffer_align = iprv.v1;
|
| 1003 |
|
|
return iprv.status;
|
| 1004 |
|
|
}
|
| 1005 |
|
|
|
| 1006 |
|
|
/* Copy relocatable PAL procedures from ROM to memory */
|
| 1007 |
|
|
static inline s64
|
| 1008 |
|
|
ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
|
| 1009 |
|
|
{
|
| 1010 |
|
|
struct ia64_pal_retval iprv;
|
| 1011 |
|
|
PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
|
| 1012 |
|
|
if (pal_proc_offset)
|
| 1013 |
|
|
*pal_proc_offset = iprv.v0;
|
| 1014 |
|
|
return iprv.status;
|
| 1015 |
|
|
}
|
| 1016 |
|
|
|
| 1017 |
|
|
/* Return the number of instruction and data debug register pairs */
|
| 1018 |
|
|
static inline s64
|
| 1019 |
|
|
ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
|
| 1020 |
|
|
{
|
| 1021 |
|
|
struct ia64_pal_retval iprv;
|
| 1022 |
|
|
PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
|
| 1023 |
|
|
if (inst_regs)
|
| 1024 |
|
|
*inst_regs = iprv.v0;
|
| 1025 |
|
|
if (data_regs)
|
| 1026 |
|
|
*data_regs = iprv.v1;
|
| 1027 |
|
|
|
| 1028 |
|
|
return iprv.status;
|
| 1029 |
|
|
}
|
| 1030 |
|
|
|
| 1031 |
|
|
#ifdef TBD
|
| 1032 |
|
|
/* Switch from IA64-system environment to IA-32 system environment */
|
| 1033 |
|
|
static inline s64
|
| 1034 |
|
|
ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
|
| 1035 |
|
|
{
|
| 1036 |
|
|
struct ia64_pal_retval iprv;
|
| 1037 |
|
|
PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
|
| 1038 |
|
|
return iprv.status;
|
| 1039 |
|
|
}
|
| 1040 |
|
|
#endif
|
| 1041 |
|
|
|
| 1042 |
|
|
/* Get unique geographical address of this processor on its bus */
|
| 1043 |
|
|
static inline s64
|
| 1044 |
|
|
ia64_pal_fixed_addr (u64 *global_unique_addr)
|
| 1045 |
|
|
{
|
| 1046 |
|
|
struct ia64_pal_retval iprv;
|
| 1047 |
|
|
PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
|
| 1048 |
|
|
if (global_unique_addr)
|
| 1049 |
|
|
*global_unique_addr = iprv.v0;
|
| 1050 |
|
|
return iprv.status;
|
| 1051 |
|
|
}
|
| 1052 |
|
|
|
| 1053 |
|
|
/* Get base frequency of the platform if generated by the processor */
|
| 1054 |
|
|
static inline s64
|
| 1055 |
|
|
ia64_pal_freq_base (u64 *platform_base_freq)
|
| 1056 |
|
|
{
|
| 1057 |
|
|
struct ia64_pal_retval iprv;
|
| 1058 |
|
|
PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
|
| 1059 |
|
|
if (platform_base_freq)
|
| 1060 |
|
|
*platform_base_freq = iprv.v0;
|
| 1061 |
|
|
return iprv.status;
|
| 1062 |
|
|
}
|
| 1063 |
|
|
|
| 1064 |
|
|
/*
|
| 1065 |
|
|
* Get the ratios for processor frequency, bus frequency and interval timer to
|
| 1066 |
|
|
* to base frequency of the platform
|
| 1067 |
|
|
*/
|
| 1068 |
|
|
static inline s64
|
| 1069 |
|
|
ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
|
| 1070 |
|
|
struct pal_freq_ratio *itc_ratio)
|
| 1071 |
|
|
{
|
| 1072 |
|
|
struct ia64_pal_retval iprv;
|
| 1073 |
|
|
PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
|
| 1074 |
|
|
if (proc_ratio)
|
| 1075 |
|
|
*(u64 *)proc_ratio = iprv.v0;
|
| 1076 |
|
|
if (bus_ratio)
|
| 1077 |
|
|
*(u64 *)bus_ratio = iprv.v1;
|
| 1078 |
|
|
if (itc_ratio)
|
| 1079 |
|
|
*(u64 *)itc_ratio = iprv.v2;
|
| 1080 |
|
|
return iprv.status;
|
| 1081 |
|
|
}
|
| 1082 |
|
|
|
| 1083 |
|
|
/* Make the processor enter HALT or one of the implementation dependent low
|
| 1084 |
|
|
* power states where prefetching and execution are suspended and cache and
|
| 1085 |
|
|
* TLB coherency is not maintained.
|
| 1086 |
|
|
*/
|
| 1087 |
|
|
static inline s64
|
| 1088 |
|
|
ia64_pal_halt (u64 halt_state)
|
| 1089 |
|
|
{
|
| 1090 |
|
|
struct ia64_pal_retval iprv;
|
| 1091 |
|
|
PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
|
| 1092 |
|
|
return iprv.status;
|
| 1093 |
|
|
}
|
| 1094 |
|
|
|
| 1095 |
|
|
typedef union pal_power_mgmt_info_u {
|
| 1096 |
|
|
u64 ppmi_data;
|
| 1097 |
|
|
struct {
|
| 1098 |
|
|
u64 exit_latency : 16,
|
| 1099 |
|
|
entry_latency : 16,
|
| 1100 |
|
|
power_consumption : 28,
|
| 1101 |
|
|
im : 1,
|
| 1102 |
|
|
co : 1,
|
| 1103 |
|
|
reserved : 2;
|
| 1104 |
|
|
} pal_power_mgmt_info_s;
|
| 1105 |
|
|
} pal_power_mgmt_info_u_t;
|
| 1106 |
|
|
|
| 1107 |
|
|
/* Return information about processor's optional power management capabilities. */
|
| 1108 |
|
|
static inline s64
|
| 1109 |
|
|
ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
|
| 1110 |
|
|
{
|
| 1111 |
|
|
struct ia64_pal_retval iprv;
|
| 1112 |
|
|
PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
|
| 1113 |
|
|
return iprv.status;
|
| 1114 |
|
|
}
|
| 1115 |
|
|
|
| 1116 |
|
|
/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
|
| 1117 |
|
|
* suspended, but cache and TLB coherency is maintained.
|
| 1118 |
|
|
*/
|
| 1119 |
|
|
static inline s64
|
| 1120 |
|
|
ia64_pal_halt_light (void)
|
| 1121 |
|
|
{
|
| 1122 |
|
|
struct ia64_pal_retval iprv;
|
| 1123 |
|
|
PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
|
| 1124 |
|
|
return iprv.status;
|
| 1125 |
|
|
}
|
| 1126 |
|
|
|
| 1127 |
|
|
/* Clear all the processor error logging registers and reset the indicator that allows
|
| 1128 |
|
|
* the error logging registers to be written. This procedure also checks the pending
|
| 1129 |
|
|
* machine check bit and pending INIT bit and reports their states.
|
| 1130 |
|
|
*/
|
| 1131 |
|
|
static inline s64
|
| 1132 |
|
|
ia64_pal_mc_clear_log (u64 *pending_vector)
|
| 1133 |
|
|
{
|
| 1134 |
|
|
struct ia64_pal_retval iprv;
|
| 1135 |
|
|
PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
|
| 1136 |
|
|
if (pending_vector)
|
| 1137 |
|
|
*pending_vector = iprv.v0;
|
| 1138 |
|
|
return iprv.status;
|
| 1139 |
|
|
}
|
| 1140 |
|
|
|
| 1141 |
|
|
/* Ensure that all outstanding transactions in a processor are completed or that any
|
| 1142 |
|
|
* MCA due to thes outstanding transaction is taken.
|
| 1143 |
|
|
*/
|
| 1144 |
|
|
static inline s64
|
| 1145 |
|
|
ia64_pal_mc_drain (void)
|
| 1146 |
|
|
{
|
| 1147 |
|
|
struct ia64_pal_retval iprv;
|
| 1148 |
|
|
PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
|
| 1149 |
|
|
return iprv.status;
|
| 1150 |
|
|
}
|
| 1151 |
|
|
|
| 1152 |
|
|
/* Return the machine check dynamic processor state */
|
| 1153 |
|
|
static inline s64
|
| 1154 |
|
|
ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
|
| 1155 |
|
|
{
|
| 1156 |
|
|
struct ia64_pal_retval iprv;
|
| 1157 |
|
|
PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
|
| 1158 |
|
|
if (size)
|
| 1159 |
|
|
*size = iprv.v0;
|
| 1160 |
|
|
if (pds)
|
| 1161 |
|
|
*pds = iprv.v1;
|
| 1162 |
|
|
return iprv.status;
|
| 1163 |
|
|
}
|
| 1164 |
|
|
|
| 1165 |
|
|
/* Return processor machine check information */
|
| 1166 |
|
|
static inline s64
|
| 1167 |
|
|
ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
|
| 1168 |
|
|
{
|
| 1169 |
|
|
struct ia64_pal_retval iprv;
|
| 1170 |
|
|
PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
|
| 1171 |
|
|
if (size)
|
| 1172 |
|
|
*size = iprv.v0;
|
| 1173 |
|
|
if (error_info)
|
| 1174 |
|
|
*error_info = iprv.v1;
|
| 1175 |
|
|
return iprv.status;
|
| 1176 |
|
|
}
|
| 1177 |
|
|
|
| 1178 |
|
|
/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
|
| 1179 |
|
|
* attempt to correct any expected machine checks.
|
| 1180 |
|
|
*/
|
| 1181 |
|
|
static inline s64
|
| 1182 |
|
|
ia64_pal_mc_expected (u64 expected, u64 *previous)
|
| 1183 |
|
|
{
|
| 1184 |
|
|
struct ia64_pal_retval iprv;
|
| 1185 |
|
|
PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
|
| 1186 |
|
|
if (previous)
|
| 1187 |
|
|
*previous = iprv.v0;
|
| 1188 |
|
|
return iprv.status;
|
| 1189 |
|
|
}
|
| 1190 |
|
|
|
| 1191 |
|
|
/* Register a platform dependent location with PAL to which it can save
|
| 1192 |
|
|
* minimal processor state in the event of a machine check or initialization
|
| 1193 |
|
|
* event.
|
| 1194 |
|
|
*/
|
| 1195 |
|
|
static inline s64
|
| 1196 |
|
|
ia64_pal_mc_register_mem (u64 physical_addr)
|
| 1197 |
|
|
{
|
| 1198 |
|
|
struct ia64_pal_retval iprv;
|
| 1199 |
|
|
PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
|
| 1200 |
|
|
return iprv.status;
|
| 1201 |
|
|
}
|
| 1202 |
|
|
|
| 1203 |
|
|
/* Restore minimal architectural processor state, set CMC interrupt if necessary
|
| 1204 |
|
|
* and resume execution
|
| 1205 |
|
|
*/
|
| 1206 |
|
|
static inline s64
|
| 1207 |
|
|
ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
|
| 1208 |
|
|
{
|
| 1209 |
|
|
struct ia64_pal_retval iprv;
|
| 1210 |
|
|
PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
|
| 1211 |
|
|
return iprv.status;
|
| 1212 |
|
|
}
|
| 1213 |
|
|
|
| 1214 |
|
|
/* Return the memory attributes implemented by the processor */
|
| 1215 |
|
|
static inline s64
|
| 1216 |
|
|
ia64_pal_mem_attrib (u64 *mem_attrib)
|
| 1217 |
|
|
{
|
| 1218 |
|
|
struct ia64_pal_retval iprv;
|
| 1219 |
|
|
PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
|
| 1220 |
|
|
if (mem_attrib)
|
| 1221 |
|
|
*mem_attrib = iprv.v0 & 0xff;
|
| 1222 |
|
|
return iprv.status;
|
| 1223 |
|
|
}
|
| 1224 |
|
|
|
| 1225 |
|
|
/* Return the amount of memory needed for second phase of processor
|
| 1226 |
|
|
* self-test and the required alignment of memory.
|
| 1227 |
|
|
*/
|
| 1228 |
|
|
static inline s64
|
| 1229 |
|
|
ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
|
| 1230 |
|
|
{
|
| 1231 |
|
|
struct ia64_pal_retval iprv;
|
| 1232 |
|
|
PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
|
| 1233 |
|
|
if (bytes_needed)
|
| 1234 |
|
|
*bytes_needed = iprv.v0;
|
| 1235 |
|
|
if (alignment)
|
| 1236 |
|
|
*alignment = iprv.v1;
|
| 1237 |
|
|
return iprv.status;
|
| 1238 |
|
|
}
|
| 1239 |
|
|
|
| 1240 |
|
|
typedef union pal_perf_mon_info_u {
|
| 1241 |
|
|
u64 ppmi_data;
|
| 1242 |
|
|
struct {
|
| 1243 |
|
|
u64 generic : 8,
|
| 1244 |
|
|
width : 8,
|
| 1245 |
|
|
cycles : 8,
|
| 1246 |
|
|
retired : 8,
|
| 1247 |
|
|
reserved : 32;
|
| 1248 |
|
|
} pal_perf_mon_info_s;
|
| 1249 |
|
|
} pal_perf_mon_info_u_t;
|
| 1250 |
|
|
|
| 1251 |
|
|
/* Return the performance monitor information about what can be counted
|
| 1252 |
|
|
* and how to configure the monitors to count the desired events.
|
| 1253 |
|
|
*/
|
| 1254 |
|
|
static inline s64
|
| 1255 |
|
|
ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
|
| 1256 |
|
|
{
|
| 1257 |
|
|
struct ia64_pal_retval iprv;
|
| 1258 |
|
|
PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
|
| 1259 |
|
|
if (pm_info)
|
| 1260 |
|
|
pm_info->ppmi_data = iprv.v0;
|
| 1261 |
|
|
return iprv.status;
|
| 1262 |
|
|
}
|
| 1263 |
|
|
|
| 1264 |
|
|
/* Specifies the physical address of the processor interrupt block
|
| 1265 |
|
|
* and I/O port space.
|
| 1266 |
|
|
*/
|
| 1267 |
|
|
static inline s64
|
| 1268 |
|
|
ia64_pal_platform_addr (u64 type, u64 physical_addr)
|
| 1269 |
|
|
{
|
| 1270 |
|
|
struct ia64_pal_retval iprv;
|
| 1271 |
|
|
PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
|
| 1272 |
|
|
return iprv.status;
|
| 1273 |
|
|
}
|
| 1274 |
|
|
|
| 1275 |
|
|
/* Set the SAL PMI entrypoint in memory */
|
| 1276 |
|
|
static inline s64
|
| 1277 |
|
|
ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
|
| 1278 |
|
|
{
|
| 1279 |
|
|
struct ia64_pal_retval iprv;
|
| 1280 |
|
|
PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
|
| 1281 |
|
|
return iprv.status;
|
| 1282 |
|
|
}
|
| 1283 |
|
|
|
| 1284 |
|
|
struct pal_features_s;
|
| 1285 |
|
|
/* Provide information about configurable processor features */
|
| 1286 |
|
|
static inline s64
|
| 1287 |
|
|
ia64_pal_proc_get_features (u64 *features_avail,
|
| 1288 |
|
|
u64 *features_status,
|
| 1289 |
|
|
u64 *features_control)
|
| 1290 |
|
|
{
|
| 1291 |
|
|
struct ia64_pal_retval iprv;
|
| 1292 |
|
|
PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
|
| 1293 |
|
|
if (iprv.status == 0) {
|
| 1294 |
|
|
*features_avail = iprv.v0;
|
| 1295 |
|
|
*features_status = iprv.v1;
|
| 1296 |
|
|
*features_control = iprv.v2;
|
| 1297 |
|
|
}
|
| 1298 |
|
|
return iprv.status;
|
| 1299 |
|
|
}
|
| 1300 |
|
|
|
| 1301 |
|
|
/* Enable/disable processor dependent features */
|
| 1302 |
|
|
static inline s64
|
| 1303 |
|
|
ia64_pal_proc_set_features (u64 feature_select)
|
| 1304 |
|
|
{
|
| 1305 |
|
|
struct ia64_pal_retval iprv;
|
| 1306 |
|
|
PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
|
| 1307 |
|
|
return iprv.status;
|
| 1308 |
|
|
}
|
| 1309 |
|
|
|
| 1310 |
|
|
/*
|
| 1311 |
|
|
* Put everything in a struct so we avoid the global offset table whenever
|
| 1312 |
|
|
* possible.
|
| 1313 |
|
|
*/
|
| 1314 |
|
|
typedef struct ia64_ptce_info_s {
|
| 1315 |
|
|
u64 base;
|
| 1316 |
|
|
u32 count[2];
|
| 1317 |
|
|
u32 stride[2];
|
| 1318 |
|
|
} ia64_ptce_info_t;
|
| 1319 |
|
|
|
| 1320 |
|
|
/* Return the information required for the architected loop used to purge
|
| 1321 |
|
|
* (initialize) the entire TC
|
| 1322 |
|
|
*/
|
| 1323 |
|
|
static inline s64
|
| 1324 |
|
|
ia64_get_ptce (ia64_ptce_info_t *ptce)
|
| 1325 |
|
|
{
|
| 1326 |
|
|
struct ia64_pal_retval iprv;
|
| 1327 |
|
|
|
| 1328 |
|
|
if (!ptce)
|
| 1329 |
|
|
return -1;
|
| 1330 |
|
|
|
| 1331 |
|
|
PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
|
| 1332 |
|
|
if (iprv.status == 0) {
|
| 1333 |
|
|
ptce->base = iprv.v0;
|
| 1334 |
|
|
ptce->count[0] = iprv.v1 >> 32;
|
| 1335 |
|
|
ptce->count[1] = iprv.v1 & 0xffffffff;
|
| 1336 |
|
|
ptce->stride[0] = iprv.v2 >> 32;
|
| 1337 |
|
|
ptce->stride[1] = iprv.v2 & 0xffffffff;
|
| 1338 |
|
|
}
|
| 1339 |
|
|
return iprv.status;
|
| 1340 |
|
|
}
|
| 1341 |
|
|
|
| 1342 |
|
|
/* Return info about implemented application and control registers. */
|
| 1343 |
|
|
static inline s64
|
| 1344 |
|
|
ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
|
| 1345 |
|
|
{
|
| 1346 |
|
|
struct ia64_pal_retval iprv;
|
| 1347 |
|
|
PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
|
| 1348 |
|
|
if (reg_info_1)
|
| 1349 |
|
|
*reg_info_1 = iprv.v0;
|
| 1350 |
|
|
if (reg_info_2)
|
| 1351 |
|
|
*reg_info_2 = iprv.v1;
|
| 1352 |
|
|
return iprv.status;
|
| 1353 |
|
|
}
|
| 1354 |
|
|
|
| 1355 |
|
|
typedef union pal_hints_u {
|
| 1356 |
|
|
u64 ph_data;
|
| 1357 |
|
|
struct {
|
| 1358 |
|
|
u64 si : 1,
|
| 1359 |
|
|
li : 1,
|
| 1360 |
|
|
reserved : 62;
|
| 1361 |
|
|
} pal_hints_s;
|
| 1362 |
|
|
} pal_hints_u_t;
|
| 1363 |
|
|
|
| 1364 |
|
|
/* Return information about the register stack and RSE for this processor
|
| 1365 |
|
|
* implementation.
|
| 1366 |
|
|
*/
|
| 1367 |
|
|
static inline s64
|
| 1368 |
|
|
ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
|
| 1369 |
|
|
{
|
| 1370 |
|
|
struct ia64_pal_retval iprv;
|
| 1371 |
|
|
PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
|
| 1372 |
|
|
if (num_phys_stacked)
|
| 1373 |
|
|
*num_phys_stacked = iprv.v0;
|
| 1374 |
|
|
if (hints)
|
| 1375 |
|
|
hints->ph_data = iprv.v1;
|
| 1376 |
|
|
return iprv.status;
|
| 1377 |
|
|
}
|
| 1378 |
|
|
|
| 1379 |
|
|
/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
|
| 1380 |
|
|
* suspended, but cause cache and TLB coherency to be maintained.
|
| 1381 |
|
|
* This is usually called in IA-32 mode.
|
| 1382 |
|
|
*/
|
| 1383 |
|
|
static inline s64
|
| 1384 |
|
|
ia64_pal_shutdown (void)
|
| 1385 |
|
|
{
|
| 1386 |
|
|
struct ia64_pal_retval iprv;
|
| 1387 |
|
|
PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
|
| 1388 |
|
|
return iprv.status;
|
| 1389 |
|
|
}
|
| 1390 |
|
|
|
| 1391 |
|
|
/* Perform the second phase of processor self-test. */
|
| 1392 |
|
|
static inline s64
|
| 1393 |
|
|
ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
|
| 1394 |
|
|
{
|
| 1395 |
|
|
struct ia64_pal_retval iprv;
|
| 1396 |
|
|
PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
|
| 1397 |
|
|
if (self_test_state)
|
| 1398 |
|
|
*self_test_state = iprv.v0;
|
| 1399 |
|
|
return iprv.status;
|
| 1400 |
|
|
}
|
| 1401 |
|
|
|
| 1402 |
|
|
typedef union pal_version_u {
|
| 1403 |
|
|
u64 pal_version_val;
|
| 1404 |
|
|
struct {
|
| 1405 |
|
|
u64 pv_pal_b_rev : 8;
|
| 1406 |
|
|
u64 pv_pal_b_model : 8;
|
| 1407 |
|
|
u64 pv_reserved1 : 8;
|
| 1408 |
|
|
u64 pv_pal_vendor : 8;
|
| 1409 |
|
|
u64 pv_pal_a_rev : 8;
|
| 1410 |
|
|
u64 pv_pal_a_model : 8;
|
| 1411 |
|
|
u64 pv_reserved2 : 16;
|
| 1412 |
|
|
} pal_version_s;
|
| 1413 |
|
|
} pal_version_u_t;
|
| 1414 |
|
|
|
| 1415 |
|
|
|
| 1416 |
|
|
/* Return PAL version information */
|
| 1417 |
|
|
static inline s64
|
| 1418 |
|
|
ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
|
| 1419 |
|
|
{
|
| 1420 |
|
|
struct ia64_pal_retval iprv;
|
| 1421 |
|
|
PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
|
| 1422 |
|
|
if (pal_min_version)
|
| 1423 |
|
|
pal_min_version->pal_version_val = iprv.v0;
|
| 1424 |
|
|
|
| 1425 |
|
|
if (pal_cur_version)
|
| 1426 |
|
|
pal_cur_version->pal_version_val = iprv.v1;
|
| 1427 |
|
|
|
| 1428 |
|
|
return iprv.status;
|
| 1429 |
|
|
}
|
| 1430 |
|
|
|
| 1431 |
|
|
typedef union pal_tc_info_u {
|
| 1432 |
|
|
u64 pti_val;
|
| 1433 |
|
|
struct {
|
| 1434 |
|
|
u64 num_sets : 8,
|
| 1435 |
|
|
associativity : 8,
|
| 1436 |
|
|
num_entries : 16,
|
| 1437 |
|
|
pf : 1,
|
| 1438 |
|
|
unified : 1,
|
| 1439 |
|
|
reduce_tr : 1,
|
| 1440 |
|
|
reserved : 29;
|
| 1441 |
|
|
} pal_tc_info_s;
|
| 1442 |
|
|
} pal_tc_info_u_t;
|
| 1443 |
|
|
|
| 1444 |
|
|
#define tc_reduce_tr pal_tc_info_s.reduce_tr
|
| 1445 |
|
|
#define tc_unified pal_tc_info_s.unified
|
| 1446 |
|
|
#define tc_pf pal_tc_info_s.pf
|
| 1447 |
|
|
#define tc_num_entries pal_tc_info_s.num_entries
|
| 1448 |
|
|
#define tc_associativity pal_tc_info_s.associativity
|
| 1449 |
|
|
#define tc_num_sets pal_tc_info_s.num_sets
|
| 1450 |
|
|
|
| 1451 |
|
|
|
| 1452 |
|
|
/* Return information about the virtual memory characteristics of the processor
|
| 1453 |
|
|
* implementation.
|
| 1454 |
|
|
*/
|
| 1455 |
|
|
static inline s64
|
| 1456 |
|
|
ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
|
| 1457 |
|
|
{
|
| 1458 |
|
|
struct ia64_pal_retval iprv;
|
| 1459 |
|
|
PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
|
| 1460 |
|
|
if (tc_info)
|
| 1461 |
|
|
tc_info->pti_val = iprv.v0;
|
| 1462 |
|
|
if (tc_pages)
|
| 1463 |
|
|
*tc_pages = iprv.v1;
|
| 1464 |
|
|
return iprv.status;
|
| 1465 |
|
|
}
|
| 1466 |
|
|
|
| 1467 |
|
|
/* Get page size information about the virtual memory characteristics of the processor
|
| 1468 |
|
|
* implementation.
|
| 1469 |
|
|
*/
|
| 1470 |
|
|
static inline s64
|
| 1471 |
|
|
ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
|
| 1472 |
|
|
{
|
| 1473 |
|
|
struct ia64_pal_retval iprv;
|
| 1474 |
|
|
PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
|
| 1475 |
|
|
if (tr_pages)
|
| 1476 |
|
|
*tr_pages = iprv.v0;
|
| 1477 |
|
|
if (vw_pages)
|
| 1478 |
|
|
*vw_pages = iprv.v1;
|
| 1479 |
|
|
return iprv.status;
|
| 1480 |
|
|
}
|
| 1481 |
|
|
|
| 1482 |
|
|
typedef union pal_vm_info_1_u {
|
| 1483 |
|
|
u64 pvi1_val;
|
| 1484 |
|
|
struct {
|
| 1485 |
|
|
u64 vw : 1,
|
| 1486 |
|
|
phys_add_size : 7,
|
| 1487 |
|
|
key_size : 8,
|
| 1488 |
|
|
max_pkr : 8,
|
| 1489 |
|
|
hash_tag_id : 8,
|
| 1490 |
|
|
max_dtr_entry : 8,
|
| 1491 |
|
|
max_itr_entry : 8,
|
| 1492 |
|
|
max_unique_tcs : 8,
|
| 1493 |
|
|
num_tc_levels : 8;
|
| 1494 |
|
|
} pal_vm_info_1_s;
|
| 1495 |
|
|
} pal_vm_info_1_u_t;
|
| 1496 |
|
|
|
| 1497 |
|
|
typedef union pal_vm_info_2_u {
|
| 1498 |
|
|
u64 pvi2_val;
|
| 1499 |
|
|
struct {
|
| 1500 |
|
|
u64 impl_va_msb : 8,
|
| 1501 |
|
|
rid_size : 8,
|
| 1502 |
|
|
reserved : 48;
|
| 1503 |
|
|
} pal_vm_info_2_s;
|
| 1504 |
|
|
} pal_vm_info_2_u_t;
|
| 1505 |
|
|
|
| 1506 |
|
|
/* Get summary information about the virtual memory characteristics of the processor
|
| 1507 |
|
|
* implementation.
|
| 1508 |
|
|
*/
|
| 1509 |
|
|
static inline s64
|
| 1510 |
|
|
ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
|
| 1511 |
|
|
{
|
| 1512 |
|
|
struct ia64_pal_retval iprv;
|
| 1513 |
|
|
PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
|
| 1514 |
|
|
if (vm_info_1)
|
| 1515 |
|
|
vm_info_1->pvi1_val = iprv.v0;
|
| 1516 |
|
|
if (vm_info_2)
|
| 1517 |
|
|
vm_info_2->pvi2_val = iprv.v1;
|
| 1518 |
|
|
return iprv.status;
|
| 1519 |
|
|
}
|
| 1520 |
|
|
|
| 1521 |
|
|
typedef union pal_itr_valid_u {
|
| 1522 |
|
|
u64 piv_val;
|
| 1523 |
|
|
struct {
|
| 1524 |
|
|
u64 access_rights_valid : 1,
|
| 1525 |
|
|
priv_level_valid : 1,
|
| 1526 |
|
|
dirty_bit_valid : 1,
|
| 1527 |
|
|
mem_attr_valid : 1,
|
| 1528 |
|
|
reserved : 60;
|
| 1529 |
|
|
} pal_tr_valid_s;
|
| 1530 |
|
|
} pal_tr_valid_u_t;
|
| 1531 |
|
|
|
| 1532 |
|
|
/* Read a translation register */
|
| 1533 |
|
|
static inline s64
|
| 1534 |
|
|
ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
|
| 1535 |
|
|
{
|
| 1536 |
|
|
struct ia64_pal_retval iprv;
|
| 1537 |
|
|
PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)__pa(tr_buffer));
|
| 1538 |
|
|
if (tr_valid)
|
| 1539 |
|
|
tr_valid->piv_val = iprv.v0;
|
| 1540 |
|
|
return iprv.status;
|
| 1541 |
|
|
}
|
| 1542 |
|
|
|
| 1543 |
|
|
static inline s64
|
| 1544 |
|
|
ia64_pal_prefetch_visibility (void)
|
| 1545 |
|
|
{
|
| 1546 |
|
|
struct ia64_pal_retval iprv;
|
| 1547 |
|
|
PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, 0, 0, 0);
|
| 1548 |
|
|
return iprv.status;
|
| 1549 |
|
|
}
|
| 1550 |
|
|
|
| 1551 |
|
|
#endif /* __ASSEMBLY__ */
|
| 1552 |
|
|
|
| 1553 |
|
|
#endif /* __KERNEL__ */
|
| 1554 |
|
|
|
| 1555 |
|
|
#endif /* _ASM_IA64_PAL_H */
|
