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[/] [or1k/] [tags/] [LINUX_2_4_26_OR32/] [linux/] [linux-2.4/] [include/] [asm-mips/] [prefetch.h] - Blame information for rev 1765

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1 1276 phoenix
/*
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * Copyright (C) 2003 by Ralf Baechle
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 */
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#ifndef __ASM_PREFETCH_H
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#define __ASM_PREFETCH_H
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/*
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 * R5000 and RM5200 implements pref and prefx instructions but they're nops, so
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 * rather than wasting time we pretend these processors don't support
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 * prefetching at all.
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 *
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 * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
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 * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
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 *
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 * Hell (and the book on my shelf I can't open ...) know what the R8000 does.
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 *
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 * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
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 * Pref_PrepareForStore also.
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 *
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 * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64;
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 * it's Pref_WriteBackInvalidate is a nop.
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 *
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 * VR7701 only implements the Load prefetch.
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 *
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 * Finally MIPS32 and MIPS64 implement all of the following hints.
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 */
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#define Pref_Load                       0
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#define Pref_Store                      1
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                                                /* 2 and 3 are reserved */
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#define Pref_LoadStreamed               4
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#define Pref_StoreStreamed              5
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#define Pref_LoadRetained               6
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#define Pref_StoreRetained              7
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                                                /* 8 ... 24 are reserved */
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#define Pref_WriteBackInvalidate        25
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#define Pref_PrepareForStore            30
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#endif /* __ASM_PREFETCH_H */

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