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[/] [or1k/] [tags/] [LINUX_2_4_26_OR32/] [linux/] [linux-2.4/] [include/] [asm-sh/] [hitachi_7751se.h] - Blame information for rev 1765

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1 1275 phoenix
#ifndef __ASM_SH_HITACHI_7751SE_H
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#define __ASM_SH_HITACHI_7751SE_H
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/*
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 * linux/include/asm-sh/hitachi_7751se.h
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 *
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 * Copyright (C) 2000  Kazumoto Kojima
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 *
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 * Hitachi SolutionEngine support
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 * Modified for 7751 Solution Engine by
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 * Ian da Silva and Jeremy Siegel, 2001.
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 */
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/* Box specific addresses.  */
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#define PA_ROM          0x00000000      /* EPROM */
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#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
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#define PA_FROM         0x01000000      /* EPROM */
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#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
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#define PA_EXT1         0x04000000
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#define PA_EXT1_SIZE    0x04000000
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#define PA_EXT2         0x08000000
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#define PA_EXT2_SIZE    0x04000000
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#define PA_SDRAM        0x0c000000
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#define PA_SDRAM_SIZE   0x04000000
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#define PA_EXT4         0x12000000
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#define PA_EXT4_SIZE    0x02000000
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#define PA_EXT5         0x14000000
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#define PA_EXT5_SIZE    0x04000000
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#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
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#define PA_DIPSW0       0xb9000000      /* Dip switch 5,6 */
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#define PA_DIPSW1       0xb9000002      /* Dip switch 7,8 */
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#define PA_LED          0xba000000      /* LED */
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#define PA_BCR          0xbb000000      /* FPGA on the MS7751SE01 */
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#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controler */
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#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
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#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
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#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
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#define MRSHPC_MODE     (PA_MRSHPC + 4)
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#define MRSHPC_OPTION   (PA_MRSHPC + 6)
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#define MRSHPC_CSR      (PA_MRSHPC + 8)
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#define MRSHPC_ISR      (PA_MRSHPC + 10)
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#define MRSHPC_ICR      (PA_MRSHPC + 12)
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#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
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#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
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#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
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#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
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#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
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#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
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#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
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#define MRSHPC_CDCR     (PA_MRSHPC + 28)
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
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#define BCR_ILCRA       (PA_BCR + 0)
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#define BCR_ILCRB       (PA_BCR + 2)
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#define BCR_ILCRC       (PA_BCR + 4)
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#define BCR_ILCRD       (PA_BCR + 6)
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#define BCR_ILCRE       (PA_BCR + 8)
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#define BCR_ILCRF       (PA_BCR + 10)
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#define BCR_ILCRG       (PA_BCR + 12)
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#define IRQ_79C973      13
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#endif  /* __ASM_SH_HITACHI_7751SE_H */

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