| 1 |
1275 |
phoenix |
#ifndef __ASM_SH_IRQ_H
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#define __ASM_SH_IRQ_H
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/*
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*
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* linux/include/asm-sh/irq.h
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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*
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*/
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#if defined(CONFIG_CPU_SUBTYPE_SH7300)
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#include <asm/irq-sh7300.h>
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#else
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#include <linux/config.h>
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#include <asm/machvec.h>
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#include <asm/ptrace.h> /* for pt_regs */
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#if defined(__sh3__)
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#define INTC_IPRA 0xfffffee2UL
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#define INTC_IPRB 0xfffffee4UL
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#elif defined(__SH4__)
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#define INTC_IPRA 0xffd00004UL
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#define INTC_IPRB 0xffd00008UL
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#define INTC_IPRC 0xffd0000cUL
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#if defined(CONFIG_CPU_SUBTYPE_SH7751)
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# define INTC_IPRD 0xffd00010UL
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#endif
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#endif
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#define TIMER_IRQ 16
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#define TIMER_IPR_ADDR INTC_IPRA
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#define TIMER_IPR_POS 3
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#define TIMER_PRIORITY 2
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#define RTC_IRQ 22
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#define RTC_IPR_ADDR INTC_IPRA
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#define RTC_IPR_POS 0
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#define RTC_PRIORITY TIMER_PRIORITY
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#if defined(__sh3__)
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#define DMTE0_IRQ 48
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#define DMTE1_IRQ 49
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#define DMTE2_IRQ 50
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#define DMTE3_IRQ 51
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#define DMA_IPR_ADDR INTC_IPRE
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#define DMA_IPR_POS 3
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#define DMA_PRIORITY 7
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#elif defined(__SH4__)
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#define DMTE0_IRQ 34
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#define DMTE1_IRQ 35
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#define DMTE2_IRQ 36
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#define DMTE3_IRQ 37
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#define DMAE_IRQ 38
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#define DMA_IPR_ADDR INTC_IPRC
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#define DMA_IPR_POS 2
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#define DMA_PRIORITY 7
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#endif
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#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
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defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
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defined (CONFIG_CPU_SUBTYPE_SH7751)
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#define SCI_ERI_IRQ 23
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#define SCI_RXI_IRQ 24
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#define SCI_TXI_IRQ 25
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#define SCI_IPR_ADDR INTC_IPRB
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#define SCI_IPR_POS 1
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#define SCI_PRIORITY 3
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
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#define SCIF_ERI_IRQ 56
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#define SCIF_RXI_IRQ 57
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#define SCIF_BRI_IRQ 58
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#define SCIF_TXI_IRQ 59
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#define SCIF_IPR_ADDR INTC_IPRE
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#define SCIF_IPR_POS 1
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#define SCIF_PRIORITY 3
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#define IRDA_ERI_IRQ 52
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#define IRDA_RXI_IRQ 53
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#define IRDA_BRI_IRQ 54
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#define IRDA_TXI_IRQ 55
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#define IRDA_IPR_ADDR INTC_IPRE
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#define IRDA_IPR_POS 2
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#define IRDA_PRIORITY 3
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_ST40)
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#define SCIF_ERI_IRQ 40
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#define SCIF_RXI_IRQ 41
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#define SCIF_BRI_IRQ 42
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#define SCIF_TXI_IRQ 43
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#define SCIF_IPR_ADDR INTC_IPRC
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#define SCIF_IPR_POS 1
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#define SCIF_PRIORITY 3
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#if defined(CONFIG_CPU_SUBTYPE_ST40)
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#define SCIF1_ERI_IRQ 23
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#define SCIF1_RXI_IRQ 24
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#define SCIF1_BRI_IRQ 25
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#define SCIF1_TXI_IRQ 26
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#define SCIF1_IPR_ADDR INTC_IPRB
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#define SCIF1_IPR_POS 1
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#define SCIF1_PRIORITY 3
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#endif
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#endif
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/* NR_IRQS is made from three components:
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* 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
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* 2. PINT_NR_IRQS - number of PINT interrupts
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* 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
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*/
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/* 1. ONCHIP_NR_IRQS */
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#ifdef CONFIG_SH_GENERIC
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# define ONCHIP_NR_IRQS 144
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#else
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# if defined(CONFIG_CPU_SUBTYPE_SH7707)
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# define ONCHIP_NR_IRQS 64
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# define PINT_NR_IRQS 16
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# elif defined(CONFIG_CPU_SUBTYPE_SH7708)
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# define ONCHIP_NR_IRQS 32
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# elif defined(CONFIG_CPU_SUBTYPE_SH7709)
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# define ONCHIP_NR_IRQS 64 // Actually 61
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# define PINT_NR_IRQS 16
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# elif defined(CONFIG_CPU_SUBTYPE_SH7750)
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# define ONCHIP_NR_IRQS 48 // Actually 44
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# elif defined(CONFIG_CPU_SUBTYPE_SH7751)
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# define ONCHIP_NR_IRQS 72
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# elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define ONCHIP_NR_IRQS 72
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# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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# define ONCHIP_NR_IRQS 144
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# elif defined(CONFIG_CPU_SUBTYPE_ST40GX1)
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# define ONCHIP_NR_IRQS 176
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# else
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# error Unknown chip
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# endif
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#endif
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/* 2. PINT_NR_IRQS */
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#ifdef CONFIG_SH_GENERIC
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# define PINT_NR_IRQS 16
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#else
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# ifndef PINT_NR_IRQS
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# define PINT_NR_IRQS 0
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# endif
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#endif
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#if PINT_NR_IRQS > 0
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# define PINT_IRQ_BASE ONCHIP_NR_IRQS
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#endif
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/* 3. OFFCHIP_NR_IRQS */
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#ifdef CONFIG_SH_GENERIC
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# define OFFCHIP_NR_IRQS 16
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#else
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# if defined(CONFIG_HD64461)
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# define OFFCHIP_NR_IRQS 16
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# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
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# define OFFCHIP_NR_IRQS 48
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# elif defined(CONFIG_HD64465)
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# define OFFCHIP_NR_IRQS 16
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# elif defined (CONFIG_SH_EC3104)
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# define OFFCHIP_NR_IRQS 16
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# elif defined (CONFIG_SH_DREAMCAST)
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# define OFFCHIP_NR_IRQS 96
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# else
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# define OFFCHIP_NR_IRQS 0
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# endif
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#endif
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#if OFFCHIP_NR_IRQS > 0
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# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
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#endif
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/* NR_IRQS. 1+2+3 */
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#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
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/* In a generic kernel, NR_IRQS is an upper bound, and we should use
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* ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
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*/
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#ifdef CONFIG_SH_GENERIC
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# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
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#else
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# define ACTUAL_NR_IRQS NR_IRQS
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#endif
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extern void disable_irq(unsigned int);
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extern void disable_irq_nosync(unsigned int);
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extern void enable_irq(unsigned int);
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/*
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* Simple Mask Register Support
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*/
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extern void make_maskreg_irq(unsigned int irq);
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extern unsigned short *irq_mask_register;
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/*
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* Function for "on chip support modules".
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*/
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extern void make_ipr_irq(unsigned int irq, unsigned int addr,
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int pos, int priority);
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extern void make_imask_irq(unsigned int irq);
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
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#define INTC_IRR0 0xa4000004UL
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#define INTC_IRR1 0xa4000006UL
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#define INTC_IRR2 0xa4000008UL
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#define INTC_ICR0 0xfffffee0UL
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#define INTC_ICR1 0xa4000010UL
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#define INTC_ICR2 0xa4000012UL
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#define INTC_INTER 0xa4000014UL
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#define INTC_IPRC 0xa4000016UL
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#define INTC_IPRD 0xa4000018UL
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#define INTC_IPRE 0xa400001aUL
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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#define INTC_IPRF 0xa400001cUL
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#endif
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#define PORT_PACR 0xa4000100UL
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#define PORT_PBCR 0xa4000102UL
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#define PORT_PCCR 0xa4000104UL
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#define PORT_PFCR 0xa400010aUL
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#define PORT_PADR 0xa4000120UL
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#define PORT_PBDR 0xa4000122UL
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#define PORT_PCDR 0xa4000124UL
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#define PORT_PFDR 0xa400012aUL
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#define IRQ0_IRQ 32
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#define IRQ1_IRQ 33
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#define IRQ2_IRQ 34
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#define IRQ3_IRQ 35
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#define IRQ4_IRQ 36
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#define IRQ5_IRQ 37
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#define IRQ0_IPR_ADDR INTC_IPRC
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#define IRQ1_IPR_ADDR INTC_IPRC
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#define IRQ2_IPR_ADDR INTC_IPRC
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#define IRQ3_IPR_ADDR INTC_IPRC
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#define IRQ4_IPR_ADDR INTC_IPRD
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#define IRQ5_IPR_ADDR INTC_IPRD
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#define IRQ0_IPR_POS 0
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#define IRQ1_IPR_POS 1
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#define IRQ2_IPR_POS 2
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#define IRQ3_IPR_POS 3
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#define IRQ4_IPR_POS 0
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#define IRQ5_IPR_POS 1
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#define IRQ0_PRIORITY 1
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#define IRQ1_PRIORITY 1
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#define IRQ2_PRIORITY 1
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#define IRQ3_PRIORITY 1
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#define IRQ4_PRIORITY 1
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#define IRQ5_PRIORITY 1
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#define PINT0_IRQ 40
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#define PINT8_IRQ 41
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#define PINT0_IPR_ADDR INTC_IPRD
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#define PINT8_IPR_ADDR INTC_IPRD
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| 267 |
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#define PINT0_IPR_POS 3
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#define PINT8_IPR_POS 2
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#define PINT0_PRIORITY 2
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#define PINT8_PRIORITY 2
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extern int ipr_irq_demux(int irq);
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#define __irq_demux(irq) ipr_irq_demux(irq)
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| 274 |
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| 275 |
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#else
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#define __irq_demux(irq) irq
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| 277 |
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#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
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| 279 |
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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| 280 |
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defined(CONFIG_CPU_SUBTYPE_ST40) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
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| 281 |
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#define INTC_ICR 0xffd00000
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| 282 |
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#define INTC_ICR_NMIL (1<<15)
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| 283 |
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#define INTC_ICR_MAI (1<<14)
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| 284 |
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#define INTC_ICR_NMIB (1<<9)
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| 285 |
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#define INTC_ICR_NMIE (1<<8)
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| 286 |
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#define INTC_ICR_IRLM (1<<7)
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| 287 |
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#endif
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| 288 |
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| 289 |
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#ifdef CONFIG_CPU_SUBTYPE_ST40
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| 290 |
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#define INTC2_FIRST_IRQ 64
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| 291 |
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#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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| 292 |
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#define NR_INTC2_IRQS 80
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| 293 |
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#elif defined(CONFIG_CPU_SUBTYPE_ST40GX1)
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| 294 |
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#define NR_INTC2_IRQS 112
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| 295 |
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#else
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| 296 |
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#error Unknown CPU
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| 297 |
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#endif
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| 298 |
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| 299 |
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#define INTC2_BASE 0xfe080000
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| 300 |
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#define INTC2_INTC2MODE (INTC2_BASE+0x80)
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| 301 |
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| 302 |
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#define INTC2_INTPRI_OFFSET 0x00
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| 303 |
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#define INTC2_INTREQ_OFFSET 0x20
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| 304 |
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#define INTC2_INTMSK_OFFSET 0x40
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| 305 |
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#define INTC2_INTMSKCLR_OFFSET 0x60
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| 306 |
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| 307 |
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void make_intc2_irq(unsigned int irq,
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| 308 |
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unsigned int ipr_offset, unsigned int ipr_shift,
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| 309 |
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unsigned int msk_offset, unsigned int msk_shift,
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| 310 |
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unsigned int priority);
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| 311 |
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void init_IRQ_intc2(void);
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| 312 |
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void intc2_add_clear_irq(int irq, int (*fn)(int));
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| 313 |
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#endif
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| 314 |
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| 315 |
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#ifdef CONFIG_SH_GENERIC
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| 316 |
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| 317 |
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static __inline__ int irq_demux(int irq)
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| 318 |
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{
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| 319 |
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if (sh_mv.mv_irq_demux) {
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| 320 |
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irq = sh_mv.mv_irq_demux(irq);
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| 321 |
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}
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| 322 |
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return __irq_demux(irq);
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| 323 |
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}
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#elif defined(CONFIG_SH_BIGSUR)
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| 326 |
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|
| 327 |
|
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extern int bigsur_irq_demux(int irq);
|
| 328 |
|
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#define irq_demux(irq) bigsur_irq_demux(irq)
|
| 329 |
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|
|
| 330 |
|
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#elif defined(CONFIG_HD64461)
|
| 331 |
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|
|
| 332 |
|
|
extern int hd64461_irq_demux(int irq);
|
| 333 |
|
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#define irq_demux(irq) hd64461_irq_demux(irq)
|
| 334 |
|
|
|
| 335 |
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#elif defined(CONFIG_HD64465)
|
| 336 |
|
|
|
| 337 |
|
|
extern int hd64465_irq_demux(int irq);
|
| 338 |
|
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#define irq_demux(irq) hd64465_irq_demux(irq)
|
| 339 |
|
|
|
| 340 |
|
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#elif defined(CONFIG_SH_EC3104)
|
| 341 |
|
|
|
| 342 |
|
|
extern int ec3104_irq_demux(int irq);
|
| 343 |
|
|
#define irq_demux ec3104_irq_demux
|
| 344 |
|
|
|
| 345 |
|
|
#elif defined(CONFIG_SH_CAT68701)
|
| 346 |
|
|
|
| 347 |
|
|
extern int cat68701_irq_demux(int irq);
|
| 348 |
|
|
#define irq_demux cat68701_irq_demux
|
| 349 |
|
|
|
| 350 |
|
|
#elif defined(CONFIG_SH_DREAMCAST)
|
| 351 |
|
|
|
| 352 |
|
|
extern int systemasic_irq_demux(int irq);
|
| 353 |
|
|
#define irq_demux systemasic_irq_demux
|
| 354 |
|
|
|
| 355 |
|
|
#else
|
| 356 |
|
|
|
| 357 |
|
|
#define irq_demux(irq) __irq_demux(irq)
|
| 358 |
|
|
|
| 359 |
|
|
#endif
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
#endif /* !CONFIG_CPU_SUBTYPE_SH7300 */
|
| 363 |
|
|
|
| 364 |
|
|
#endif /* __ASM_SH_IRQ_H */
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