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phoenix |
/* $Id: psrcompat.h,v 1.1.1.1 2004-04-15 03:01:07 phoenix Exp $ */
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#ifndef _SPARC64_PSRCOMPAT_H
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#define _SPARC64_PSRCOMPAT_H
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#include <asm/pstate.h>
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/* Old 32-bit PSR fields for the compatability conversion code. */
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#define PSR_CWP 0x0000001f /* current window pointer */
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#define PSR_ET 0x00000020 /* enable traps field */
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#define PSR_PS 0x00000040 /* previous privilege level */
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#define PSR_S 0x00000080 /* current privilege level */
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#define PSR_PIL 0x00000f00 /* processor interrupt level */
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#define PSR_EF 0x00001000 /* enable floating point */
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#define PSR_EC 0x00002000 /* enable co-processor */
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#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
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#define PSR_ICC 0x00f00000 /* integer condition codes */
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#define PSR_C 0x00100000 /* carry bit */
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#define PSR_V 0x00200000 /* overflow bit */
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#define PSR_Z 0x00400000 /* zero bit */
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#define PSR_N 0x00800000 /* negative bit */
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#define PSR_VERS 0x0f000000 /* cpu-version field */
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#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
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#define PSR_V8PLUS 0xff000000 /* fake impl/ver, meaning a 64bit CPU is present */
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#define PSR_XCC 0x000f0000 /* if PSR_V8PLUS, this is %xcc */
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extern inline unsigned int tstate_to_psr(unsigned long tstate)
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{
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return ((tstate & TSTATE_CWP) |
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PSR_S |
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((tstate & TSTATE_ICC) >> 12) |
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((tstate & TSTATE_XCC) >> 20) |
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PSR_V8PLUS);
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}
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extern inline unsigned long psr_to_tstate_icc(unsigned int psr)
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{
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unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
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if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
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tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
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return tstate;
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}
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#endif /* !(_SPARC64_PSRCOMPAT_H) */
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