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phoenix |
/* $Id: system.h,v 1.1.1.1 2004-04-15 03:01:07 phoenix Exp $ */
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#ifndef __SPARC64_SYSTEM_H
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#define __SPARC64_SYSTEM_H
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#include <linux/config.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/asm_offsets.h>
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#include <asm/visasm.h>
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#ifndef __ASSEMBLY__
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/*
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* Sparc (general) CPU types
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*/
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enum sparc_cpu {
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sun4 = 0x00,
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sun4c = 0x01,
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sun4m = 0x02,
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sun4d = 0x03,
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sun4e = 0x04,
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sun4u = 0x05, /* V8 ploos ploos */
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sun_unknown = 0x06,
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ap1000 = 0x07, /* almost a sun4m */
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};
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#define sparc_cpu_model sun4u
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/* This cannot ever be a sun4c nor sun4 :) That's just history. */
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#define ARCH_SUN4C_SUN4 0
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#define ARCH_SUN4 0
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#endif
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#define setipl(__new_ipl) \
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__asm__ __volatile__("wrpr %0, %%pil" : : "r" (__new_ipl) : "memory")
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#define __cli() \
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__asm__ __volatile__("wrpr 15, %%pil" : : : "memory")
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#define __sti() \
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__asm__ __volatile__("wrpr 0, %%pil" : : : "memory")
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#define getipl() \
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({ unsigned long retval; __asm__ __volatile__("rdpr %%pil, %0" : "=r" (retval)); retval; })
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#define swap_pil(__new_pil) \
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({ unsigned long retval; \
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__asm__ __volatile__("rdpr %%pil, %0\n\t" \
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"wrpr %1, %%pil" \
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: "=&r" (retval) \
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: "r" (__new_pil) \
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: "memory"); \
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retval; \
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})
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#define read_pil_and_cli() \
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({ unsigned long retval; \
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__asm__ __volatile__("rdpr %%pil, %0\n\t" \
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"wrpr 15, %%pil" \
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: "=r" (retval) \
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: : "memory"); \
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retval; \
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})
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#define read_pil_and_sti() \
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({ unsigned long retval; \
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__asm__ __volatile__("rdpr %%pil, %0\n\t" \
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"wrpr 0, %%pil" \
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: "=r" (retval) \
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: : "memory"); \
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retval; \
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})
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#define __save_flags(flags) ((flags) = getipl())
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#define __save_and_cli(flags) ((flags) = read_pil_and_cli())
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#define __save_and_sti(flags) ((flags) = read_pil_and_sti())
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#define __restore_flags(flags) setipl((flags))
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#define local_irq_disable() __cli()
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#define local_irq_enable() __sti()
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#define local_irq_save(flags) __save_and_cli(flags)
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#define local_irq_set(flags) __save_and_sti(flags)
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#define local_irq_restore(flags) __restore_flags(flags)
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#ifndef CONFIG_SMP
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#define cli() __cli()
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#define sti() __sti()
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#define save_flags(x) __save_flags(x)
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#define restore_flags(x) __restore_flags(x)
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#define save_and_cli(x) __save_and_cli(x)
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#else
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#ifndef __ASSEMBLY__
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extern void __global_cli(void);
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extern void __global_sti(void);
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extern unsigned long __global_save_flags(void);
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extern void __global_restore_flags(unsigned long flags);
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#endif
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#define cli() __global_cli()
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#define sti() __global_sti()
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#define save_flags(x) ((x) = __global_save_flags())
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#define restore_flags(flags) __global_restore_flags(flags)
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#define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
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#endif
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#define nop() __asm__ __volatile__ ("nop")
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#define membar(type) __asm__ __volatile__ ("membar " type : : : "memory");
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#define mb() \
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membar("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad");
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#define rmb() membar("#LoadLoad")
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#define wmb() membar("#StoreStore")
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#define set_mb(__var, __value) \
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do { __var = __value; membar("#StoreLoad | #StoreStore"); } while(0)
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#define set_wmb(__var, __value) \
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do { __var = __value; membar("#StoreStore"); } while(0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#else
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#define smp_mb() __asm__ __volatile__("":::"memory");
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#define smp_rmb() __asm__ __volatile__("":::"memory");
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#define smp_wmb() __asm__ __volatile__("":::"memory");
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#endif
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#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
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#define flushw_all() __asm__ __volatile__("flushw")
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/* Performance counter register access. */
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#define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
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#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p));
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#define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
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/* Blackbird errata workaround. See commentary in
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* arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
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* for more information.
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*/
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#define reset_pic() \
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__asm__ __volatile__("ba,pt %xcc, 99f\n\t" \
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".align 64\n" \
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"99:wr %g0, 0x0, %pic\n\t" \
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"rd %pic, %g0")
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#ifndef __ASSEMBLY__
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extern void synchronize_user_stack(void);
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extern void __flushw_user(void);
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#define flushw_user() __flushw_user()
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#define flush_user_windows flushw_user
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#define flush_register_windows flushw_all
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#define prepare_to_switch flushw_all
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#ifndef CONFIG_DEBUG_SPINLOCK
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#define CHECK_LOCKS(PREV) do { } while(0)
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#else /* CONFIG_DEBUG_SPINLOCK */
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#define CHECK_LOCKS(PREV) \
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if ((PREV)->thread.smp_lock_count) { \
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unsigned long rpc; \
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__asm__ __volatile__("mov %%i7, %0" : "=r" (rpc)); \
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printk(KERN_CRIT "(%s)[%d]: Sleeping with %d locks held!\n", \
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(PREV)->comm, (PREV)->pid, \
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(PREV)->thread.smp_lock_count); \
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printk(KERN_CRIT "(%s)[%d]: Last lock at %08x\n", \
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(PREV)->comm, (PREV)->pid, \
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(PREV)->thread.smp_lock_pc); \
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printk(KERN_CRIT "(%s)[%d]: Sched caller %016lx\n", \
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(PREV)->comm, (PREV)->pid, rpc); \
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}
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#endif /* !(CONFIG_DEBUG_SPINLOCK) */
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/* See what happens when you design the chip correctly?
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*
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* We tell gcc we clobber all non-fixed-usage registers except
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* for l0/l1. It will use one for 'next' and the other to hold
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* the output value of 'last'. 'next' is not referenced again
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* past the invocation of switch_to in the scheduler, so we need
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* not preserve it's value. Hairy, but it lets us remove 2 loads
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* and 2 stores in this critical code path. -DaveM
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*/
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#define switch_to(prev, next, last) \
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do { CHECK_LOCKS(prev); \
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if (current->thread.flags & SPARC_FLAG_PERFCTR) { \
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unsigned long __tmp; \
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read_pcr(__tmp); \
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current->thread.pcr_reg = __tmp; \
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read_pic(__tmp); \
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current->thread.kernel_cntd0 += (unsigned int)(__tmp); \
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current->thread.kernel_cntd1 += ((__tmp) >> 32); \
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} \
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save_and_clear_fpu(); \
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/* If you are tempted to conditionalize the following */ \
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/* so that ASI is only written if it changes, think again. */ \
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__asm__ __volatile__("wr %%g0, %0, %%asi" \
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: : "r" (next->thread.current_ds.seg)); \
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__asm__ __volatile__( \
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"mov %%g6, %%g5\n\t" \
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"wrpr %%g0, 0x95, %%pstate\n\t" \
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"stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
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"stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
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"rdpr %%wstate, %%o5\n\t" \
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"stx %%o6, [%%g6 + %3]\n\t" \
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"stb %%o5, [%%g6 + %2]\n\t" \
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"rdpr %%cwp, %%o5\n\t" \
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"stb %%o5, [%%g6 + %5]\n\t" \
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"mov %1, %%g6\n\t" \
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"ldub [%1 + %5], %%g1\n\t" \
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"wrpr %%g1, %%cwp\n\t" \
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"ldx [%%g6 + %3], %%o6\n\t" \
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"ldub [%%g6 + %2], %%o5\n\t" \
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"ldub [%%g6 + %4], %%o7\n\t" \
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"mov %%g6, %%l2\n\t" \
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"wrpr %%o5, 0x0, %%wstate\n\t" \
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"ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
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"ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
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"wrpr %%g0, 0x94, %%pstate\n\t" \
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"mov %%l2, %%g6\n\t" \
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"wrpr %%g0, 0x96, %%pstate\n\t" \
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"andcc %%o7, %6, %%g0\n\t" \
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"bne,pn %%icc, ret_from_syscall\n\t" \
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" mov %%g5, %0\n\t" \
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: "=&r" (last) \
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: "r" (next), \
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"i" ((const unsigned long)(&((struct task_struct *)0)->thread.wstate)),\
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"i" ((const unsigned long)(&((struct task_struct *)0)->thread.ksp)), \
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"i" ((const unsigned long)(&((struct task_struct *)0)->thread.flags)),\
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"i" ((const unsigned long)(&((struct task_struct *)0)->thread.cwp)), \
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"i" (SPARC_FLAG_NEWCHILD) \
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: "cc", \
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"g1", "g2", "g3", "g5", "g7", \
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"l2", "l3", "l4", "l5", "l6", "l7", \
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"i0", "i1", "i2", "i3", "i4", "i5", \
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| 238 |
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"o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
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/* If you fuck with this, update ret_from_syscall code too. */ \
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if (current->thread.flags & SPARC_FLAG_PERFCTR) { \
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| 241 |
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write_pcr(current->thread.pcr_reg); \
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reset_pic(); \
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} \
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} while(0)
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| 246 |
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extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
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{
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| 248 |
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__asm__ __volatile__(
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| 249 |
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" mov %0, %%g5\n"
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| 250 |
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"1: lduw [%2], %%g7\n"
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| 251 |
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" cas [%2], %%g7, %0\n"
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| 252 |
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" cmp %%g7, %0\n"
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| 253 |
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" bne,a,pn %%icc, 1b\n"
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| 254 |
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" mov %%g5, %0\n"
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| 255 |
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" membar #StoreLoad | #StoreStore\n"
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| 256 |
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: "=&r" (val)
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| 257 |
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: "0" (val), "r" (m)
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| 258 |
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: "g5", "g7", "cc", "memory");
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| 259 |
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return val;
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| 260 |
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}
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| 261 |
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| 262 |
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extern __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
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| 263 |
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{
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| 264 |
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__asm__ __volatile__(
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| 265 |
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" mov %0, %%g5\n"
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| 266 |
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"1: ldx [%2], %%g7\n"
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| 267 |
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" casx [%2], %%g7, %0\n"
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| 268 |
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" cmp %%g7, %0\n"
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| 269 |
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" bne,a,pn %%xcc, 1b\n"
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| 270 |
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" mov %%g5, %0\n"
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| 271 |
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" membar #StoreLoad | #StoreStore\n"
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| 272 |
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: "=&r" (val)
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| 273 |
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: "0" (val), "r" (m)
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| 274 |
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: "g5", "g7", "cc", "memory");
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| 275 |
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return val;
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| 276 |
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}
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| 277 |
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| 278 |
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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| 279 |
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#define tas(ptr) (xchg((ptr),1))
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| 280 |
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| 281 |
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extern void __xchg_called_with_bad_pointer(void);
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| 282 |
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| 283 |
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static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
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| 284 |
|
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int size)
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| 285 |
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{
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| 286 |
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switch (size) {
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| 287 |
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case 4:
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| 288 |
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return xchg32(ptr, x);
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| 289 |
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case 8:
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| 290 |
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return xchg64(ptr, x);
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| 291 |
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};
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| 292 |
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__xchg_called_with_bad_pointer();
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| 293 |
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return x;
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| 294 |
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}
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| 295 |
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| 296 |
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extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
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| 297 |
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|
| 298 |
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/*
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| 299 |
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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| 300 |
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* store NEW in MEM. Return the initial value in MEM. Success is
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| 301 |
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* indicated by comparing RETURN with OLD.
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| 302 |
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*/
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| 303 |
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|
|
| 304 |
|
|
#define __HAVE_ARCH_CMPXCHG 1
|
| 305 |
|
|
|
| 306 |
|
|
extern __inline__ unsigned long
|
| 307 |
|
|
__cmpxchg_u32(volatile int *m, int old, int new)
|
| 308 |
|
|
{
|
| 309 |
|
|
__asm__ __volatile__("cas [%2], %3, %0\n\t"
|
| 310 |
|
|
"membar #StoreLoad | #StoreStore"
|
| 311 |
|
|
: "=&r" (new)
|
| 312 |
|
|
: "0" (new), "r" (m), "r" (old)
|
| 313 |
|
|
: "memory");
|
| 314 |
|
|
|
| 315 |
|
|
return new;
|
| 316 |
|
|
}
|
| 317 |
|
|
|
| 318 |
|
|
extern __inline__ unsigned long
|
| 319 |
|
|
__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
|
| 320 |
|
|
{
|
| 321 |
|
|
__asm__ __volatile__("casx [%2], %3, %0\n\t"
|
| 322 |
|
|
"membar #StoreLoad | #StoreStore"
|
| 323 |
|
|
: "=&r" (new)
|
| 324 |
|
|
: "0" (new), "r" (m), "r" (old)
|
| 325 |
|
|
: "memory");
|
| 326 |
|
|
|
| 327 |
|
|
return new;
|
| 328 |
|
|
}
|
| 329 |
|
|
|
| 330 |
|
|
/* This function doesn't exist, so you'll get a linker error
|
| 331 |
|
|
if something tries to do an invalid cmpxchg(). */
|
| 332 |
|
|
extern void __cmpxchg_called_with_bad_pointer(void);
|
| 333 |
|
|
|
| 334 |
|
|
static __inline__ unsigned long
|
| 335 |
|
|
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
|
| 336 |
|
|
{
|
| 337 |
|
|
switch (size) {
|
| 338 |
|
|
case 4:
|
| 339 |
|
|
return __cmpxchg_u32(ptr, old, new);
|
| 340 |
|
|
case 8:
|
| 341 |
|
|
return __cmpxchg_u64(ptr, old, new);
|
| 342 |
|
|
}
|
| 343 |
|
|
__cmpxchg_called_with_bad_pointer();
|
| 344 |
|
|
return old;
|
| 345 |
|
|
}
|
| 346 |
|
|
|
| 347 |
|
|
#define cmpxchg(ptr,o,n) \
|
| 348 |
|
|
({ \
|
| 349 |
|
|
__typeof__(*(ptr)) _o_ = (o); \
|
| 350 |
|
|
__typeof__(*(ptr)) _n_ = (n); \
|
| 351 |
|
|
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
|
| 352 |
|
|
(unsigned long)_n_, sizeof(*(ptr))); \
|
| 353 |
|
|
})
|
| 354 |
|
|
|
| 355 |
|
|
#endif /* !(__ASSEMBLY__) */
|
| 356 |
|
|
|
| 357 |
|
|
#endif /* !(__SPARC64_SYSTEM_H) */
|
