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1275 |
phoenix |
#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#ifdef __KERNEL__
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#ifdef CONFIG_SMP
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#define LOCK_PREFIX "lock ; "
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#else
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#define LOCK_PREFIX ""
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#endif
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#define prepare_to_switch() do {} while(0)
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#define __STR(x) #x
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#define STR(x) __STR(x)
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#define __PUSH(x) "pushq %%" __STR(x) "\n\t"
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#define __POP(x) "popq %%" __STR(x) "\n\t"
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struct save_context_frame {
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unsigned long rbp;
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unsigned long rbx;
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unsigned long r11;
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unsigned long r10;
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unsigned long r9;
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unsigned long r8;
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unsigned long rcx;
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unsigned long rdx;
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unsigned long r15;
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unsigned long r14;
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unsigned long r13;
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unsigned long r12;
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unsigned long rdi;
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unsigned long rsi;
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};
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/* frame pointer must be last for get_wchan */
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#define SAVE_CONTEXT \
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__PUSH(rsi) __PUSH(rdi) \
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__PUSH(r12) __PUSH(r13) __PUSH(r14) __PUSH(r15) \
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__PUSH(rdx) __PUSH(rcx) __PUSH(r8) __PUSH(r9) __PUSH(r10) __PUSH(r11) \
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__PUSH(rbx) __PUSH(rbp)
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#define RESTORE_CONTEXT \
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__POP(rbp) __POP(rbx) \
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__POP(r11) __POP(r10) __POP(r9) __POP(r8) __POP(rcx) __POP(rdx) \
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__POP(r15) __POP(r14) __POP(r13) __POP(r12) \
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__POP(rdi) __POP(rsi)
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#define switch_to(prev,next,last) do { void *l; \
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asm volatile(SAVE_CONTEXT \
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"movq %%rsp,%0\n\t" /* save RSP */ \
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"movq %3,%%rsp\n\t" /* restore RSP */ \
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"leaq thread_return(%%rip),%%rax\n\t" \
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"movq %%rax,%1\n\t" /* save RIP */ \
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"pushq %4\n\t" /* setup new RIP */ \
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"jmp __switch_to\n\t" \
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".globl thread_return\n" \
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"thread_return:\n\t" \
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RESTORE_CONTEXT \
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:"=m" (prev->thread.rsp),"=m" (prev->thread.rip), "=a" (l) \
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:"m" (next->thread.rsp),"m" (next->thread.rip), \
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"S" (next), "D" (prev) \
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:"memory","cc"); \
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last = l; \
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} while(0)
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extern void load_gs_index(unsigned);
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/*
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* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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*/
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#define loadsegment(seg,value) \
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asm volatile("\n" \
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"1:\t" \
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"movl %0,%%" #seg "\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3:\t" \
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"movl %1,%%" #seg "\n\t" \
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"jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n\t" \
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".align 4\n\t" \
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".quad 1b,3b\n" \
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".previous" \
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: :"r" ((int)(value)), "r" (0))
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#define set_debug(value,register) \
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__asm__("movq %0,%%db" #register \
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: /* no output */ \
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:"r" ((unsigned long) value))
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/*
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* Clear and set 'TS' bit respectively
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*/
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#define clts() __asm__ __volatile__ ("clts")
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#define read_cr0() ({ \
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unsigned long __dummy; \
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__asm__( \
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"movq %%cr0,%0\n\t" \
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:"=r" (__dummy)); \
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__dummy; \
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})
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#define write_cr0(x) \
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__asm__("movq %0,%%cr0": :"r" (x));
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#define read_cr4() ({ \
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unsigned long __dummy; \
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__asm__( \
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"movq %%cr4,%0\n\t" \
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:"=r" (__dummy)); \
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__dummy; \
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})
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#define write_cr4(x) \
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__asm__("movq %0,%%cr4": :"r" (x));
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#define stts() write_cr0(8 | read_cr0())
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#define wbinvd() \
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__asm__ __volatile__ ("wbinvd": : :"memory");
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#endif /* __KERNEL__ */
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#define nop() __asm__ __volatile__ ("nop")
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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#define __xg(x) ((volatile long *)(x))
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extern inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
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{
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*ptr = val;
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}
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#define _set_64bit set_64bit
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %k0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 8:
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__asm__ __volatile__("xchgq %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 8:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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#define cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*
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* For now, "wmb()" doesn't actually do anything, as all
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* Intel CPU's follow what Intel calls a *Processor Order*,
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* in which all writes are seen in the program order even
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* outside the CPU.
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*
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* I expect future Intel CPU's to have a weaker ordering,
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* but I'd also expect them to finally get their act together
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* and add some real memory barriers if so.
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*/
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence":::"memory")
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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| 256 |
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#define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
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| 259 |
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/* interrupt control.. */
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#define __save_flags(x) do { warn_if_not_ulong(x); __asm__ __volatile__("# save_flags \n\t pushfq ; popq %q0":"=g" (x): /* no input */ :"memory"); } while (0)
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#define __restore_flags(x) __asm__ __volatile__("# restore_flags \n\t pushq %0 ; popfq": /* no output */ :"g" (x):"memory", "cc")
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| 262 |
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#define __cli() __asm__ __volatile__("cli": : :"memory")
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| 263 |
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#define __sti() __asm__ __volatile__("sti": : :"memory")
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| 264 |
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/* used in the idle loop; sti takes one instruction cycle to complete */
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#define safe_halt() __asm__ __volatile__("sti; hlt": : :"memory")
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| 267 |
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#define __save_and_cli(x) do { __save_flags(x); __cli(); } while(0)
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| 268 |
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#define __save_and_sti(x) do { __save_flags(x); __sti(); } while(0)
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| 269 |
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| 270 |
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/* For spinlocks etc */
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#define local_irq_save(x) do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_save \n\t pushfq ; popq %0 ; cli":"=g" (x): /* no input */ :"memory"); } while (0)
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#define local_irq_set(x) do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_set \n\t pushfq ; popq %0 ; sti":"=g" (x): /* no input */ :"memory"); } while (0)
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| 273 |
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#define local_irq_restore(x) __asm__ __volatile__("# local_irq_restore \n\t pushq %0 ; popfq": /* no output */ :"g" (x):"memory")
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| 274 |
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#define local_irq_disable() __cli()
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| 275 |
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#define local_irq_enable() __sti()
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| 276 |
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| 277 |
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#ifdef CONFIG_SMP
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| 278 |
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| 279 |
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extern void __global_cli(void);
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| 280 |
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extern void __global_sti(void);
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| 281 |
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extern unsigned long __global_save_flags(void);
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| 282 |
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extern void __global_restore_flags(unsigned long);
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| 283 |
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#define cli() __global_cli()
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| 284 |
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#define sti() __global_sti()
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| 285 |
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#define save_flags(x) ((x)=__global_save_flags())
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| 286 |
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#define restore_flags(x) __global_restore_flags(x)
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| 287 |
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#define save_and_cli(x) do { save_flags(x); cli(); } while(0)
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| 288 |
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#define save_and_sti(x) do { save_flags(x); sti(); } while(0)
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| 289 |
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| 290 |
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#else
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| 291 |
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| 292 |
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#define cli() __cli()
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| 293 |
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#define sti() __sti()
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| 294 |
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#define save_flags(x) __save_flags(x)
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| 295 |
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#define restore_flags(x) __restore_flags(x)
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| 296 |
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#define save_and_cli(x) __save_and_cli(x)
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| 297 |
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#define save_and_sti(x) __save_and_sti(x)
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| 298 |
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| 299 |
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#endif
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| 300 |
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| 301 |
|
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/* Default simics "magic" breakpoint */
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| 302 |
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#define icebp() asm volatile("xchg %%bx,%%bx" ::: "ebx")
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| 303 |
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|
| 304 |
|
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/*
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| 305 |
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* disable hlt during certain critical i/o operations
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| 306 |
|
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*/
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| 307 |
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#define HAVE_DISABLE_HLT
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| 308 |
|
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void disable_hlt(void);
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| 309 |
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void enable_hlt(void);
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| 310 |
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| 311 |
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#endif
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