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1181 |
sfurman |
/* Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* Logically, this code should be part of libopcode but since some of
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the operand insertion/extraction functions help bfd to implement
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relocations, this code is included as part of cpu-ia64.c. This
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avoids circular dependencies between libopcode and libbfd and also
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obviates the need for applications to link in libopcode when all
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they really want is libbfd.
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--davidm Mon Apr 13 22:14:02 1998 */
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#include "../opcodes/ia64-opc.h"
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#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
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static const char*
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ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
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ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
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{
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return "internal error---this shouldn't happen";
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}
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static const char*
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ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
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ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
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{
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return "internal error---this shouldn't happen";
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}
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static const char*
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ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
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ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
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{
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return 0;
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}
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static const char*
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ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
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ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
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{
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return 0;
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}
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static const char*
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ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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if (value >= 1u << self->field[0].bits)
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return "register number out of range";
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*code |= value << self->field[0].shift;
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return 0;
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}
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static const char*
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ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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*valuep = ((code >> self->field[0].shift)
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& ((1u << self->field[0].bits) - 1));
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return 0;
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}
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static const char*
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ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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ia64_insn new = 0;
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int i;
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for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
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{
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new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
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<< self->field[i].shift);
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value >>= self->field[i].bits;
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}
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if (value)
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return "integer operand out of range";
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*code |= new;
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return 0;
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}
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static const char*
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ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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BFD_HOST_U_64_BIT value = 0;
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int i, bits = 0, total = 0;
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for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
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{
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bits = self->field[i].bits;
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value |= ((code >> self->field[i].shift)
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& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
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total += bits;
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}
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*valuep = value;
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return 0;
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}
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static const char*
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ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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if (value & 0x7)
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return "value not an integer multiple of 8";
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return ins_immu (self, value >> 3, code);
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}
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static const char*
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ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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const char *result;
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result = ext_immu (self, code, valuep);
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if (result)
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return result;
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*valuep = *valuep << 3;
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return 0;
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}
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static const char*
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ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
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ia64_insn *code, int scale)
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{
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BFD_HOST_64_BIT svalue = value, sign_bit = 0;
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ia64_insn new = 0;
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int i;
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svalue >>= scale;
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for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
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{
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new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
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<< self->field[i].shift);
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sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
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svalue >>= self->field[i].bits;
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}
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if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
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return "integer operand out of range";
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*code |= new;
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return 0;
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}
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static const char*
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ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
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ia64_insn *valuep, int scale)
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{
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int i, bits = 0, total = 0, shift;
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BFD_HOST_64_BIT val = 0;
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for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
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{
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bits = self->field[i].bits;
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val |= ((code >> self->field[i].shift)
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& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
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total += bits;
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}
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/* sign extend: */
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shift = 8*sizeof (val) - total;
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val = (val << shift) >> shift;
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*valuep = (val << scale);
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return 0;
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}
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static const char*
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ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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return ins_imms_scaled (self, value, code, 0);
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}
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static const char*
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ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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if (value == (BFD_HOST_U_64_BIT) 0x100000000)
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value = 0;
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else
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value = (((BFD_HOST_64_BIT)value << 32) >> 32);
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return ins_imms_scaled (self, value, code, 0);
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}
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static const char*
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ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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return ext_imms_scaled (self, code, valuep, 0);
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}
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static const char*
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ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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--value;
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return ins_imms_scaled (self, value, code, 0);
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}
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static const char*
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ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
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ia64_insn *code)
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{
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if (value == (BFD_HOST_U_64_BIT) 0x100000000)
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value = 0;
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else
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value = (((BFD_HOST_64_BIT)value << 32) >> 32);
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--value;
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return ins_imms_scaled (self, value, code, 0);
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}
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static const char*
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ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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const char *res = ext_imms_scaled (self, code, valuep, 0);
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++*valuep;
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return res;
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}
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static const char*
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ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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return ins_imms_scaled (self, value, code, 1);
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}
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240 |
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static const char*
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ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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return ext_imms_scaled (self, code, valuep, 1);
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}
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246 |
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static const char*
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ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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249 |
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return ins_imms_scaled (self, value, code, 4);
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}
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252 |
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static const char*
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ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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return ext_imms_scaled (self, code, valuep, 4);
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}
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257 |
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258 |
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static const char*
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ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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return ins_imms_scaled (self, value, code, 16);
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}
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263 |
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264 |
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static const char*
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ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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return ext_imms_scaled (self, code, valuep, 16);
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268 |
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}
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269 |
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|
270 |
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static const char*
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ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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272 |
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{
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273 |
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ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
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return ins_immu (self, value ^ mask, code);
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275 |
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}
|
276 |
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|
277 |
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static const char*
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278 |
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ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
279 |
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{
|
280 |
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const char *result;
|
281 |
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ia64_insn mask;
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282 |
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|
283 |
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mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
|
284 |
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result = ext_immu (self, code, valuep);
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285 |
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if (!result)
|
286 |
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{
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287 |
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mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
|
288 |
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*valuep ^= mask;
|
289 |
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}
|
290 |
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return result;
|
291 |
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}
|
292 |
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|
293 |
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static const char*
|
294 |
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ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
295 |
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{
|
296 |
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--value;
|
297 |
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if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
|
298 |
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return "count out of range";
|
299 |
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|
300 |
|
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*code |= value << self->field[0].shift;
|
301 |
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return 0;
|
302 |
|
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}
|
303 |
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|
304 |
|
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static const char*
|
305 |
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ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
306 |
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{
|
307 |
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*valuep = ((code >> self->field[0].shift)
|
308 |
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& ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
|
309 |
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return 0;
|
310 |
|
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}
|
311 |
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|
312 |
|
|
static const char*
|
313 |
|
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ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
314 |
|
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{
|
315 |
|
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--value;
|
316 |
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|
317 |
|
|
if (value > 2)
|
318 |
|
|
return "count must be in range 1..3";
|
319 |
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|
320 |
|
|
*code |= value << self->field[0].shift;
|
321 |
|
|
return 0;
|
322 |
|
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}
|
323 |
|
|
|
324 |
|
|
static const char*
|
325 |
|
|
ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
326 |
|
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{
|
327 |
|
|
*valuep = ((code >> self->field[0].shift) & 0x3) + 1;
|
328 |
|
|
return 0;
|
329 |
|
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}
|
330 |
|
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|
331 |
|
|
static const char*
|
332 |
|
|
ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
333 |
|
|
{
|
334 |
|
|
switch (value)
|
335 |
|
|
{
|
336 |
|
|
case 0: value = 0; break;
|
337 |
|
|
case 7: value = 1; break;
|
338 |
|
|
case 15: value = 2; break;
|
339 |
|
|
case 16: value = 3; break;
|
340 |
|
|
default: return "count must be 0, 7, 15, or 16";
|
341 |
|
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}
|
342 |
|
|
*code |= value << self->field[0].shift;
|
343 |
|
|
return 0;
|
344 |
|
|
}
|
345 |
|
|
|
346 |
|
|
static const char*
|
347 |
|
|
ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
348 |
|
|
{
|
349 |
|
|
ia64_insn value;
|
350 |
|
|
|
351 |
|
|
value = (code >> self->field[0].shift) & 0x3;
|
352 |
|
|
switch (value)
|
353 |
|
|
{
|
354 |
|
|
case 0: value = 0; break;
|
355 |
|
|
case 1: value = 7; break;
|
356 |
|
|
case 2: value = 15; break;
|
357 |
|
|
case 3: value = 16; break;
|
358 |
|
|
}
|
359 |
|
|
*valuep = value;
|
360 |
|
|
return 0;
|
361 |
|
|
}
|
362 |
|
|
|
363 |
|
|
static const char*
|
364 |
|
|
ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
|
365 |
|
|
{
|
366 |
|
|
BFD_HOST_64_BIT val = value;
|
367 |
|
|
BFD_HOST_U_64_BIT sign = 0;
|
368 |
|
|
|
369 |
|
|
if (val < 0)
|
370 |
|
|
{
|
371 |
|
|
sign = 0x4;
|
372 |
|
|
value = -value;
|
373 |
|
|
}
|
374 |
|
|
switch (value)
|
375 |
|
|
{
|
376 |
|
|
case 1: value = 3; break;
|
377 |
|
|
case 4: value = 2; break;
|
378 |
|
|
case 8: value = 1; break;
|
379 |
|
|
case 16: value = 0; break;
|
380 |
|
|
default: return "count must be +/- 1, 4, 8, or 16";
|
381 |
|
|
}
|
382 |
|
|
*code |= (sign | value) << self->field[0].shift;
|
383 |
|
|
return 0;
|
384 |
|
|
}
|
385 |
|
|
|
386 |
|
|
static const char*
|
387 |
|
|
ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
|
388 |
|
|
{
|
389 |
|
|
BFD_HOST_64_BIT val;
|
390 |
|
|
int negate;
|
391 |
|
|
|
392 |
|
|
val = (code >> self->field[0].shift) & 0x7;
|
393 |
|
|
negate = val & 0x4;
|
394 |
|
|
switch (val & 0x3)
|
395 |
|
|
{
|
396 |
|
|
case 0: val = 16; break;
|
397 |
|
|
case 1: val = 8; break;
|
398 |
|
|
case 2: val = 4; break;
|
399 |
|
|
case 3: val = 1; break;
|
400 |
|
|
}
|
401 |
|
|
if (negate)
|
402 |
|
|
val = -val;
|
403 |
|
|
|
404 |
|
|
*valuep = val;
|
405 |
|
|
return 0;
|
406 |
|
|
}
|
407 |
|
|
|
408 |
|
|
#define CST IA64_OPND_CLASS_CST
|
409 |
|
|
#define REG IA64_OPND_CLASS_REG
|
410 |
|
|
#define IND IA64_OPND_CLASS_IND
|
411 |
|
|
#define ABS IA64_OPND_CLASS_ABS
|
412 |
|
|
#define REL IA64_OPND_CLASS_REL
|
413 |
|
|
|
414 |
|
|
#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
|
415 |
|
|
#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
|
416 |
|
|
|
417 |
|
|
const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
|
418 |
|
|
{
|
419 |
|
|
/* constants: */
|
420 |
|
|
{ CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
|
421 |
|
|
{ CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
|
422 |
|
|
{ CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
|
423 |
|
|
{ CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
|
424 |
|
|
{ CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
|
425 |
|
|
{ CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
|
426 |
|
|
{ CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
|
427 |
|
|
{ CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
|
428 |
|
|
{ CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
|
429 |
|
|
{ CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
|
430 |
|
|
{ CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
|
431 |
|
|
{ CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
|
432 |
|
|
{ CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
|
433 |
|
|
|
434 |
|
|
/* register operands: */
|
435 |
|
|
{ REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
|
436 |
|
|
"an application register" },
|
437 |
|
|
{ REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
|
438 |
|
|
"a branch register" },
|
439 |
|
|
{ REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
|
440 |
|
|
"a branch register"},
|
441 |
|
|
{ REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
|
442 |
|
|
"a control register"},
|
443 |
|
|
{ REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
|
444 |
|
|
"a floating-point register" },
|
445 |
|
|
{ REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
|
446 |
|
|
"a floating-point register" },
|
447 |
|
|
{ REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
|
448 |
|
|
"a floating-point register" },
|
449 |
|
|
{ REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
|
450 |
|
|
"a floating-point register" },
|
451 |
|
|
{ REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
|
452 |
|
|
"a predicate register" },
|
453 |
|
|
{ REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
|
454 |
|
|
"a predicate register" },
|
455 |
|
|
{ REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
|
456 |
|
|
"a general register" },
|
457 |
|
|
{ REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
|
458 |
|
|
"a general register" },
|
459 |
|
|
{ REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
|
460 |
|
|
"a general register" },
|
461 |
|
|
{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
|
462 |
|
|
"a general register r0-r3" },
|
463 |
|
|
|
464 |
|
|
/* indirect operands: */
|
465 |
|
|
{ IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
|
466 |
|
|
"a cpuid register" },
|
467 |
|
|
{ IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
|
468 |
|
|
"a dbr register" },
|
469 |
|
|
{ IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
|
470 |
|
|
"a dtr register" },
|
471 |
|
|
{ IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
|
472 |
|
|
"an itr register" },
|
473 |
|
|
{ IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
|
474 |
|
|
"an ibr register" },
|
475 |
|
|
{ IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
|
476 |
|
|
"an indirect memory address" },
|
477 |
|
|
{ IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
|
478 |
|
|
"an msr register" },
|
479 |
|
|
{ IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
|
480 |
|
|
"a pkr register" },
|
481 |
|
|
{ IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
|
482 |
|
|
"a pmc register" },
|
483 |
|
|
{ IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
|
484 |
|
|
"a pmd register" },
|
485 |
|
|
{ IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
|
486 |
|
|
"an rr register" },
|
487 |
|
|
|
488 |
|
|
/* immediate operands: */
|
489 |
|
|
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
|
490 |
|
|
"a 5-bit count (0-31)" },
|
491 |
|
|
{ ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
|
492 |
|
|
"a 2-bit count (1-4)" },
|
493 |
|
|
{ ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
|
494 |
|
|
"a 2-bit count (1-3)" },
|
495 |
|
|
{ ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
|
496 |
|
|
"a count (0, 7, 15, or 16)" },
|
497 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
|
498 |
|
|
"a 5-bit count (0-31)" },
|
499 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
|
500 |
|
|
"a 6-bit count (0-63)" },
|
501 |
|
|
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
|
502 |
|
|
"a 6-bit bit pos (0-63)" },
|
503 |
|
|
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
|
504 |
|
|
"a 6-bit bit pos (0-63)" },
|
505 |
|
|
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
|
506 |
|
|
"a 6-bit bit pos (0-63)" },
|
507 |
|
|
{ ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
|
508 |
|
|
"a 1-bit integer (-1, 0)" },
|
509 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
|
510 |
|
|
"a 2-bit unsigned (0-3)" },
|
511 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
|
512 |
|
|
"a 7-bit unsigned (0-127)" },
|
513 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
|
514 |
|
|
"a 7-bit unsigned (0-127)" },
|
515 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
|
516 |
|
|
"a frame size (register count)" },
|
517 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
|
518 |
|
|
"a local register count" },
|
519 |
|
|
{ ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
|
520 |
|
|
"a rotating register count (integer multiple of 8)" },
|
521 |
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM8 */
|
522 |
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
523 |
|
|
"an 8-bit integer (-128-127)" },
|
524 |
|
|
{ ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
|
525 |
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
526 |
|
|
"an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
|
527 |
|
|
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
|
528 |
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
529 |
|
|
"an 8-bit integer (-127-128)" },
|
530 |
|
|
{ ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
|
531 |
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
532 |
|
|
"an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
|
533 |
|
|
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
|
534 |
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
535 |
|
|
"an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
|
536 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
|
537 |
|
|
"a 9-bit unsigned (0-511)" },
|
538 |
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM9a */
|
539 |
|
|
{{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
|
540 |
|
|
"a 9-bit integer (-256-255)" },
|
541 |
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM9b */
|
542 |
|
|
{{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
|
543 |
|
|
"a 9-bit integer (-256-255)" },
|
544 |
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM14 */
|
545 |
|
|
{{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
|
546 |
|
|
"a 14-bit integer (-8192-8191)" },
|
547 |
|
|
{ ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
|
548 |
|
|
{{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
|
549 |
|
|
"a 17-bit integer (-65536-65535)" },
|
550 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
|
551 |
|
|
"a 21-bit unsigned" },
|
552 |
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM22 */
|
553 |
|
|
{{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
|
554 |
|
|
"a 22-bit signed integer" },
|
555 |
|
|
{ ABS, ins_immu, ext_immu, 0, /* IMMU24 */
|
556 |
|
|
{{21, 6}, { 2, 31}, { 1, 36}}, 0,
|
557 |
|
|
"a 24-bit unsigned" },
|
558 |
|
|
{ ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
|
559 |
|
|
"a 44-bit unsigned (least 16 bits ignored/zeroes)" },
|
560 |
|
|
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
|
561 |
|
|
"a 62-bit unsigned" },
|
562 |
|
|
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
|
563 |
|
|
"a 64-bit unsigned" },
|
564 |
|
|
{ ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
|
565 |
|
|
"an increment (+/- 1, 4, 8, or 16)" },
|
566 |
|
|
{ ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
|
567 |
|
|
"a 4-bit length (1-16)" },
|
568 |
|
|
{ ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
|
569 |
|
|
"a 6-bit length (1-64)" },
|
570 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
|
571 |
|
|
"a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
|
572 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
|
573 |
|
|
"an 8-bit mix type" },
|
574 |
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
|
575 |
|
|
"a 6-bit bit pos (0-63)" },
|
576 |
|
|
{ REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
|
577 |
|
|
"a branch tag" },
|
578 |
|
|
{ REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
|
579 |
|
|
"a branch tag" },
|
580 |
|
|
{ REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
|
581 |
|
|
"a branch target" },
|
582 |
|
|
{ REL, ins_imms4, ext_imms4, 0, /* TGT25b */
|
583 |
|
|
{{ 7, 6}, {13, 20}, { 1, 36}}, 0,
|
584 |
|
|
"a branch target" },
|
585 |
|
|
{ REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
|
586 |
|
|
"a branch target" },
|
587 |
|
|
{ REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
|
588 |
|
|
"a branch target" },
|
589 |
|
|
};
|