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1181 |
sfurman |
// OBSOLETE /* fr30 simulator support code
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// OBSOLETE Copyright (C) 1998, 1999 Free Software Foundation, Inc.
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// OBSOLETE Contributed by Cygnus Solutions.
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// OBSOLETE
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// OBSOLETE This file is part of the GNU simulators.
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// OBSOLETE
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// OBSOLETE This program is free software; you can redistribute it and/or modify
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// OBSOLETE it under the terms of the GNU General Public License as published by
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// OBSOLETE the Free Software Foundation; either version 2, or (at your option)
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// OBSOLETE any later version.
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// OBSOLETE
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// OBSOLETE This program is distributed in the hope that it will be useful,
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// OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of
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// OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// OBSOLETE GNU General Public License for more details.
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// OBSOLETE
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// OBSOLETE You should have received a copy of the GNU General Public License along
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// OBSOLETE with this program; if not, write to the Free Software Foundation, Inc.,
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// OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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// OBSOLETE
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// OBSOLETE #define WANT_CPU
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// OBSOLETE #define WANT_CPU_FR30BF
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// OBSOLETE
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// OBSOLETE #include "sim-main.h"
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// OBSOLETE #include "cgen-mem.h"
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// OBSOLETE #include "cgen-ops.h"
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// OBSOLETE
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// OBSOLETE /* Convert gdb dedicated register number to actual dr reg number. */
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// OBSOLETE
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// OBSOLETE static int
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// OBSOLETE decode_gdb_dr_regnum (int gdb_regnum)
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// OBSOLETE {
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// OBSOLETE switch (gdb_regnum)
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// OBSOLETE {
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// OBSOLETE case TBR_REGNUM : return H_DR_TBR;
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// OBSOLETE case RP_REGNUM : return H_DR_RP;
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// OBSOLETE case SSP_REGNUM : return H_DR_SSP;
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// OBSOLETE case USP_REGNUM : return H_DR_USP;
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// OBSOLETE case MDH_REGNUM : return H_DR_MDH;
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// OBSOLETE case MDL_REGNUM : return H_DR_MDL;
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// OBSOLETE }
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// OBSOLETE abort ();
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* The contents of BUF are in target byte order. */
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// OBSOLETE
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// OBSOLETE int
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// OBSOLETE fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
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// OBSOLETE {
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// OBSOLETE if (rn < 16)
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// OBSOLETE SETTWI (buf, fr30bf_h_gr_get (current_cpu, rn));
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// OBSOLETE else
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// OBSOLETE switch (rn)
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// OBSOLETE {
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// OBSOLETE case PC_REGNUM :
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// OBSOLETE SETTWI (buf, fr30bf_h_pc_get (current_cpu));
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// OBSOLETE break;
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// OBSOLETE case PS_REGNUM :
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// OBSOLETE SETTWI (buf, fr30bf_h_ps_get (current_cpu));
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// OBSOLETE break;
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// OBSOLETE case TBR_REGNUM :
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// OBSOLETE case RP_REGNUM :
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// OBSOLETE case SSP_REGNUM :
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// OBSOLETE case USP_REGNUM :
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// OBSOLETE case MDH_REGNUM :
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// OBSOLETE case MDL_REGNUM :
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// OBSOLETE SETTWI (buf, fr30bf_h_dr_get (current_cpu,
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// OBSOLETE decode_gdb_dr_regnum (rn)));
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// OBSOLETE break;
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// OBSOLETE default :
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// OBSOLETE return 0;
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE return -1; /*FIXME*/
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* The contents of BUF are in target byte order. */
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// OBSOLETE
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// OBSOLETE int
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// OBSOLETE fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
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// OBSOLETE {
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// OBSOLETE if (rn < 16)
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// OBSOLETE fr30bf_h_gr_set (current_cpu, rn, GETTWI (buf));
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// OBSOLETE else
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// OBSOLETE switch (rn)
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// OBSOLETE {
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// OBSOLETE case PC_REGNUM :
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// OBSOLETE fr30bf_h_pc_set (current_cpu, GETTWI (buf));
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// OBSOLETE break;
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// OBSOLETE case PS_REGNUM :
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// OBSOLETE fr30bf_h_ps_set (current_cpu, GETTWI (buf));
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// OBSOLETE break;
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// OBSOLETE case TBR_REGNUM :
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// OBSOLETE case RP_REGNUM :
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// OBSOLETE case SSP_REGNUM :
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// OBSOLETE case USP_REGNUM :
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// OBSOLETE case MDH_REGNUM :
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// OBSOLETE case MDL_REGNUM :
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// OBSOLETE fr30bf_h_dr_set (current_cpu,
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// OBSOLETE decode_gdb_dr_regnum (rn),
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// OBSOLETE GETTWI (buf));
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// OBSOLETE break;
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// OBSOLETE default :
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// OBSOLETE return 0;
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE return -1; /*FIXME*/
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* Cover fns to access the ccr bits. */
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// OBSOLETE
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// OBSOLETE BI
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// OBSOLETE fr30bf_h_sbit_get_handler (SIM_CPU *current_cpu)
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// OBSOLETE {
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// OBSOLETE return CPU (h_sbit);
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE void
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// OBSOLETE fr30bf_h_sbit_set_handler (SIM_CPU *current_cpu, BI newval)
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// OBSOLETE {
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// OBSOLETE int old_sbit = CPU (h_sbit);
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// OBSOLETE int new_sbit = (newval != 0);
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// OBSOLETE
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// OBSOLETE CPU (h_sbit) = new_sbit;
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// OBSOLETE
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// OBSOLETE /* When switching stack modes, update the registers. */
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// OBSOLETE if (old_sbit != new_sbit)
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// OBSOLETE {
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// OBSOLETE if (old_sbit)
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// OBSOLETE {
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// OBSOLETE /* Switching user -> system. */
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// OBSOLETE CPU (h_dr[H_DR_USP]) = CPU (h_gr[H_GR_SP]);
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// OBSOLETE CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_SSP]);
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// OBSOLETE }
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// OBSOLETE else
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// OBSOLETE {
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// OBSOLETE /* Switching system -> user. */
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// OBSOLETE CPU (h_dr[H_DR_SSP]) = CPU (h_gr[H_GR_SP]);
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// OBSOLETE CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_USP]);
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// OBSOLETE }
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* TODO: r15 interlock */
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* Cover fns to access the ccr bits. */
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// OBSOLETE
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// OBSOLETE UQI
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// OBSOLETE fr30bf_h_ccr_get_handler (SIM_CPU *current_cpu)
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// OBSOLETE {
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// OBSOLETE int ccr = ( (GET_H_CBIT () << 0)
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// OBSOLETE | (GET_H_VBIT () << 1)
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// OBSOLETE | (GET_H_ZBIT () << 2)
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// OBSOLETE | (GET_H_NBIT () << 3)
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// OBSOLETE | (GET_H_IBIT () << 4)
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// OBSOLETE | (GET_H_SBIT () << 5));
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// OBSOLETE
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// OBSOLETE return ccr;
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE void
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// OBSOLETE fr30bf_h_ccr_set_handler (SIM_CPU *current_cpu, UQI newval)
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// OBSOLETE {
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// OBSOLETE int ccr = newval & 0x3f;
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// OBSOLETE
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// OBSOLETE SET_H_CBIT ((ccr & 1) != 0);
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// OBSOLETE SET_H_VBIT ((ccr & 2) != 0);
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// OBSOLETE SET_H_ZBIT ((ccr & 4) != 0);
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// OBSOLETE SET_H_NBIT ((ccr & 8) != 0);
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// OBSOLETE SET_H_IBIT ((ccr & 0x10) != 0);
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// OBSOLETE SET_H_SBIT ((ccr & 0x20) != 0);
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* Cover fns to access the scr bits. */
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// OBSOLETE
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// OBSOLETE UQI
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// OBSOLETE fr30bf_h_scr_get_handler (SIM_CPU *current_cpu)
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// OBSOLETE {
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// OBSOLETE int scr = ( (GET_H_TBIT () << 0)
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// OBSOLETE | (GET_H_D0BIT () << 1)
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// OBSOLETE | (GET_H_D1BIT () << 2));
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// OBSOLETE return scr;
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE void
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// OBSOLETE fr30bf_h_scr_set_handler (SIM_CPU *current_cpu, UQI newval)
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// OBSOLETE {
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// OBSOLETE int scr = newval & 7;
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// OBSOLETE
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// OBSOLETE SET_H_TBIT ((scr & 1) != 0);
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// OBSOLETE SET_H_D0BIT ((scr & 2) != 0);
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// OBSOLETE SET_H_D1BIT ((scr & 4) != 0);
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* Cover fns to access the ilm bits. */
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// OBSOLETE
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// OBSOLETE UQI
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// OBSOLETE fr30bf_h_ilm_get_handler (SIM_CPU *current_cpu)
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// OBSOLETE {
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// OBSOLETE return CPU (h_ilm);
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE void
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// OBSOLETE fr30bf_h_ilm_set_handler (SIM_CPU *current_cpu, UQI newval)
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// OBSOLETE {
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// OBSOLETE int ilm = newval & 0x1f;
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// OBSOLETE int current_ilm = CPU (h_ilm);
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// OBSOLETE
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// OBSOLETE /* We can only set new ilm values < 16 if the current ilm is < 16. Otherwise
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// OBSOLETE we add 16 to the value we are given. */
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// OBSOLETE if (current_ilm >= 16 && ilm < 16)
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// OBSOLETE ilm += 16;
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// OBSOLETE
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// OBSOLETE CPU (h_ilm) = ilm;
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* Cover fns to access the ps register. */
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// OBSOLETE
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// OBSOLETE USI
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// OBSOLETE fr30bf_h_ps_get_handler (SIM_CPU *current_cpu)
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// OBSOLETE {
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// OBSOLETE int ccr = GET_H_CCR ();
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// OBSOLETE int scr = GET_H_SCR ();
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// OBSOLETE int ilm = GET_H_ILM ();
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// OBSOLETE
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// OBSOLETE return ccr | (scr << 8) | (ilm << 16);
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE void
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// OBSOLETE fr30bf_h_ps_set_handler (SIM_CPU *current_cpu, USI newval)
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// OBSOLETE {
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// OBSOLETE int ccr = newval & 0xff;
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// OBSOLETE int scr = (newval >> 8) & 7;
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// OBSOLETE int ilm = (newval >> 16) & 0x1f;
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// OBSOLETE
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// OBSOLETE SET_H_CCR (ccr);
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// OBSOLETE SET_H_SCR (scr);
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// OBSOLETE SET_H_ILM (ilm);
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE /* Cover fns to access the dedicated registers. */
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// OBSOLETE
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// OBSOLETE SI
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// OBSOLETE fr30bf_h_dr_get_handler (SIM_CPU *current_cpu, UINT dr)
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// OBSOLETE {
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// OBSOLETE switch (dr)
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// OBSOLETE {
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// OBSOLETE case H_DR_SSP :
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// OBSOLETE if (! GET_H_SBIT ())
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// OBSOLETE return GET_H_GR (H_GR_SP);
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// OBSOLETE else
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// OBSOLETE return CPU (h_dr[H_DR_SSP]);
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// OBSOLETE case H_DR_USP :
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// OBSOLETE if (GET_H_SBIT ())
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// OBSOLETE return GET_H_GR (H_GR_SP);
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// OBSOLETE else
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// OBSOLETE return CPU (h_dr[H_DR_USP]);
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// OBSOLETE case H_DR_TBR :
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// OBSOLETE case H_DR_RP :
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// OBSOLETE case H_DR_MDH :
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// OBSOLETE case H_DR_MDL :
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// OBSOLETE return CPU (h_dr[dr]);
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// OBSOLETE }
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// OBSOLETE return 0;
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE void
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// OBSOLETE fr30bf_h_dr_set_handler (SIM_CPU *current_cpu, UINT dr, SI newval)
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// OBSOLETE {
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// OBSOLETE switch (dr)
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// OBSOLETE {
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// OBSOLETE case H_DR_SSP :
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// OBSOLETE if (! GET_H_SBIT ())
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// OBSOLETE SET_H_GR (H_GR_SP, newval);
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// OBSOLETE else
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// OBSOLETE CPU (h_dr[H_DR_SSP]) = newval;
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// OBSOLETE break;
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// OBSOLETE case H_DR_USP :
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// OBSOLETE if (GET_H_SBIT ())
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// OBSOLETE SET_H_GR (H_GR_SP, newval);
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// OBSOLETE else
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// OBSOLETE CPU (h_dr[H_DR_USP]) = newval;
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// OBSOLETE break;
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// OBSOLETE case H_DR_TBR :
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// OBSOLETE case H_DR_RP :
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// OBSOLETE case H_DR_MDH :
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// OBSOLETE case H_DR_MDL :
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// OBSOLETE CPU (h_dr[dr]) = newval;
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// OBSOLETE break;
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// OBSOLETE }
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// OBSOLETE }
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// OBSOLETE
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// OBSOLETE #if WITH_PROFILE_MODEL_P
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// OBSOLETE
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// OBSOLETE /* FIXME: Some of these should be inline or macros. Later. */
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// OBSOLETE
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297 |
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// OBSOLETE /* Initialize cycle counting for an insn.
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298 |
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// OBSOLETE FIRST_P is non-zero if this is the first insn in a set of parallel
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299 |
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// OBSOLETE insns. */
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300 |
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// OBSOLETE
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301 |
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// OBSOLETE void
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302 |
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// OBSOLETE fr30bf_model_insn_before (SIM_CPU *cpu, int first_p)
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303 |
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// OBSOLETE {
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304 |
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// OBSOLETE MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
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305 |
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// OBSOLETE d->load_regs_pending = 0;
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306 |
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// OBSOLETE }
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307 |
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// OBSOLETE
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308 |
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// OBSOLETE /* Record the cycles computed for an insn.
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309 |
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// OBSOLETE LAST_P is non-zero if this is the last insn in a set of parallel insns,
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310 |
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// OBSOLETE and we update the total cycle count.
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311 |
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// OBSOLETE CYCLES is the cycle count of the insn. */
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312 |
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// OBSOLETE
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313 |
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// OBSOLETE void
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314 |
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// OBSOLETE fr30bf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
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315 |
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// OBSOLETE {
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316 |
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// OBSOLETE PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
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317 |
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// OBSOLETE MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
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318 |
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// OBSOLETE
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319 |
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// OBSOLETE PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
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320 |
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// OBSOLETE PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
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321 |
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// OBSOLETE d->load_regs = d->load_regs_pending;
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322 |
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// OBSOLETE }
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323 |
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// OBSOLETE
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324 |
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// OBSOLETE static INLINE int
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325 |
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// OBSOLETE check_load_stall (SIM_CPU *cpu, int regno)
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326 |
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// OBSOLETE {
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327 |
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// OBSOLETE const MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
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328 |
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// OBSOLETE UINT load_regs = d->load_regs;
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329 |
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// OBSOLETE
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330 |
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// OBSOLETE if (regno != -1
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331 |
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// OBSOLETE && (load_regs & (1 << regno)) != 0)
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332 |
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// OBSOLETE {
|
333 |
|
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// OBSOLETE PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
|
334 |
|
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// OBSOLETE ++ PROFILE_MODEL_LOAD_STALL_CYCLES (p);
|
335 |
|
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// OBSOLETE if (TRACE_INSN_P (cpu))
|
336 |
|
|
// OBSOLETE cgen_trace_printf (cpu, " ; Load stall.");
|
337 |
|
|
// OBSOLETE return 1;
|
338 |
|
|
// OBSOLETE }
|
339 |
|
|
// OBSOLETE else
|
340 |
|
|
// OBSOLETE return 0;
|
341 |
|
|
// OBSOLETE }
|
342 |
|
|
// OBSOLETE
|
343 |
|
|
// OBSOLETE int
|
344 |
|
|
// OBSOLETE fr30bf_model_fr30_1_u_exec (SIM_CPU *cpu, const IDESC *idesc,
|
345 |
|
|
// OBSOLETE int unit_num, int referenced,
|
346 |
|
|
// OBSOLETE INT in_Ri, INT in_Rj, INT out_Ri)
|
347 |
|
|
// OBSOLETE {
|
348 |
|
|
// OBSOLETE int cycles = idesc->timing->units[unit_num].done;
|
349 |
|
|
// OBSOLETE cycles += check_load_stall (cpu, in_Ri);
|
350 |
|
|
// OBSOLETE cycles += check_load_stall (cpu, in_Rj);
|
351 |
|
|
// OBSOLETE return cycles;
|
352 |
|
|
// OBSOLETE }
|
353 |
|
|
// OBSOLETE
|
354 |
|
|
// OBSOLETE int
|
355 |
|
|
// OBSOLETE fr30bf_model_fr30_1_u_cti (SIM_CPU *cpu, const IDESC *idesc,
|
356 |
|
|
// OBSOLETE int unit_num, int referenced,
|
357 |
|
|
// OBSOLETE INT in_Ri)
|
358 |
|
|
// OBSOLETE {
|
359 |
|
|
// OBSOLETE PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
|
360 |
|
|
// OBSOLETE /* (1 << 1): The pc is the 2nd element in inputs, outputs.
|
361 |
|
|
// OBSOLETE ??? can be cleaned up */
|
362 |
|
|
// OBSOLETE int taken_p = (referenced & (1 << 1)) != 0;
|
363 |
|
|
// OBSOLETE int cycles = idesc->timing->units[unit_num].done;
|
364 |
|
|
// OBSOLETE int delay_slot_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT);
|
365 |
|
|
// OBSOLETE
|
366 |
|
|
// OBSOLETE cycles += check_load_stall (cpu, in_Ri);
|
367 |
|
|
// OBSOLETE if (taken_p)
|
368 |
|
|
// OBSOLETE {
|
369 |
|
|
// OBSOLETE /* ??? Handling cti's without delay slots this way will run afoul of
|
370 |
|
|
// OBSOLETE accurate system simulation. Later. */
|
371 |
|
|
// OBSOLETE if (! delay_slot_p)
|
372 |
|
|
// OBSOLETE {
|
373 |
|
|
// OBSOLETE ++cycles;
|
374 |
|
|
// OBSOLETE ++PROFILE_MODEL_CTI_STALL_CYCLES (p);
|
375 |
|
|
// OBSOLETE }
|
376 |
|
|
// OBSOLETE ++PROFILE_MODEL_TAKEN_COUNT (p);
|
377 |
|
|
// OBSOLETE }
|
378 |
|
|
// OBSOLETE else
|
379 |
|
|
// OBSOLETE ++PROFILE_MODEL_UNTAKEN_COUNT (p);
|
380 |
|
|
// OBSOLETE
|
381 |
|
|
// OBSOLETE return cycles;
|
382 |
|
|
// OBSOLETE }
|
383 |
|
|
// OBSOLETE
|
384 |
|
|
// OBSOLETE int
|
385 |
|
|
// OBSOLETE fr30bf_model_fr30_1_u_load (SIM_CPU *cpu, const IDESC *idesc,
|
386 |
|
|
// OBSOLETE int unit_num, int referenced,
|
387 |
|
|
// OBSOLETE INT in_Rj, INT out_Ri)
|
388 |
|
|
// OBSOLETE {
|
389 |
|
|
// OBSOLETE MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
|
390 |
|
|
// OBSOLETE int cycles = idesc->timing->units[unit_num].done;
|
391 |
|
|
// OBSOLETE d->load_regs_pending |= 1 << out_Ri;
|
392 |
|
|
// OBSOLETE cycles += check_load_stall (cpu, in_Rj);
|
393 |
|
|
// OBSOLETE return cycles;
|
394 |
|
|
// OBSOLETE }
|
395 |
|
|
// OBSOLETE
|
396 |
|
|
// OBSOLETE int
|
397 |
|
|
// OBSOLETE fr30bf_model_fr30_1_u_store (SIM_CPU *cpu, const IDESC *idesc,
|
398 |
|
|
// OBSOLETE int unit_num, int referenced,
|
399 |
|
|
// OBSOLETE INT in_Ri, INT in_Rj)
|
400 |
|
|
// OBSOLETE {
|
401 |
|
|
// OBSOLETE int cycles = idesc->timing->units[unit_num].done;
|
402 |
|
|
// OBSOLETE cycles += check_load_stall (cpu, in_Ri);
|
403 |
|
|
// OBSOLETE cycles += check_load_stall (cpu, in_Rj);
|
404 |
|
|
// OBSOLETE return cycles;
|
405 |
|
|
// OBSOLETE }
|
406 |
|
|
// OBSOLETE
|
407 |
|
|
// OBSOLETE int
|
408 |
|
|
// OBSOLETE fr30bf_model_fr30_1_u_ldm (SIM_CPU *cpu, const IDESC *idesc,
|
409 |
|
|
// OBSOLETE int unit_num, int referenced,
|
410 |
|
|
// OBSOLETE INT reglist)
|
411 |
|
|
// OBSOLETE {
|
412 |
|
|
// OBSOLETE return idesc->timing->units[unit_num].done;
|
413 |
|
|
// OBSOLETE }
|
414 |
|
|
// OBSOLETE
|
415 |
|
|
// OBSOLETE int
|
416 |
|
|
// OBSOLETE fr30bf_model_fr30_1_u_stm (SIM_CPU *cpu, const IDESC *idesc,
|
417 |
|
|
// OBSOLETE int unit_num, int referenced,
|
418 |
|
|
// OBSOLETE INT reglist)
|
419 |
|
|
// OBSOLETE {
|
420 |
|
|
// OBSOLETE return idesc->timing->units[unit_num].done;
|
421 |
|
|
// OBSOLETE }
|
422 |
|
|
// OBSOLETE
|
423 |
|
|
// OBSOLETE #endif /* WITH_PROFILE_MODEL_P */
|