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        # Test macro
 
        .macro assert reg,value
        cmpeq f0,\reg,\value
        bra/fx fail
        .endm
 
 
        # PR 14580 - a.s
 
        add  r8,r0,0x11112222
        add  r9,r0,-32
        sra r1,r8,r9            ||nop
        sra r2,r8,-32           ||nop
        srl r3,r8,r9            ||nop
        srl r4,r8,-32           ||nop
 
        assert r1, 0
        assert r2, 0
        assert r3, 0
        assert r4, 0
 
 
        # PR 17266 - a.s
 
        add r20, r0, 0xffffffff
        add r21, r0, 0xffffffff
        add r22, r0, 0xffffffff
        add r23, r0, 0xffffffff
        add r1, r0, 0x12345678
        add r2, r0, -33
        srahh r20, r1, r2
        srahl r21, r1, r2
        srlhh r22, r1, r2
        srlhl r23, r1, r2
        sra r24, r1, r2
        srl r25, r1, r2
        rot r26, r1, r2
 
        assert r20, 0xacf0ffff
        assert r21, 0xffffacf0
        assert r22, 0xacf0ffff
        assert r23, 0xffffacf0
        assert r24, 0x2468acf0
        assert r25, 0x2468acf0
        assert r26, 0x2468acf0
 
 
        # PR 17266 - a2.s
 
        add r20, r0, 0xffffffff
        add r21, r0, 0xffffffff
        add r22, r0, 0xffffffff
        add r23, r0, 0xffffffff
        add r1, r0, 0x12345678
        add r2, r0, -17
        sra2h r20, r1, r2
        srl2h r21, r1, r2
        rot2h r22, r1, r2
 
        assert r20, 0x2468acf0
        assert r21, 0x2468acf0
        assert r22, 0x2468acf0
 
 
        # PR 17685 - a.s
 
        add r20,r0,r0
        add r21,r0,r0
        add r22,r0,r0
        add r23,r0,r0
        add r24,r0,r0
        add r25,r0,r0
        add r30,r0,r0
        add r31,r0,r0
 
        add  r8,r0,0x55555555
        add  r9,r0,0x1f
        sra r20,r8,r9 ||nop
        srl r21,r8,r9 ||nop
        srahh r22,r8,r9 ||nop
        srahl r23,r8,r9 ||nop
        srlhh r24,r8,r9 ||nop
        srlhl r25,r8,r9 ||nop
 
        add  r8,r0,0x5555aaaa
        add  r9,r0,0x000ffff1
        sra2h r30,r8,r9 ||nop
        srl2h r31,r8,r9 ||nop
 
        assert  r20, 0
        assert  r21, 0
        assert  r22, 0
        assert  r23, 0
        assert  r24, 0
        assert  r25, 0
        assert  r30, 0
        assert  r31, 0
 
 
        # PR 18196 - a.s
 
        add r1,r0,0xfedcba98
        add r2,r0,0x76543210
        add r3,r0,0x41
        add r4,r0,1
        nop                      || mvtacc a0 r1,r2
        nop                      || mvfacc r10,a0 r3
        nop                      || mvfacc r11,a0 r4
 
        assert r10, 0x3b2a1908
        assert r11, 0x3b2a1908
 
 
        # PR 18329 - a.s
 
        add r10,r0,0  || add r2,r0,-1
        add r11,r0,0  || add r12,r0,0
        add r13,r0,0  || add r14,r0,0
        add r15,r0,0  || add r16,r0,0
        add r17,r0,0  || add r18,r0,0
 
        add r3,r0,0x00000020    ; 32
        src r10,r2,r3
        add r3,r0,0x00000021    ; 33
        src r11,r2,r3
        add r3,r0,0x0000003f    ; 63
        src r12,r2,r3
        add r3,r0,0x00000040    ;64
        src r13,r2,r3
        add r3,r0,0x00000041    ;65
        src r14,r2,r3
 
        add r3,r0,0xffffffdf    ;-33
        src r15,r2,r3
        add r3,r0,0xffffffc1    ;-63
        src r16,r2,r3
        add r3,r0,0xffffffc0    ;-64
        src r17,r2,r3
        add r3,r0,0xffffffbf    ;-65
        src r18,r2,r3
 
        assert r10, 0x00000000
        assert r11, 0x80000000
        assert r12, 0xfffffffe
        assert r13, 0x00000000
        assert r14, 0x80000000
        assert r15, 0x00000001
        assert r16, 0x7fffffff
        assert r17, 0xffffffff
        assert r18, 0x00000001
 
 
        # PR 18364 - b.s
 
        add r1,r0,0x12345678
        add r2,r0,0x9abcdef0
        add r3,r0,0xffffffe0 ; -32
        add r4,r0,0xffffffc0 ; -64
        src r1,r2,r3 ||nop
        add r10,r1,r0 ||nop
        add r1,r0,0x12345678
        src r1,r2,r4 ||nop
        add r11,r1,r0 ||nop
 
        assert r10, 0x9abcdef0
        assert r11, 0x9abcdef0
 
 
        # all okay
 
        bra     ok
 
ok:
        add r2, r0, 0
        .long 0x0e000004
        nop
 
fail:
        add r2, r0, 47
        .long 0x0e000004
        nop

Line No.	Rev	Author	Line
1	1181	sfurman	`# Test macro`
2
3			`.macro assert reg,value`
4			`cmpeq f0,\reg,\value`
5			`bra/fx fail`
6			`.endm`
7
8
9			`# PR 14580 - a.s`
10
11			`add r8,r0,0x11112222`
12			`add r9,r0,-32`
13			`sra r1,r8,r9 \|\|nop`
14			`sra r2,r8,-32 \|\|nop`
15			`srl r3,r8,r9 \|\|nop`
16			`srl r4,r8,-32 \|\|nop`
17
18			`assert r1, 0`
19			`assert r2, 0`
20			`assert r3, 0`
21			`assert r4, 0`
22
23
24			`# PR 17266 - a.s`
25
26			`add r20, r0, 0xffffffff`
27			`add r21, r0, 0xffffffff`
28			`add r22, r0, 0xffffffff`
29			`add r23, r0, 0xffffffff`
30			`add r1, r0, 0x12345678`
31			`add r2, r0, -33`
32			`srahh r20, r1, r2`
33			`srahl r21, r1, r2`
34			`srlhh r22, r1, r2`
35			`srlhl r23, r1, r2`
36			`sra r24, r1, r2`
37			`srl r25, r1, r2`
38			`rot r26, r1, r2`
39
40			`assert r20, 0xacf0ffff`
41			`assert r21, 0xffffacf0`
42			`assert r22, 0xacf0ffff`
43			`assert r23, 0xffffacf0`
44			`assert r24, 0x2468acf0`
45			`assert r25, 0x2468acf0`
46			`assert r26, 0x2468acf0`
47
48
49			`# PR 17266 - a2.s`
50
51			`add r20, r0, 0xffffffff`
52			`add r21, r0, 0xffffffff`
53			`add r22, r0, 0xffffffff`
54			`add r23, r0, 0xffffffff`
55			`add r1, r0, 0x12345678`
56			`add r2, r0, -17`
57			`sra2h r20, r1, r2`
58			`srl2h r21, r1, r2`
59			`rot2h r22, r1, r2`
60
61			`assert r20, 0x2468acf0`
62			`assert r21, 0x2468acf0`
63			`assert r22, 0x2468acf0`
64
65
66			`# PR 17685 - a.s`
67
68			`add r20,r0,r0`
69			`add r21,r0,r0`
70			`add r22,r0,r0`
71			`add r23,r0,r0`
72			`add r24,r0,r0`
73			`add r25,r0,r0`
74			`add r30,r0,r0`
75			`add r31,r0,r0`
76
77			`add r8,r0,0x55555555`
78			`add r9,r0,0x1f`
79			`sra r20,r8,r9 \|\|nop`
80			`srl r21,r8,r9 \|\|nop`
81			`srahh r22,r8,r9 \|\|nop`
82			`srahl r23,r8,r9 \|\|nop`
83			`srlhh r24,r8,r9 \|\|nop`
84			`srlhl r25,r8,r9 \|\|nop`
85
86			`add r8,r0,0x5555aaaa`
87			`add r9,r0,0x000ffff1`
88			`sra2h r30,r8,r9 \|\|nop`
89			`srl2h r31,r8,r9 \|\|nop`
90
91			`assert r20, 0`
92			`assert r21, 0`
93			`assert r22, 0`
94			`assert r23, 0`
95			`assert r24, 0`
96			`assert r25, 0`
97			`assert r30, 0`
98			`assert r31, 0`
99
100
101			`# PR 18196 - a.s`
102
103			`add r1,r0,0xfedcba98`
104			`add r2,r0,0x76543210`
105			`add r3,r0,0x41`
106			`add r4,r0,1`
107			`nop \|\| mvtacc a0 r1,r2`
108			`nop \|\| mvfacc r10,a0 r3`
109			`nop \|\| mvfacc r11,a0 r4`
110
111			`assert r10, 0x3b2a1908`
112			`assert r11, 0x3b2a1908`
113
114
115			`# PR 18329 - a.s`
116
117			`add r10,r0,0 \|\| add r2,r0,-1`
118			`add r11,r0,0 \|\| add r12,r0,0`
119			`add r13,r0,0 \|\| add r14,r0,0`
120			`add r15,r0,0 \|\| add r16,r0,0`
121			`add r17,r0,0 \|\| add r18,r0,0`
122
123			`add r3,r0,0x00000020 ; 32`
124			`src r10,r2,r3`
125			`add r3,r0,0x00000021 ; 33`
126			`src r11,r2,r3`
127			`add r3,r0,0x0000003f ; 63`
128			`src r12,r2,r3`
129			`add r3,r0,0x00000040 ;64`
130			`src r13,r2,r3`
131			`add r3,r0,0x00000041 ;65`
132			`src r14,r2,r3`
133
134			`add r3,r0,0xffffffdf ;-33`
135			`src r15,r2,r3`
136			`add r3,r0,0xffffffc1 ;-63`
137			`src r16,r2,r3`
138			`add r3,r0,0xffffffc0 ;-64`
139			`src r17,r2,r3`
140			`add r3,r0,0xffffffbf ;-65`
141			`src r18,r2,r3`
142
143			`assert r10, 0x00000000`
144			`assert r11, 0x80000000`
145			`assert r12, 0xfffffffe`
146			`assert r13, 0x00000000`
147			`assert r14, 0x80000000`
148			`assert r15, 0x00000001`
149			`assert r16, 0x7fffffff`
150			`assert r17, 0xffffffff`
151			`assert r18, 0x00000001`
152
153
154			`# PR 18364 - b.s`
155
156			`add r1,r0,0x12345678`
157			`add r2,r0,0x9abcdef0`
158			`add r3,r0,0xffffffe0 ; -32`
159			`add r4,r0,0xffffffc0 ; -64`
160			`src r1,r2,r3 \|\|nop`
161			`add r10,r1,r0 \|\|nop`
162			`add r1,r0,0x12345678`
163			`src r1,r2,r4 \|\|nop`
164			`add r11,r1,r0 \|\|nop`
165
166			`assert r10, 0x9abcdef0`
167			`assert r11, 0x9abcdef0`
168
169
170			`# all okay`
171
172			`bra ok`
173
174			`ok:`
175			`add r2, r0, 0`
176			`.long 0x0e000004`
177			`nop`
178
179			`fail:`
180			`add r2, r0, 47`
181			`.long 0x0e000004`
182			`nop`

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[/] [or1k/] [tags/] [VER_5_3/] [gdb-5.3/] [sim/] [testsuite/] [d30v-elf/] [do-shifts.S] - Blame information for rev 1783