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[/] [or1k/] [tags/] [alpha/] [gen_or1k_isa/] [sources/] [body.tex] - Blame information for rev 1765

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1 80 lampret 
 
2 
\begin{document}
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\vspace{50mm}\section{OpenRISC 1000 Instruction Set}
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Draft, Do not distribute
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\newpage
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\vspace{10mm}
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\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
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{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
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\textbf{\huge l.illegal}&
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\multicolumn{1}{c}{\textbf{\huge Illegal instruction}}&
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\textbf{\huge l.illegal}\\
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\end{tabular}\par}
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\bigskip{}
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\vspace{10mm}
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{\centering \begin{tabular}{|cccccccccccccccccccccccccccccccc|}
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\hline
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0\\
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\hline
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\multicolumn{32}{|c|}{opcode 0x0}\\
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\hline
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\multicolumn{32}{|c|}{32 bits}\\
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\hline
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\end{tabular}\par}
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\vspace{15mm}
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{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
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\vspace{5mm}
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\begin{quotation}
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\texttt{\large l.illegal\ }{\large \par}
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\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Description:}{\LARGE \par}
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\vspace{5mm}
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\begin{quotation}
75 
\texttt{\large The result of this instruction is always an illegal instruction exception.}{\large \par}
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\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Operation:}{\LARGE \par}
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\vspace{5mm}
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\begin{quotation}
81 
PC <- address of illegal instruction exception handler
82 
\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Notes:}{\LARGE \par}
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\vspace{5mm}
86 
\begin{quotation}
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88 
\end{quotation}
89 
\vspace{10mm}
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\vfill
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Class 1:
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{\centering \begin{tabular}{|c|c|c|}
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\hline
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Architecture Level&
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Execution Mode&
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Implementation\\
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\hline
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Core CPU&User and Supervisor&Mandatory always\\
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\hline
100 
\end{tabular}\par}
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103 
 
104 
\newpage
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\vspace{10mm}
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\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
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{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
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\textbf{\huge l.j}&
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\multicolumn{1}{c}{\textbf{\huge Jump}}&
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\textbf{\huge l.j}\\
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\end{tabular}\par}
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\bigskip{}
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\vspace{10mm}
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{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
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\hline
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31&
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0\\
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\hline
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\multicolumn{6}{|c|}{opcode 0x0}&
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\multicolumn{26}{c|}{X}\\
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\hline
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\multicolumn{6}{|c|}{6 bits}&
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\multicolumn{26}{c|}{26 bits}\\
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\hline
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\end{tabular}\par}
164 
\vspace{15mm}
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{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
166 
\vspace{5mm}
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\begin{quotation}
168 
\texttt{\large l.j\ X}{\large \par}
169 
\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Description:}{\LARGE \par}
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\vspace{5mm}
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\begin{quotation}
174 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
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\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Operation:}{\LARGE \par}
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\vspace{5mm}
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\begin{quotation}
180 
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
181 
\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Notes:}{\LARGE \par}
184 
\vspace{5mm}
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\begin{quotation}
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187 
\end{quotation}
188 
\vspace{10mm}
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\vfill
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Class 1:
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{\centering \begin{tabular}{|c|c|c|}
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\hline
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Architecture Level&
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Execution Mode&
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Implementation\\
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\hline
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Core CPU&User and Supervisor&Mandatory always\\
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\hline
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\end{tabular}\par}
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\newpage
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\vspace{10mm}
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\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
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{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
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\textbf{\huge l.jal}&
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\multicolumn{1}{c}{\textbf{\huge Jump and Link}}&
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\textbf{\huge l.jal}\\
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\end{tabular}\par}
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\bigskip{}
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\vspace{10mm}
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{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
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\hline
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0\\
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\hline
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\multicolumn{6}{|c|}{opcode 0x1}&
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\multicolumn{26}{c|}{X}\\
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\hline
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\multicolumn{6}{|c|}{6 bits}&
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\multicolumn{26}{c|}{26 bits}\\
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261 
\hline
262 
\end{tabular}\par}
263 
\vspace{15mm}
264 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
265 
\vspace{5mm}
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\begin{quotation}
267 
\texttt{\large l.jal\ X}{\large \par}
268 
\end{quotation}
269 
\vspace{10mm}
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\textbf{\LARGE Description:}{\LARGE \par}
271 
\vspace{5mm}
272 
\begin{quotation}
273 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
274 
\end{quotation}
275 
\vspace{10mm}
276 
\textbf{\LARGE Operation:}{\LARGE \par}
277 
\vspace{5mm}
278 
\begin{quotation}
279 
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
280 
\end{quotation}
281 
\vspace{10mm}
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\textbf{\LARGE Notes:}{\LARGE \par}
283 
\vspace{5mm}
284 
\begin{quotation}
285 
 
286 
\end{quotation}
287 
\vspace{10mm}
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\vfill
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Class 1:
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{\centering \begin{tabular}{|c|c|c|}
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\hline
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Architecture Level&
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Execution Mode&
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Implementation\\
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\hline
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Core CPU&User and Supervisor&Mandatory always\\
297 
\hline
298 
\end{tabular}\par}
299 
 
300 
 
301 
 
302 
\newpage
303 
\vspace{10mm}
304 
\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
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{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
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\textbf{\huge l.bnf}&
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\multicolumn{1}{c}{\textbf{\huge Branch if No Flag}}&
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\textbf{\huge l.bnf}\\
314 
\end{tabular}\par}
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\bigskip{}
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\vspace{10mm}
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{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
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\hline
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0\\
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\hline
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\multicolumn{6}{|c|}{opcode 0x2}&
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\multicolumn{26}{c|}{X}\\
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356 
\hline
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\multicolumn{6}{|c|}{6 bits}&
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\multicolumn{26}{c|}{26 bits}\\
359 
 
360 
\hline
361 
\end{tabular}\par}
362 
\vspace{15mm}
363 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
364 
\vspace{5mm}
365 
\begin{quotation}
366 
\texttt{\large l.bnf\ X}{\large \par}
367 
\end{quotation}
368 
\vspace{10mm}
369 
\textbf{\LARGE Description:}{\LARGE \par}
370 
\vspace{5mm}
371 
\begin{quotation}
372 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is cleared, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
373 
\end{quotation}
374 
\vspace{10mm}
375 
\textbf{\LARGE Operation:}{\LARGE \par}
376 
\vspace{5mm}
377 
\begin{quotation}
378 
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared
379 
\end{quotation}
380 
\vspace{10mm}
381 
\textbf{\LARGE Notes:}{\LARGE \par}
382 
\vspace{5mm}
383 
\begin{quotation}
384 
 
385 
\end{quotation}
386 
\vspace{10mm}
387 
\vfill
388 
Class 1:
389 
{\centering \begin{tabular}{|c|c|c|}
390 
\hline
391 
Architecture Level&
392 
Execution Mode&
393 
Implementation\\
394 
\hline
395 
Core CPU&User and Supervisor&Mandatory always\\
396 
\hline
397 
\end{tabular}\par}
398 
 
399 
 
400 
 
401 
\newpage
402 
\vspace{10mm}
403 
\lyxline{\small}\vspace{-1\parskip}
404 
\vspace{10mm}
405 
{\raggedright \begin{tabular}{ccc}
406 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
407 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
409 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
410 
\textbf{\huge l.bf}&
411 
\multicolumn{1}{c}{\textbf{\huge Branch if Flag}}&
412 
\textbf{\huge l.bf}\\
413 
\end{tabular}\par}
414 
\bigskip{}
415 
 
416 
\vspace{10mm}
417 
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
418 
\hline
419 
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451 
\hline
452 
\multicolumn{6}{|c|}{opcode 0x3}&
453 
\multicolumn{26}{c|}{X}\\
454 
 
455 
\hline
456 
\multicolumn{6}{|c|}{6 bits}&
457 
\multicolumn{26}{c|}{26 bits}\\
458 
 
459 
\hline
460 
\end{tabular}\par}
461 
\vspace{15mm}
462 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
463 
\vspace{5mm}
464 
\begin{quotation}
465 
\texttt{\large l.bf\ X}{\large \par}
466 
\end{quotation}
467 
\vspace{10mm}
468 
\textbf{\LARGE Description:}{\LARGE \par}
469 
\vspace{5mm}
470 
\begin{quotation}
471 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is set, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
472 
\end{quotation}
473 
\vspace{10mm}
474 
\textbf{\LARGE Operation:}{\LARGE \par}
475 
\vspace{5mm}
476 
\begin{quotation}
477 
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set
478 
\end{quotation}
479 
\vspace{10mm}
480 
\textbf{\LARGE Notes:}{\LARGE \par}
481 
\vspace{5mm}
482 
\begin{quotation}
483 
 
484 
\end{quotation}
485 
\vspace{10mm}
486 
\vfill
487 
Class 1:
488 
{\centering \begin{tabular}{|c|c|c|}
489 
\hline
490 
Architecture Level&
491 
Execution Mode&
492 
Implementation\\
493 
\hline
494 
Core CPU&User and Supervisor&Mandatory always\\
495 
\hline
496 
\end{tabular}\par}
497 
 
498 
 
499 
 
500 
\newpage
501 
\vspace{10mm}
502 
\lyxline{\small}\vspace{-1\parskip}
503 
\vspace{10mm}
504 
{\raggedright \begin{tabular}{ccc}
505 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
506 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
507 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
508 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
509 
\textbf{\huge l.load32u}&
510 
\multicolumn{1}{c}{\textbf{\huge Load Word and Extend with Zero}}&
511 
\textbf{\huge l.load32u}\\
512 
\end{tabular}\par}
513 
\bigskip{}
514 
 
515 
\vspace{10mm}
516 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
517 
\hline
518 
31&
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0\\
550 
\hline
551 
\multicolumn{7}{|c|}{opcode 0x8}&
552 
\multicolumn{1}{c|}{J}&
553 
\multicolumn{4}{c|}{A}&
554 
\multicolumn{4}{c|}{B}&
555 
\multicolumn{16}{c|}{J}\\
556 
 
557 
\hline
558 
\multicolumn{7}{|c|}{7 bits}&
559 
\multicolumn{1}{c|}{1 bits}&
560 
\multicolumn{4}{c|}{4 bits}&
561 
\multicolumn{4}{c|}{4 bits}&
562 
\multicolumn{16}{c|}{16 bits}\\
563 
 
564 
\hline
565 
\end{tabular}\par}
566 
\vspace{15mm}
567 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
568 
\vspace{5mm}
569 
\begin{quotation}
570 
\texttt{\large l.load32u\ rA,J(rB)}{\large \par}
571 
\end{quotation}
572 
\vspace{10mm}
573 
\textbf{\LARGE Description:}{\LARGE \par}
574 
\vspace{5mm}
575 
\begin{quotation}
576 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The word in memory addressed by EA is loaded into general register rA. }{\large \par}
577 
\end{quotation}
578 
\vspace{10mm}
579 
\textbf{\LARGE Operation:}{\LARGE \par}
580 
\vspace{5mm}
581 
\begin{quotation}
582 
EA <- exts(Immediate) + rB\\rA <- (EA){[}31:0{]}
583 
\end{quotation}
584 
\vspace{10mm}
585 
\textbf{\LARGE Notes:}{\LARGE \par}
586 
\vspace{5mm}
587 
\begin{quotation}
588 
 
589 
\end{quotation}
590 
\vspace{10mm}
591 
\vfill
592 
Class 1:
593 
{\centering \begin{tabular}{|c|c|c|}
594 
\hline
595 
Architecture Level&
596 
Execution Mode&
597 
Implementation\\
598 
\hline
599 
Core CPU&User and Supervisor&Mandatory always\\
600 
\hline
601 
\end{tabular}\par}
602 
 
603 
 
604 
 
605 
\newpage
606 
\vspace{10mm}
607 
\lyxline{\small}\vspace{-1\parskip}
608 
\vspace{10mm}
609 
{\raggedright \begin{tabular}{ccc}
610 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
611 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
612 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
613 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
614 
\textbf{\huge l.load16u}&
615 
\multicolumn{1}{c}{\textbf{\huge Load Half Word and Extend with Zero}}&
616 
\textbf{\huge l.load16u}\\
617 
\end{tabular}\par}
618 
\bigskip{}
619 
 
620 
\vspace{10mm}
621 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
622 
\hline
623 
31&
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0\\
655 
\hline
656 
\multicolumn{7}{|c|}{opcode 0x9}&
657 
\multicolumn{1}{c|}{J}&
658 
\multicolumn{4}{c|}{A}&
659 
\multicolumn{4}{c|}{B}&
660 
\multicolumn{16}{c|}{J}\\
661 
 
662 
\hline
663 
\multicolumn{7}{|c|}{7 bits}&
664 
\multicolumn{1}{c|}{1 bits}&
665 
\multicolumn{4}{c|}{4 bits}&
666 
\multicolumn{4}{c|}{4 bits}&
667 
\multicolumn{16}{c|}{16 bits}\\
668 
 
669 
\hline
670 
\end{tabular}\par}
671 
\vspace{15mm}
672 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
673 
\vspace{5mm}
674 
\begin{quotation}
675 
\texttt{\large l.load16u\ rA,J(rB)}{\large \par}
676 
\end{quotation}
677 
\vspace{10mm}
678 
\textbf{\LARGE Description:}{\LARGE \par}
679 
\vspace{5mm}
680 
\begin{quotation}
681 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The half word in memory addressed by EA is loaded into the low-order 16 bits of general register rA. High-order 16 bits of general register rA are replaced with zero.}{\large \par}
682 
\end{quotation}
683 
\vspace{10mm}
684 
\textbf{\LARGE Operation:}{\LARGE \par}
685 
\vspace{5mm}
686 
\begin{quotation}
687 
EA <- exts(Immediate) + rB\\rA{[}15:0{]} <- (EA){[}15:0{]}\\rA{[}31:16{]} <- 0
688 
\end{quotation}
689 
\vspace{10mm}
690 
\textbf{\LARGE Notes:}{\LARGE \par}
691 
\vspace{5mm}
692 
\begin{quotation}
693 
 
694 
\end{quotation}
695 
\vspace{10mm}
696 
\vfill
697 
Class 1:
698 
{\centering \begin{tabular}{|c|c|c|}
699 
\hline
700 
Architecture Level&
701 
Execution Mode&
702 
Implementation\\
703 
\hline
704 
Core CPU&User and Supervisor&Mandatory always\\
705 
\hline
706 
\end{tabular}\par}
707 
 
708 
 
709 
 
710 
\newpage
711 
\vspace{10mm}
712 
\lyxline{\small}\vspace{-1\parskip}
713 
\vspace{10mm}
714 
{\raggedright \begin{tabular}{ccc}
715 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
716 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
717 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
718 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
719 
\textbf{\huge l.load16s}&
720 
\multicolumn{1}{c}{\textbf{\huge Load Half Word and Extend with Sign}}&
721 
\textbf{\huge l.load16s}\\
722 
\end{tabular}\par}
723 
\bigskip{}
724 
 
725 
\vspace{10mm}
726 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
727 
\hline
728 
31&
729 
&
730 
&
731 
&
732 
&
733 
&
734 
25&
735 
24&
736 
23&
737 
&
738 
&
739 
20&
740 
19&
741 
&
742 
&
743 
16&
744 
15&
745 
&
746 
&
747 
&
748 
&
749 
&
750 
&
751 
&
752 
&
753 
&
754 
&
755 
&
756 
&
757 
&
758 
&
759 
0\\
760 
\hline
761 
\multicolumn{7}{|c|}{opcode 0xa}&
762 
\multicolumn{1}{c|}{J}&
763 
\multicolumn{4}{c|}{A}&
764 
\multicolumn{4}{c|}{B}&
765 
\multicolumn{16}{c|}{J}\\
766 
 
767 
\hline
768 
\multicolumn{7}{|c|}{7 bits}&
769 
\multicolumn{1}{c|}{1 bits}&
770 
\multicolumn{4}{c|}{4 bits}&
771 
\multicolumn{4}{c|}{4 bits}&
772 
\multicolumn{16}{c|}{16 bits}\\
773 
 
774 
\hline
775 
\end{tabular}\par}
776 
\vspace{15mm}
777 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
778 
\vspace{5mm}
779 
\begin{quotation}
780 
\texttt{\large l.load16s\ rA,J(rB)}{\large \par}
781 
\end{quotation}
782 
\vspace{10mm}
783 
\textbf{\LARGE Description:}{\LARGE \par}
784 
\vspace{5mm}
785 
\begin{quotation}
786 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The half word in memory addressed by EA is loaded into the low-order 16 bits of general register rA. High-order 16 bits of general register rA are replaced with bit 15 of the loaded value.}{\large \par}
787 
\end{quotation}
788 
\vspace{10mm}
789 
\textbf{\LARGE Operation:}{\LARGE \par}
790 
\vspace{5mm}
791 
\begin{quotation}
792 
EA <- exts(Immediate) + rB\\rA{[}15:0{]} <- (EA){[}15:0{]}\\rA{[}31:16{]} <- rA{[}15{]}
793 
\end{quotation}
794 
\vspace{10mm}
795 
\textbf{\LARGE Notes:}{\LARGE \par}
796 
\vspace{5mm}
797 
\begin{quotation}
798 
 
799 
\end{quotation}
800 
\vspace{10mm}
801 
\vfill
802 
Class 1:
803 
{\centering \begin{tabular}{|c|c|c|}
804 
\hline
805 
Architecture Level&
806 
Execution Mode&
807 
Implementation\\
808 
\hline
809 
Core CPU&User and Supervisor&Mandatory always\\
810 
\hline
811 
\end{tabular}\par}
812 
 
813 
 
814 
 
815 
\newpage
816 
\vspace{10mm}
817 
\lyxline{\small}\vspace{-1\parskip}
818 
\vspace{10mm}
819 
{\raggedright \begin{tabular}{ccc}
820 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
821 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
822 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
823 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
824 
\textbf{\huge l.load8u}&
825 
\multicolumn{1}{c}{\textbf{\huge Load Byte and Extend with Zero}}&
826 
\textbf{\huge l.load8u}\\
827 
\end{tabular}\par}
828 
\bigskip{}
829 
 
830 
\vspace{10mm}
831 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
832 
\hline
833 
31&
834 
&
835 
&
836 
&
837 
&
838 
&
839 
25&
840 
24&
841 
23&
842 
&
843 
&
844 
20&
845 
19&
846 
&
847 
&
848 
16&
849 
15&
850 
&
851 
&
852 
&
853 
&
854 
&
855 
&
856 
&
857 
&
858 
&
859 
&
860 
&
861 
&
862 
&
863 
&
864 
0\\
865 
\hline
866 
\multicolumn{7}{|c|}{opcode 0xb}&
867 
\multicolumn{1}{c|}{J}&
868 
\multicolumn{4}{c|}{A}&
869 
\multicolumn{4}{c|}{B}&
870 
\multicolumn{16}{c|}{J}\\
871 
 
872 
\hline
873 
\multicolumn{7}{|c|}{7 bits}&
874 
\multicolumn{1}{c|}{1 bits}&
875 
\multicolumn{4}{c|}{4 bits}&
876 
\multicolumn{4}{c|}{4 bits}&
877 
\multicolumn{16}{c|}{16 bits}\\
878 
 
879 
\hline
880 
\end{tabular}\par}
881 
\vspace{15mm}
882 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
883 
\vspace{5mm}
884 
\begin{quotation}
885 
\texttt{\large l.load8u\ rA,J(rB)}{\large \par}
886 
\end{quotation}
887 
\vspace{10mm}
888 
\textbf{\LARGE Description:}{\LARGE \par}
889 
\vspace{5mm}
890 
\begin{quotation}
891 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The byte in memory addressed by EA is loaded into the low-order eight bits of general register rA. High-order 24 bits of general register rA are replaced with zero.}{\large \par}
892 
\end{quotation}
893 
\vspace{10mm}
894 
\textbf{\LARGE Operation:}{\LARGE \par}
895 
\vspace{5mm}
896 
\begin{quotation}
897 
EA <- exts(Immediate) + rB\\rA{[}7:0{]} <- (EA){[}7:0{]}\\rA{[}31:8{]} <- 0
898 
\end{quotation}
899 
\vspace{10mm}
900 
\textbf{\LARGE Notes:}{\LARGE \par}
901 
\vspace{5mm}
902 
\begin{quotation}
903 
 
904 
\end{quotation}
905 
\vspace{10mm}
906 
\vfill
907 
Class 1:
908 
{\centering \begin{tabular}{|c|c|c|}
909 
\hline
910 
Architecture Level&
911 
Execution Mode&
912 
Implementation\\
913 
\hline
914 
Core CPU&User and Supervisor&Mandatory always\\
915 
\hline
916 
\end{tabular}\par}
917 
 
918 
 
919 
 
920 
\newpage
921 
\vspace{10mm}
922 
\lyxline{\small}\vspace{-1\parskip}
923 
\vspace{10mm}
924 
{\raggedright \begin{tabular}{ccc}
925 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
926 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
927 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
928 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
929 
\textbf{\huge l.load8s}&
930 
\multicolumn{1}{c}{\textbf{\huge Load Byte and Extend with Sign}}&
931 
\textbf{\huge l.load8s}\\
932 
\end{tabular}\par}
933 
\bigskip{}
934 
 
935 
\vspace{10mm}
936 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
937 
\hline
938 
31&
939 
&
940 
&
941 
&
942 
&
943 
&
944 
25&
945 
24&
946 
23&
947 
&
948 
&
949 
20&
950 
19&
951 
&
952 
&
953 
16&
954 
15&
955 
&
956 
&
957 
&
958 
&
959 
&
960 
&
961 
&
962 
&
963 
&
964 
&
965 
&
966 
&
967 
&
968 
&
969 
0\\
970 
\hline
971 
\multicolumn{7}{|c|}{opcode 0xc}&
972 
\multicolumn{1}{c|}{J}&
973 
\multicolumn{4}{c|}{A}&
974 
\multicolumn{4}{c|}{B}&
975 
\multicolumn{16}{c|}{J}\\
976 
 
977 
\hline
978 
\multicolumn{7}{|c|}{7 bits}&
979 
\multicolumn{1}{c|}{1 bits}&
980 
\multicolumn{4}{c|}{4 bits}&
981 
\multicolumn{4}{c|}{4 bits}&
982 
\multicolumn{16}{c|}{16 bits}\\
983 
 
984 
\hline
985 
\end{tabular}\par}
986 
\vspace{15mm}
987 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
988 
\vspace{5mm}
989 
\begin{quotation}
990 
\texttt{\large l.load8s\ rA,J(rB)}{\large \par}
991 
\end{quotation}
992 
\vspace{10mm}
993 
\textbf{\LARGE Description:}{\LARGE \par}
994 
\vspace{5mm}
995 
\begin{quotation}
996 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The byte in memory addressed by EA is loaded into the low-order eight bits of general register rA. High-order 24 bits of general register rA are replaced with bit 7 of the loaded value.}{\large \par}
997 
\end{quotation}
998 
\vspace{10mm}
999 
\textbf{\LARGE Operation:}{\LARGE \par}
1000 
\vspace{5mm}
1001 
\begin{quotation}
1002 
EA <- exts(Immediate) + rB\\rA{[}7:0{]} <- (EA){[}7:0{]}\\rA{[}31:8{]} <- rA{[}8{]}
1003 
\end{quotation}
1004 
\vspace{10mm}
1005 
\textbf{\LARGE Notes:}{\LARGE \par}
1006 
\vspace{5mm}
1007 
\begin{quotation}
1008 
 
1009 
\end{quotation}
1010 
\vspace{10mm}
1011 
\vfill
1012 
Class 1:
1013 
{\centering \begin{tabular}{|c|c|c|}
1014 
\hline
1015 
Architecture Level&
1016 
Execution Mode&
1017 
Implementation\\
1018 
\hline
1019 
Core CPU&User and Supervisor&Mandatory always\\
1020 
\hline
1021 
\end{tabular}\par}
1022 
 
1023 
 
1024 
 
1025 
\newpage
1026 
\vspace{10mm}
1027 
\lyxline{\small}\vspace{-1\parskip}
1028 
\vspace{10mm}
1029 
{\raggedright \begin{tabular}{ccc}
1030 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1031 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1032 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1033 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1034 
\textbf{\huge l.stor32}&
1035 
\multicolumn{1}{c}{\textbf{\huge Store Word}}&
1036 
\textbf{\huge l.stor32}\\
1037 
\end{tabular}\par}
1038 
\bigskip{}
1039 
 
1040 
\vspace{10mm}
1041 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1042 
\hline
1043 
31&
1044 
&
1045 
&
1046 
&
1047 
&
1048 
&
1049 
25&
1050 
24&
1051 
23&
1052 
&
1053 
&
1054 
20&
1055 
19&
1056 
&
1057 
&
1058 
16&
1059 
15&
1060 
&
1061 
&
1062 
&
1063 
&
1064 
&
1065 
&
1066 
&
1067 
&
1068 
&
1069 
&
1070 
&
1071 
&
1072 
&
1073 
&
1074 
0\\
1075 
\hline
1076 
\multicolumn{7}{|c|}{opcode 0xd}&
1077 
\multicolumn{1}{c|}{J}&
1078 
\multicolumn{4}{c|}{A}&
1079 
\multicolumn{4}{c|}{B}&
1080 
\multicolumn{16}{c|}{J}\\
1081 
 
1082 
\hline
1083 
\multicolumn{7}{|c|}{7 bits}&
1084 
\multicolumn{1}{c|}{1 bits}&
1085 
\multicolumn{4}{c|}{4 bits}&
1086 
\multicolumn{4}{c|}{4 bits}&
1087 
\multicolumn{16}{c|}{16 bits}\\
1088 
 
1089 
\hline
1090 
\end{tabular}\par}
1091 
\vspace{15mm}
1092 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1093 
\vspace{5mm}
1094 
\begin{quotation}
1095 
\texttt{\large l.stor32\ J(rA),rB}{\large \par}
1096 
\end{quotation}
1097 
\vspace{10mm}
1098 
\textbf{\LARGE Description:}{\LARGE \par}
1099 
\vspace{5mm}
1100 
\begin{quotation}
1101 
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The word in general register rB is stored to memory addressed by EA. }{\large \par}
1102 
\end{quotation}
1103 
\vspace{10mm}
1104 
\textbf{\LARGE Operation:}{\LARGE \par}
1105 
\vspace{5mm}
1106 
\begin{quotation}
1107 
EA <- exts(Immediate) + rA\\(EA){[}31:0{]} <- rB
1108 
\end{quotation}
1109 
\vspace{10mm}
1110 
\textbf{\LARGE Notes:}{\LARGE \par}
1111 
\vspace{5mm}
1112 
\begin{quotation}
1113 
 
1114 
\end{quotation}
1115 
\vspace{10mm}
1116 
\vfill
1117 
Class 1:
1118 
{\centering \begin{tabular}{|c|c|c|}
1119 
\hline
1120 
Architecture Level&
1121 
Execution Mode&
1122 
Implementation\\
1123 
\hline
1124 
Core CPU&User and Supervisor&Mandatory always\\
1125 
\hline
1126 
\end{tabular}\par}
1127 
 
1128 
 
1129 
 
1130 
\newpage
1131 
\vspace{10mm}
1132 
\lyxline{\small}\vspace{-1\parskip}
1133 
\vspace{10mm}
1134 
{\raggedright \begin{tabular}{ccc}
1135 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1136 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1137 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1138 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1139 
\textbf{\huge l.stor16}&
1140 
\multicolumn{1}{c}{\textbf{\huge Store Half Word}}&
1141 
\textbf{\huge l.stor16}\\
1142 
\end{tabular}\par}
1143 
\bigskip{}
1144 
 
1145 
\vspace{10mm}
1146 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1147 
\hline
1148 
31&
1149 
&
1150 
&
1151 
&
1152 
&
1153 
&
1154 
25&
1155 
24&
1156 
23&
1157 
&
1158 
&
1159 
20&
1160 
19&
1161 
&
1162 
&
1163 
16&
1164 
15&
1165 
&
1166 
&
1167 
&
1168 
&
1169 
&
1170 
&
1171 
&
1172 
&
1173 
&
1174 
&
1175 
&
1176 
&
1177 
&
1178 
&
1179 
0\\
1180 
\hline
1181 
\multicolumn{7}{|c|}{opcode 0xe}&
1182 
\multicolumn{1}{c|}{J}&
1183 
\multicolumn{4}{c|}{A}&
1184 
\multicolumn{4}{c|}{B}&
1185 
\multicolumn{16}{c|}{J}\\
1186 
 
1187 
\hline
1188 
\multicolumn{7}{|c|}{7 bits}&
1189 
\multicolumn{1}{c|}{1 bits}&
1190 
\multicolumn{4}{c|}{4 bits}&
1191 
\multicolumn{4}{c|}{4 bits}&
1192 
\multicolumn{16}{c|}{16 bits}\\
1193 
 
1194 
\hline
1195 
\end{tabular}\par}
1196 
\vspace{15mm}
1197 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1198 
\vspace{5mm}
1199 
\begin{quotation}
1200 
\texttt{\large l.stor16\ J(rA),rB}{\large \par}
1201 
\end{quotation}
1202 
\vspace{10mm}
1203 
\textbf{\LARGE Description:}{\LARGE \par}
1204 
\vspace{5mm}
1205 
\begin{quotation}
1206 
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The low-order 16 bits of general register rB are stored to memory addressed by EA. }{\large \par}
1207 
\end{quotation}
1208 
\vspace{10mm}
1209 
\textbf{\LARGE Operation:}{\LARGE \par}
1210 
\vspace{5mm}
1211 
\begin{quotation}
1212 
EA <- exts(Immediate) + rA\\(EA){[}15:0{]} <- rB{[}15:0{]}
1213 
\end{quotation}
1214 
\vspace{10mm}
1215 
\textbf{\LARGE Notes:}{\LARGE \par}
1216 
\vspace{5mm}
1217 
\begin{quotation}
1218 
 
1219 
\end{quotation}
1220 
\vspace{10mm}
1221 
\vfill
1222 
Class 1:
1223 
{\centering \begin{tabular}{|c|c|c|}
1224 
\hline
1225 
Architecture Level&
1226 
Execution Mode&
1227 
Implementation\\
1228 
\hline
1229 
Core CPU&User and Supervisor&Mandatory always\\
1230 
\hline
1231 
\end{tabular}\par}
1232 
 
1233 
 
1234 
 
1235 
\newpage
1236 
\vspace{10mm}
1237 
\lyxline{\small}\vspace{-1\parskip}
1238 
\vspace{10mm}
1239 
{\raggedright \begin{tabular}{ccc}
1240 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1241 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1242 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1243 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1244 
\textbf{\huge l.stor8}&
1245 
\multicolumn{1}{c}{\textbf{\huge Store Byte}}&
1246 
\textbf{\huge l.stor8}\\
1247 
\end{tabular}\par}
1248 
\bigskip{}
1249 
 
1250 
\vspace{10mm}
1251 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1252 
\hline
1253 
31&
1254 
&
1255 
&
1256 
&
1257 
&
1258 
&
1259 
25&
1260 
24&
1261 
23&
1262 
&
1263 
&
1264 
20&
1265 
19&
1266 
&
1267 
&
1268 
16&
1269 
15&
1270 
&
1271 
&
1272 
&
1273 
&
1274 
&
1275 
&
1276 
&
1277 
&
1278 
&
1279 
&
1280 
&
1281 
&
1282 
&
1283 
&
1284 
0\\
1285 
\hline
1286 
\multicolumn{7}{|c|}{opcode 0xf}&
1287 
\multicolumn{1}{c|}{J}&
1288 
\multicolumn{4}{c|}{A}&
1289 
\multicolumn{4}{c|}{B}&
1290 
\multicolumn{16}{c|}{J}\\
1291 
 
1292 
\hline
1293 
\multicolumn{7}{|c|}{7 bits}&
1294 
\multicolumn{1}{c|}{1 bits}&
1295 
\multicolumn{4}{c|}{4 bits}&
1296 
\multicolumn{4}{c|}{4 bits}&
1297 
\multicolumn{16}{c|}{16 bits}\\
1298 
 
1299 
\hline
1300 
\end{tabular}\par}
1301 
\vspace{15mm}
1302 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1303 
\vspace{5mm}
1304 
\begin{quotation}
1305 
\texttt{\large l.stor8\ J(rA),rB}{\large \par}
1306 
\end{quotation}
1307 
\vspace{10mm}
1308 
\textbf{\LARGE Description:}{\LARGE \par}
1309 
\vspace{5mm}
1310 
\begin{quotation}
1311 
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The low-order 8 bits of general register rB are stored to memory addressed by EA. }{\large \par}
1312 
\end{quotation}
1313 
\vspace{10mm}
1314 
\textbf{\LARGE Operation:}{\LARGE \par}
1315 
\vspace{5mm}
1316 
\begin{quotation}
1317 
EA <- exts(Immediate) + rA\\(EA){[}7:0{]} <- rB{[}7:0{]}
1318 
\end{quotation}
1319 
\vspace{10mm}
1320 
\textbf{\LARGE Notes:}{\LARGE \par}
1321 
\vspace{5mm}
1322 
\begin{quotation}
1323 
 
1324 
\end{quotation}
1325 
\vspace{10mm}
1326 
\vfill
1327 
Class 1:
1328 
{\centering \begin{tabular}{|c|c|c|}
1329 
\hline
1330 
Architecture Level&
1331 
Execution Mode&
1332 
Implementation\\
1333 
\hline
1334 
Core CPU&User and Supervisor&Mandatory always\\
1335 
\hline
1336 
\end{tabular}\par}
1337 
 
1338 
 
1339 
 
1340 
\newpage
1341 
\vspace{10mm}
1342 
\lyxline{\small}\vspace{-1\parskip}
1343 
\vspace{10mm}
1344 
{\raggedright \begin{tabular}{ccc}
1345 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1346 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1347 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1348 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1349 
\textbf{\huge l.addi32s}&
1350 
\multicolumn{1}{c}{\textbf{\huge Add Immediate Signed}}&
1351 
\textbf{\huge l.addi32s}\\
1352 
\end{tabular}\par}
1353 
\bigskip{}
1354 
 
1355 
\vspace{10mm}
1356 
{\centering \begin{tabular}{|cccccc|cc|cccc|cccc|cccccccccccccccc|}
1357 
\hline
1358 
31&
1359 
&
1360 
&
1361 
&
1362 
&
1363 
26&
1364 
25&
1365 
24&
1366 
23&
1367 
&
1368 
&
1369 
20&
1370 
19&
1371 
&
1372 
&
1373 
16&
1374 
15&
1375 
&
1376 
&
1377 
&
1378 
&
1379 
&
1380 
&
1381 
&
1382 
&
1383 
&
1384 
&
1385 
&
1386 
&
1387 
&
1388 
&
1389 
0\\
1390 
\hline
1391 
\multicolumn{6}{|c|}{opcode 0x8}&
1392 
\multicolumn{2}{c|}{I}&
1393 
\multicolumn{4}{c|}{A}&
1394 
\multicolumn{4}{c|}{B}&
1395 
\multicolumn{16}{c|}{I}\\
1396 
 
1397 
\hline
1398 
\multicolumn{6}{|c|}{6 bits}&
1399 
\multicolumn{2}{c|}{2 bits}&
1400 
\multicolumn{4}{c|}{4 bits}&
1401 
\multicolumn{4}{c|}{4 bits}&
1402 
\multicolumn{16}{c|}{16 bits}\\
1403 
 
1404 
\hline
1405 
\end{tabular}\par}
1406 
\vspace{15mm}
1407 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1408 
\vspace{5mm}
1409 
\begin{quotation}
1410 
\texttt{\large l.addi32s\ rA,rB,I}{\large \par}
1411 
\end{quotation}
1412 
\vspace{10mm}
1413 
\textbf{\LARGE Description:}{\LARGE \par}
1414 
\vspace{5mm}
1415 
\begin{quotation}
1416 
\texttt{\large Immediate is signed-extended and added to the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
1417 
\end{quotation}
1418 
\vspace{10mm}
1419 
\textbf{\LARGE Operation:}{\LARGE \par}
1420 
\vspace{5mm}
1421 
\begin{quotation}
1422 
rA <- rB + exts(Immediate)
1423 
\end{quotation}
1424 
\vspace{10mm}
1425 
\textbf{\LARGE Notes:}{\LARGE \par}
1426 
\vspace{5mm}
1427 
\begin{quotation}
1428 
 
1429 
\end{quotation}
1430 
\vspace{10mm}
1431 
\vfill
1432 
Class 1:
1433 
{\centering \begin{tabular}{|c|c|c|}
1434 
\hline
1435 
Architecture Level&
1436 
Execution Mode&
1437 
Implementation\\
1438 
\hline
1439 
Core CPU&User and Supervisor&Mandatory always\\
1440 
\hline
1441 
\end{tabular}\par}
1442 
 
1443 
 
1444 
 
1445 
\newpage
1446 
\vspace{10mm}
1447 
\lyxline{\small}\vspace{-1\parskip}
1448 
\vspace{10mm}
1449 
{\raggedright \begin{tabular}{ccc}
1450 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1451 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1452 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1453 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1454 
\textbf{\huge l.subi32s}&
1455 
\multicolumn{1}{c}{\textbf{\huge Subtract Immediate Signed}}&
1456 
\textbf{\huge l.subi32s}\\
1457 
\end{tabular}\par}
1458 
\bigskip{}
1459 
 
1460 
\vspace{10mm}
1461 
{\centering \begin{tabular}{|cccccc|cc|cccc|cccc|cccccccccccccccc|}
1462 
\hline
1463 
31&
1464 
&
1465 
&
1466 
&
1467 
&
1468 
26&
1469 
25&
1470 
24&
1471 
23&
1472 
&
1473 
&
1474 
20&
1475 
19&
1476 
&
1477 
&
1478 
16&
1479 
15&
1480 
&
1481 
&
1482 
&
1483 
&
1484 
&
1485 
&
1486 
&
1487 
&
1488 
&
1489 
&
1490 
&
1491 
&
1492 
&
1493 
&
1494 
0\\
1495 
\hline
1496 
\multicolumn{6}{|c|}{opcode 0x9}&
1497 
\multicolumn{2}{c|}{I}&
1498 
\multicolumn{4}{c|}{A}&
1499 
\multicolumn{4}{c|}{B}&
1500 
\multicolumn{16}{c|}{I}\\
1501 
 
1502 
\hline
1503 
\multicolumn{6}{|c|}{6 bits}&
1504 
\multicolumn{2}{c|}{2 bits}&
1505 
\multicolumn{4}{c|}{4 bits}&
1506 
\multicolumn{4}{c|}{4 bits}&
1507 
\multicolumn{16}{c|}{16 bits}\\
1508 
 
1509 
\hline
1510 
\end{tabular}\par}
1511 
\vspace{15mm}
1512 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1513 
\vspace{5mm}
1514 
\begin{quotation}
1515 
\texttt{\large l.subi32s\ rA,rB,I}{\large \par}
1516 
\end{quotation}
1517 
\vspace{10mm}
1518 
\textbf{\LARGE Description:}{\LARGE \par}
1519 
\vspace{5mm}
1520 
\begin{quotation}
1521 
\texttt{\large Immediate is signed-extended and subtracted from the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
1522 
\end{quotation}
1523 
\vspace{10mm}
1524 
\textbf{\LARGE Operation:}{\LARGE \par}
1525 
\vspace{5mm}
1526 
\begin{quotation}
1527 
rA <- rB - exts(Immediate)
1528 
\end{quotation}
1529 
\vspace{10mm}
1530 
\textbf{\LARGE Notes:}{\LARGE \par}
1531 
\vspace{5mm}
1532 
\begin{quotation}
1533 
 
1534 
\end{quotation}
1535 
\vspace{10mm}
1536 
\vfill
1537 
Class 1:
1538 
{\centering \begin{tabular}{|c|c|c|}
1539 
\hline
1540 
Architecture Level&
1541 
Execution Mode&
1542 
Implementation\\
1543 
\hline
1544 
Core CPU&User and Supervisor&Mandatory always\\
1545 
\hline
1546 
\end{tabular}\par}
1547 
 
1548 
 
1549 
 
1550 
\newpage
1551 
\vspace{10mm}
1552 
\lyxline{\small}\vspace{-1\parskip}
1553 
\vspace{10mm}
1554 
{\raggedright \begin{tabular}{ccc}
1555 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1556 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1557 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1558 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1559 
\textbf{\huge l.muli32s}&
1560 
\multicolumn{1}{c}{\textbf{\huge Multiply Immediate Signed}}&
1561 
\textbf{\huge l.muli32s}\\
1562 
\end{tabular}\par}
1563 
\bigskip{}
1564 
 
1565 
\vspace{10mm}
1566 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
1567 
\hline
1568 
31&
1569 
&
1570 
&
1571 
&
1572 
&
1573 
&
1574 
&
1575 
24&
1576 
23&
1577 
&
1578 
&
1579 
20&
1580 
19&
1581 
&
1582 
&
1583 
16&
1584 
15&
1585 
&
1586 
&
1587 
&
1588 
&
1589 
&
1590 
&
1591 
&
1592 
&
1593 
&
1594 
&
1595 
&
1596 
&
1597 
&
1598 
&
1599 
0\\
1600 
\hline
1601 
\multicolumn{8}{|c|}{opcode 0x28}&
1602 
\multicolumn{4}{c|}{A}&
1603 
\multicolumn{4}{c|}{B}&
1604 
\multicolumn{16}{c|}{I}\\
1605 
 
1606 
\hline
1607 
\multicolumn{8}{|c|}{8 bits}&
1608 
\multicolumn{4}{c|}{4 bits}&
1609 
\multicolumn{4}{c|}{4 bits}&
1610 
\multicolumn{16}{c|}{16 bits}\\
1611 
 
1612 
\hline
1613 
\end{tabular}\par}
1614 
\vspace{15mm}
1615 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1616 
\vspace{5mm}
1617 
\begin{quotation}
1618 
\texttt{\large l.muli32s\ rA,rB,I}{\large \par}
1619 
\end{quotation}
1620 
\vspace{10mm}
1621 
\textbf{\LARGE Description:}{\LARGE \par}
1622 
\vspace{5mm}
1623 
\begin{quotation}
1624 
\texttt{\large Immediate and the contents of general register rB are multiplied and the result is truncated to 32 bits and placed into general register rA.}{\large \par}
1625 
\end{quotation}
1626 
\vspace{10mm}
1627 
\textbf{\LARGE Operation:}{\LARGE \par}
1628 
\vspace{5mm}
1629 
\begin{quotation}
1630 
rA <- rB * Immediate
1631 
\end{quotation}
1632 
\vspace{10mm}
1633 
\textbf{\LARGE Notes:}{\LARGE \par}
1634 
\vspace{5mm}
1635 
\begin{quotation}
1636 
 
1637 
\end{quotation}
1638 
\vspace{10mm}
1639 
\vfill
1640 
Class 2:
1641 
{\centering \begin{tabular}{|c|c|c|}
1642 
\hline
1643 
Architecture Level&
1644 
Execution Mode&
1645 
Implementation\\
1646 
\hline
1647 
Core CPU&User and Supervisor&Recommended\\
1648 
\hline
1649 
\end{tabular}\par}
1650 
 
1651 
 
1652 
 
1653 
\newpage
1654 
\vspace{10mm}
1655 
\lyxline{\small}\vspace{-1\parskip}
1656 
\vspace{10mm}
1657 
{\raggedright \begin{tabular}{ccc}
1658 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1659 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1660 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1661 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1662 
\textbf{\huge l.xori16}&
1663 
\multicolumn{1}{c}{\textbf{\huge Exclusive Or Immediate Half Word}}&
1664 
\textbf{\huge l.xori16}\\
1665 
\end{tabular}\par}
1666 
\bigskip{}
1667 
 
1668 
\vspace{10mm}
1669 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
1670 
\hline
1671 
31&
1672 
&
1673 
&
1674 
&
1675 
&
1676 
&
1677 
&
1678 
24&
1679 
23&
1680 
&
1681 
&
1682 
20&
1683 
19&
1684 
&
1685 
&
1686 
16&
1687 
15&
1688 
&
1689 
&
1690 
&
1691 
&
1692 
&
1693 
&
1694 
&
1695 
&
1696 
&
1697 
&
1698 
&
1699 
&
1700 
&
1701 
&
1702 
0\\
1703 
\hline
1704 
\multicolumn{8}{|c|}{opcode 0x29}&
1705 
\multicolumn{4}{c|}{A}&
1706 
\multicolumn{4}{c|}{B}&
1707 
\multicolumn{16}{c|}{I}\\
1708 
 
1709 
\hline
1710 
\multicolumn{8}{|c|}{8 bits}&
1711 
\multicolumn{4}{c|}{4 bits}&
1712 
\multicolumn{4}{c|}{4 bits}&
1713 
\multicolumn{16}{c|}{16 bits}\\
1714 
 
1715 
\hline
1716 
\end{tabular}\par}
1717 
\vspace{15mm}
1718 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1719 
\vspace{5mm}
1720 
\begin{quotation}
1721 
\texttt{\large l.xori16\ rA,rB,I}{\large \par}
1722 
\end{quotation}
1723 
\vspace{10mm}
1724 
\textbf{\LARGE Description:}{\LARGE \par}
1725 
\vspace{5mm}
1726 
\begin{quotation}
1727 
\texttt{\large Immediate is zero-extended and combined with the contents of general register rB in a bit-wise logical XOR operation. The result is placed into general register rA.}{\large \par}
1728 
\end{quotation}
1729 
\vspace{10mm}
1730 
\textbf{\LARGE Operation:}{\LARGE \par}
1731 
\vspace{5mm}
1732 
\begin{quotation}
1733 
rA <- rB XOR exts(Immediate)
1734 
\end{quotation}
1735 
\vspace{10mm}
1736 
\textbf{\LARGE Notes:}{\LARGE \par}
1737 
\vspace{5mm}
1738 
\begin{quotation}
1739 
 
1740 
\end{quotation}
1741 
\vspace{10mm}
1742 
\vfill
1743 
Class 3:
1744 
{\centering \begin{tabular}{|c|c|c|}
1745 
\hline
1746 
Architecture Level&
1747 
Execution Mode&
1748 
Implementation\\
1749 
\hline
1750 
Core CPU&User and Supervisor&Optional\\
1751 
\hline
1752 
\end{tabular}\par}
1753 
 
1754 
 
1755 
 
1756 
\newpage
1757 
\vspace{10mm}
1758 
\lyxline{\small}\vspace{-1\parskip}
1759 
\vspace{10mm}
1760 
{\raggedright \begin{tabular}{ccc}
1761 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1762 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1763 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1764 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1765 
\textbf{\huge l.immlo16u}&
1766 
\multicolumn{1}{c}{\textbf{\huge Immediate Low-Order Half Word Unsigned}}&
1767 
\textbf{\huge l.immlo16u}\\
1768 
\end{tabular}\par}
1769 
\bigskip{}
1770 
 
1771 
\vspace{10mm}
1772 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
1773 
\hline
1774 
31&
1775 
&
1776 
&
1777 
&
1778 
&
1779 
&
1780 
&
1781 
24&
1782 
23&
1783 
&
1784 
&
1785 
20&
1786 
19&
1787 
&
1788 
&
1789 
16&
1790 
15&
1791 
&
1792 
&
1793 
&
1794 
&
1795 
&
1796 
&
1797 
&
1798 
&
1799 
&
1800 
&
1801 
&
1802 
&
1803 
&
1804 
&
1805 
0\\
1806 
\hline
1807 
\multicolumn{8}{|c|}{opcode 0x2a}&
1808 
\multicolumn{4}{c|}{A}&
1809 
\multicolumn{4}{c|}{reserved}&
1810 
\multicolumn{16}{c|}{I}\\
1811 
 
1812 
\hline
1813 
\multicolumn{8}{|c|}{8 bits}&
1814 
\multicolumn{4}{c|}{4 bits}&
1815 
\multicolumn{4}{c|}{4 bits}&
1816 
\multicolumn{16}{c|}{16 bits}\\
1817 
 
1818 
\hline
1819 
\end{tabular}\par}
1820 
\vspace{15mm}
1821 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1822 
\vspace{5mm}
1823 
\begin{quotation}
1824 
\texttt{\large l.immlo16u\ rA,I}{\large \par}
1825 
\end{quotation}
1826 
\vspace{10mm}
1827 
\textbf{\LARGE Description:}{\LARGE \par}
1828 
\vspace{5mm}
1829 
\begin{quotation}
1830 
\texttt{\large 16 bit immediate is placed into low-order 16 bits of general register rA.}{\large \par}
1831 
\end{quotation}
1832 
\vspace{10mm}
1833 
\textbf{\LARGE Operation:}{\LARGE \par}
1834 
\vspace{5mm}
1835 
\begin{quotation}
1836 
rA{[}15:0{]} <- Immediate
1837 
\end{quotation}
1838 
\vspace{10mm}
1839 
\textbf{\LARGE Notes:}{\LARGE \par}
1840 
\vspace{5mm}
1841 
\begin{quotation}
1842 
 
1843 
\end{quotation}
1844 
\vspace{10mm}
1845 
\vfill
1846 
Class 1:
1847 
{\centering \begin{tabular}{|c|c|c|}
1848 
\hline
1849 
Architecture Level&
1850 
Execution Mode&
1851 
Implementation\\
1852 
\hline
1853 
Core CPU&User and Supervisor&Mandatory always\\
1854 
\hline
1855 
\end{tabular}\par}
1856 
 
1857 
 
1858 
 
1859 
\newpage
1860 
\vspace{10mm}
1861 
\lyxline{\small}\vspace{-1\parskip}
1862 
\vspace{10mm}
1863 
{\raggedright \begin{tabular}{ccc}
1864 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1865 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1866 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1867 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1868 
\textbf{\huge l.immhi16u}&
1869 
\multicolumn{1}{c}{\textbf{\huge Immediate High-Order Half Word Unsigned}}&
1870 
\textbf{\huge l.immhi16u}\\
1871 
\end{tabular}\par}
1872 
\bigskip{}
1873 
 
1874 
\vspace{10mm}
1875 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
1876 
\hline
1877 
31&
1878 
&
1879 
&
1880 
&
1881 
&
1882 
&
1883 
&
1884 
24&
1885 
23&
1886 
&
1887 
&
1888 
20&
1889 
19&
1890 
&
1891 
&
1892 
16&
1893 
15&
1894 
&
1895 
&
1896 
&
1897 
&
1898 
&
1899 
&
1900 
&
1901 
&
1902 
&
1903 
&
1904 
&
1905 
&
1906 
&
1907 
&
1908 
0\\
1909 
\hline
1910 
\multicolumn{8}{|c|}{opcode 0x2b}&
1911 
\multicolumn{4}{c|}{A}&
1912 
\multicolumn{4}{c|}{reserved}&
1913 
\multicolumn{16}{c|}{I}\\
1914 
 
1915 
\hline
1916 
\multicolumn{8}{|c|}{8 bits}&
1917 
\multicolumn{4}{c|}{4 bits}&
1918 
\multicolumn{4}{c|}{4 bits}&
1919 
\multicolumn{16}{c|}{16 bits}\\
1920 
 
1921 
\hline
1922 
\end{tabular}\par}
1923 
\vspace{15mm}
1924 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1925 
\vspace{5mm}
1926 
\begin{quotation}
1927 
\texttt{\large l.immhi16u\ rA,I}{\large \par}
1928 
\end{quotation}
1929 
\vspace{10mm}
1930 
\textbf{\LARGE Description:}{\LARGE \par}
1931 
\vspace{5mm}
1932 
\begin{quotation}
1933 
\texttt{\large 16 bit immediate is placed into high-order 16 bits of general register rA.}{\large \par}
1934 
\end{quotation}
1935 
\vspace{10mm}
1936 
\textbf{\LARGE Operation:}{\LARGE \par}
1937 
\vspace{5mm}
1938 
\begin{quotation}
1939 
rA{[}31:16{]} <- Immediate
1940 
\end{quotation}
1941 
\vspace{10mm}
1942 
\textbf{\LARGE Notes:}{\LARGE \par}
1943 
\vspace{5mm}
1944 
\begin{quotation}
1945 
 
1946 
\end{quotation}
1947 
\vspace{10mm}
1948 
\vfill
1949 
Class 1:
1950 
{\centering \begin{tabular}{|c|c|c|}
1951 
\hline
1952 
Architecture Level&
1953 
Execution Mode&
1954 
Implementation\\
1955 
\hline
1956 
Core CPU&User and Supervisor&Mandatory always\\
1957 
\hline
1958 
\end{tabular}\par}
1959 
 
1960 
 
1961 
 
1962 
\newpage
1963 
\vspace{10mm}
1964 
\lyxline{\small}\vspace{-1\parskip}
1965 
\vspace{10mm}
1966 
{\raggedright \begin{tabular}{ccc}
1967 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1968 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1969 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1970 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1971 
\textbf{\huge l.sub32s}&
1972 
\multicolumn{1}{c}{\textbf{\huge Subtract Signed}}&
1973 
\textbf{\huge l.sub32s}\\
1974 
\end{tabular}\par}
1975 
\bigskip{}
1976 
 
1977 
\vspace{10mm}
1978 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
1979 
\hline
1980 
31&
1981 
&
1982 
&
1983 
&
1984 
&
1985 
&
1986 
&
1987 
24&
1988 
23&
1989 
&
1990 
&
1991 
20&
1992 
19&
1993 
&
1994 
&
1995 
16&
1996 
15&
1997 
&
1998 
&
1999 
12&
2000 
11&
2001 
&
2002 
&
2003 
8&
2004 
7&
2005 
&
2006 
&
2007 
&
2008 
&
2009 
&
2010 
&
2011 
0\\
2012 
\hline
2013 
\multicolumn{8}{|c|}{opcode 0x2c}&
2014 
\multicolumn{4}{c|}{A}&
2015 
\multicolumn{4}{c|}{B}&
2016 
\multicolumn{4}{c|}{C}&
2017 
\multicolumn{4}{c|}{opcode 0x0}&
2018 
\multicolumn{8}{c|}{reserved}\\
2019 
 
2020 
\hline
2021 
\multicolumn{8}{|c|}{8 bits}&
2022 
\multicolumn{4}{c|}{4 bits}&
2023 
\multicolumn{4}{c|}{4 bits}&
2024 
\multicolumn{4}{c|}{4 bits}&
2025 
\multicolumn{4}{c|}{4 bits}&
2026 
\multicolumn{8}{c|}{8 bits}\\
2027 
 
2028 
\hline
2029 
\end{tabular}\par}
2030 
\vspace{15mm}
2031 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2032 
\vspace{5mm}
2033 
\begin{quotation}
2034 
\texttt{\large l.sub32s\ rA,rB,rC}{\large \par}
2035 
\end{quotation}
2036 
\vspace{10mm}
2037 
\textbf{\LARGE Description:}{\LARGE \par}
2038 
\vspace{5mm}
2039 
\begin{quotation}
2040 
\texttt{\large The contents of general register rC is subtracted from the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
2041 
\end{quotation}
2042 
\vspace{10mm}
2043 
\textbf{\LARGE Operation:}{\LARGE \par}
2044 
\vspace{5mm}
2045 
\begin{quotation}
2046 
rA <- rB - rC
2047 
\end{quotation}
2048 
\vspace{10mm}
2049 
\textbf{\LARGE Notes:}{\LARGE \par}
2050 
\vspace{5mm}
2051 
\begin{quotation}
2052 
 
2053 
\end{quotation}
2054 
\vspace{10mm}
2055 
\vfill
2056 
Class 1:
2057 
{\centering \begin{tabular}{|c|c|c|}
2058 
\hline
2059 
Architecture Level&
2060 
Execution Mode&
2061 
Implementation\\
2062 
\hline
2063 
Core CPU&User and Supervisor&Mandatory always\\
2064 
\hline
2065 
\end{tabular}\par}
2066 
 
2067 
 
2068 
 
2069 
\newpage
2070 
\vspace{10mm}
2071 
\lyxline{\small}\vspace{-1\parskip}
2072 
\vspace{10mm}
2073 
{\raggedright \begin{tabular}{ccc}
2074 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2075 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2076 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2077 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2078 
\textbf{\huge l.shla32}&
2079 
\multicolumn{1}{c}{\textbf{\huge Shift Left Arithmetic}}&
2080 
\textbf{\huge l.shla32}\\
2081 
\end{tabular}\par}
2082 
\bigskip{}
2083 
 
2084 
\vspace{10mm}
2085 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
2086 
\hline
2087 
31&
2088 
&
2089 
&
2090 
&
2091 
&
2092 
&
2093 
&
2094 
24&
2095 
23&
2096 
&
2097 
&
2098 
20&
2099 
19&
2100 
&
2101 
&
2102 
16&
2103 
15&
2104 
&
2105 
&
2106 
12&
2107 
11&
2108 
&
2109 
&
2110 
8&
2111 
7&
2112 
&
2113 
&
2114 
&
2115 
3&
2116 
2&
2117 
&
2118 
0\\
2119 
\hline
2120 
\multicolumn{8}{|c|}{opcode 0x2c}&
2121 
\multicolumn{4}{c|}{A}&
2122 
\multicolumn{4}{c|}{B}&
2123 
\multicolumn{4}{c|}{C}&
2124 
\multicolumn{4}{c|}{opcode 0x1}&
2125 
\multicolumn{5}{c|}{L}&
2126 
\multicolumn{3}{c|}{reserved}\\
2127 
 
2128 
\hline
2129 
\multicolumn{8}{|c|}{8 bits}&
2130 
\multicolumn{4}{c|}{4 bits}&
2131 
\multicolumn{4}{c|}{4 bits}&
2132 
\multicolumn{4}{c|}{4 bits}&
2133 
\multicolumn{4}{c|}{4 bits}&
2134 
\multicolumn{5}{c|}{5 bits}&
2135 
\multicolumn{3}{c|}{3 bits}\\
2136 
 
2137 
\hline
2138 
\end{tabular}\par}
2139 
\vspace{15mm}
2140 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2141 
\vspace{5mm}
2142 
\begin{quotation}
2143 
\texttt{\large l.shla32\ rA,rB,rC,L}{\large \par}
2144 
\end{quotation}
2145 
\vspace{10mm}
2146 
\textbf{\LARGE Description:}{\LARGE \par}
2147 
\vspace{5mm}
2148 
\begin{quotation}
2149 
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted left, inserting zeros into the low-order bits.}{\large \par}
2150 
\end{quotation}
2151 
\vspace{10mm}
2152 
\textbf{\LARGE Operation:}{\LARGE \par}
2153 
\vspace{5mm}
2154 
\begin{quotation}
2155 
b <- Immediate | rC\\rA{[}31:b{]} <- rB{[}31-b:0{]}\\rA{[}b:0{]} <- 0
2156 
\end{quotation}
2157 
\vspace{10mm}
2158 
\textbf{\LARGE Notes:}{\LARGE \par}
2159 
\vspace{5mm}
2160 
\begin{quotation}
2161 
 
2162 
\end{quotation}
2163 
\vspace{10mm}
2164 
\vfill
2165 
Class 1:
2166 
{\centering \begin{tabular}{|c|c|c|}
2167 
\hline
2168 
Architecture Level&
2169 
Execution Mode&
2170 
Implementation\\
2171 
\hline
2172 
Core CPU&User and Supervisor&Mandatory always\\
2173 
\hline
2174 
\end{tabular}\par}
2175 
 
2176 
 
2177 
 
2178 
\newpage
2179 
\vspace{10mm}
2180 
\lyxline{\small}\vspace{-1\parskip}
2181 
\vspace{10mm}
2182 
{\raggedright \begin{tabular}{ccc}
2183 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2184 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2185 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2186 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2187 
\textbf{\huge l.shra32}&
2188 
\multicolumn{1}{c}{\textbf{\huge Shift Right Arithmetic}}&
2189 
\textbf{\huge l.shra32}\\
2190 
\end{tabular}\par}
2191 
\bigskip{}
2192 
 
2193 
\vspace{10mm}
2194 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
2195 
\hline
2196 
31&
2197 
&
2198 
&
2199 
&
2200 
&
2201 
&
2202 
&
2203 
24&
2204 
23&
2205 
&
2206 
&
2207 
20&
2208 
19&
2209 
&
2210 
&
2211 
16&
2212 
15&
2213 
&
2214 
&
2215 
12&
2216 
11&
2217 
&
2218 
&
2219 
8&
2220 
7&
2221 
&
2222 
&
2223 
&
2224 
3&
2225 
2&
2226 
&
2227 
0\\
2228 
\hline
2229 
\multicolumn{8}{|c|}{opcode 0x2c}&
2230 
\multicolumn{4}{c|}{A}&
2231 
\multicolumn{4}{c|}{B}&
2232 
\multicolumn{4}{c|}{C}&
2233 
\multicolumn{4}{c|}{opcode 0x2}&
2234 
\multicolumn{5}{c|}{L}&
2235 
\multicolumn{3}{c|}{reserved}\\
2236 
 
2237 
\hline
2238 
\multicolumn{8}{|c|}{8 bits}&
2239 
\multicolumn{4}{c|}{4 bits}&
2240 
\multicolumn{4}{c|}{4 bits}&
2241 
\multicolumn{4}{c|}{4 bits}&
2242 
\multicolumn{4}{c|}{4 bits}&
2243 
\multicolumn{5}{c|}{5 bits}&
2244 
\multicolumn{3}{c|}{3 bits}\\
2245 
 
2246 
\hline
2247 
\end{tabular}\par}
2248 
\vspace{15mm}
2249 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2250 
\vspace{5mm}
2251 
\begin{quotation}
2252 
\texttt{\large l.shra32\ rA,rB,rC,L}{\large \par}
2253 
\end{quotation}
2254 
\vspace{10mm}
2255 
\textbf{\LARGE Description:}{\LARGE \par}
2256 
\vspace{5mm}
2257 
\begin{quotation}
2258 
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted right, sign-extending the high-order bits.}{\large \par}
2259 
\end{quotation}
2260 
\vspace{10mm}
2261 
\textbf{\LARGE Operation:}{\LARGE \par}
2262 
\vspace{5mm}
2263 
\begin{quotation}
2264 
b <- Immediate | rC\\rA{[}31-b:0{]} <- rB{[}31:b{]}\\rA{[}31-b:31{]} <- rB{[}31{]}
2265 
\end{quotation}
2266 
\vspace{10mm}
2267 
\textbf{\LARGE Notes:}{\LARGE \par}
2268 
\vspace{5mm}
2269 
\begin{quotation}
2270 
 
2271 
\end{quotation}
2272 
\vspace{10mm}
2273 
\vfill
2274 
Class 1:
2275 
{\centering \begin{tabular}{|c|c|c|}
2276 
\hline
2277 
Architecture Level&
2278 
Execution Mode&
2279 
Implementation\\
2280 
\hline
2281 
Core CPU&User and Supervisor&Mandatory always\\
2282 
\hline
2283 
\end{tabular}\par}
2284 
 
2285 
 
2286 
 
2287 
\newpage
2288 
\vspace{10mm}
2289 
\lyxline{\small}\vspace{-1\parskip}
2290 
\vspace{10mm}
2291 
{\raggedright \begin{tabular}{ccc}
2292 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2293 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2294 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2295 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2296 
\textbf{\huge l.shrl32}&
2297 
\multicolumn{1}{c}{\textbf{\huge Shift Right Logical}}&
2298 
\textbf{\huge l.shrl32}\\
2299 
\end{tabular}\par}
2300 
\bigskip{}
2301 
 
2302 
\vspace{10mm}
2303 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
2304 
\hline
2305 
31&
2306 
&
2307 
&
2308 
&
2309 
&
2310 
&
2311 
&
2312 
24&
2313 
23&
2314 
&
2315 
&
2316 
20&
2317 
19&
2318 
&
2319 
&
2320 
16&
2321 
15&
2322 
&
2323 
&
2324 
12&
2325 
11&
2326 
&
2327 
&
2328 
8&
2329 
7&
2330 
&
2331 
&
2332 
&
2333 
3&
2334 
2&
2335 
&
2336 
0\\
2337 
\hline
2338 
\multicolumn{8}{|c|}{opcode 0x2c}&
2339 
\multicolumn{4}{c|}{A}&
2340 
\multicolumn{4}{c|}{B}&
2341 
\multicolumn{4}{c|}{C}&
2342 
\multicolumn{4}{c|}{opcode 0x3}&
2343 
\multicolumn{5}{c|}{L}&
2344 
\multicolumn{3}{c|}{reserved}\\
2345 
 
2346 
\hline
2347 
\multicolumn{8}{|c|}{8 bits}&
2348 
\multicolumn{4}{c|}{4 bits}&
2349 
\multicolumn{4}{c|}{4 bits}&
2350 
\multicolumn{4}{c|}{4 bits}&
2351 
\multicolumn{4}{c|}{4 bits}&
2352 
\multicolumn{5}{c|}{5 bits}&
2353 
\multicolumn{3}{c|}{3 bits}\\
2354 
 
2355 
\hline
2356 
\end{tabular}\par}
2357 
\vspace{15mm}
2358 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2359 
\vspace{5mm}
2360 
\begin{quotation}
2361 
\texttt{\large l.shrl32\ rA,rB,rC,L}{\large \par}
2362 
\end{quotation}
2363 
\vspace{10mm}
2364 
\textbf{\LARGE Description:}{\LARGE \par}
2365 
\vspace{5mm}
2366 
\begin{quotation}
2367 
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted right, inserting zeros into the high-order bits.}{\large \par}
2368 
\end{quotation}
2369 
\vspace{10mm}
2370 
\textbf{\LARGE Operation:}{\LARGE \par}
2371 
\vspace{5mm}
2372 
\begin{quotation}
2373 
b <- Immediate | rC\\rA{[}31-b:0{]} <- rB{[}31:b{]}\\rA{[}31-b:31{]} <- 0
2374 
\end{quotation}
2375 
\vspace{10mm}
2376 
\textbf{\LARGE Notes:}{\LARGE \par}
2377 
\vspace{5mm}
2378 
\begin{quotation}
2379 
 
2380 
\end{quotation}
2381 
\vspace{10mm}
2382 
\vfill
2383 
Class 1:
2384 
{\centering \begin{tabular}{|c|c|c|}
2385 
\hline
2386 
Architecture Level&
2387 
Execution Mode&
2388 
Implementation\\
2389 
\hline
2390 
Core CPU&User and Supervisor&Mandatory always\\
2391 
\hline
2392 
\end{tabular}\par}
2393 
 
2394 
 
2395 
 
2396 
\newpage
2397 
\vspace{10mm}
2398 
\lyxline{\small}\vspace{-1\parskip}
2399 
\vspace{10mm}
2400 
{\raggedright \begin{tabular}{ccc}
2401 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2402 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2403 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2404 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2405 
\textbf{\huge l.and32}&
2406 
\multicolumn{1}{c}{\textbf{\huge And}}&
2407 
\textbf{\huge l.and32}\\
2408 
\end{tabular}\par}
2409 
\bigskip{}
2410 
 
2411 
\vspace{10mm}
2412 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2413 
\hline
2414 
31&
2415 
&
2416 
&
2417 
&
2418 
&
2419 
&
2420 
&
2421 
24&
2422 
23&
2423 
&
2424 
&
2425 
20&
2426 
19&
2427 
&
2428 
&
2429 
16&
2430 
15&
2431 
&
2432 
&
2433 
12&
2434 
11&
2435 
&
2436 
&
2437 
8&
2438 
7&
2439 
&
2440 
&
2441 
&
2442 
&
2443 
&
2444 
&
2445 
0\\
2446 
\hline
2447 
\multicolumn{8}{|c|}{opcode 0x2c}&
2448 
\multicolumn{4}{c|}{A}&
2449 
\multicolumn{4}{c|}{B}&
2450 
\multicolumn{4}{c|}{C}&
2451 
\multicolumn{4}{c|}{opcode 0x4}&
2452 
\multicolumn{8}{c|}{reserved}\\
2453 
 
2454 
\hline
2455 
\multicolumn{8}{|c|}{8 bits}&
2456 
\multicolumn{4}{c|}{4 bits}&
2457 
\multicolumn{4}{c|}{4 bits}&
2458 
\multicolumn{4}{c|}{4 bits}&
2459 
\multicolumn{4}{c|}{4 bits}&
2460 
\multicolumn{8}{c|}{8 bits}\\
2461 
 
2462 
\hline
2463 
\end{tabular}\par}
2464 
\vspace{15mm}
2465 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2466 
\vspace{5mm}
2467 
\begin{quotation}
2468 
\texttt{\large l.and32\ rA,rB,rC}{\large \par}
2469 
\end{quotation}
2470 
\vspace{10mm}
2471 
\textbf{\LARGE Description:}{\LARGE \par}
2472 
\vspace{5mm}
2473 
\begin{quotation}
2474 
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical AND operation. The result is placed into general register rA.}{\large \par}
2475 
\end{quotation}
2476 
\vspace{10mm}
2477 
\textbf{\LARGE Operation:}{\LARGE \par}
2478 
\vspace{5mm}
2479 
\begin{quotation}
2480 
rA <- rB AND rC
2481 
\end{quotation}
2482 
\vspace{10mm}
2483 
\textbf{\LARGE Notes:}{\LARGE \par}
2484 
\vspace{5mm}
2485 
\begin{quotation}
2486 
 
2487 
\end{quotation}
2488 
\vspace{10mm}
2489 
\vfill
2490 
Class 1:
2491 
{\centering \begin{tabular}{|c|c|c|}
2492 
\hline
2493 
Architecture Level&
2494 
Execution Mode&
2495 
Implementation\\
2496 
\hline
2497 
Core CPU&User and Supervisor&Mandatory always\\
2498 
\hline
2499 
\end{tabular}\par}
2500 
 
2501 
 
2502 
 
2503 
\newpage
2504 
\vspace{10mm}
2505 
\lyxline{\small}\vspace{-1\parskip}
2506 
\vspace{10mm}
2507 
{\raggedright \begin{tabular}{ccc}
2508 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2509 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2510 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2511 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2512 
\textbf{\huge l.or32}&
2513 
\multicolumn{1}{c}{\textbf{\huge Or}}&
2514 
\textbf{\huge l.or32}\\
2515 
\end{tabular}\par}
2516 
\bigskip{}
2517 
 
2518 
\vspace{10mm}
2519 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2520 
\hline
2521 
31&
2522 
&
2523 
&
2524 
&
2525 
&
2526 
&
2527 
&
2528 
24&
2529 
23&
2530 
&
2531 
&
2532 
20&
2533 
19&
2534 
&
2535 
&
2536 
16&
2537 
15&
2538 
&
2539 
&
2540 
12&
2541 
11&
2542 
&
2543 
&
2544 
8&
2545 
7&
2546 
&
2547 
&
2548 
&
2549 
&
2550 
&
2551 
&
2552 
0\\
2553 
\hline
2554 
\multicolumn{8}{|c|}{opcode 0x2c}&
2555 
\multicolumn{4}{c|}{A}&
2556 
\multicolumn{4}{c|}{B}&
2557 
\multicolumn{4}{c|}{C}&
2558 
\multicolumn{4}{c|}{opcode 0x5}&
2559 
\multicolumn{8}{c|}{reserved}\\
2560 
 
2561 
\hline
2562 
\multicolumn{8}{|c|}{8 bits}&
2563 
\multicolumn{4}{c|}{4 bits}&
2564 
\multicolumn{4}{c|}{4 bits}&
2565 
\multicolumn{4}{c|}{4 bits}&
2566 
\multicolumn{4}{c|}{4 bits}&
2567 
\multicolumn{8}{c|}{8 bits}\\
2568 
 
2569 
\hline
2570 
\end{tabular}\par}
2571 
\vspace{15mm}
2572 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2573 
\vspace{5mm}
2574 
\begin{quotation}
2575 
\texttt{\large l.or32\ rA,rB,rC}{\large \par}
2576 
\end{quotation}
2577 
\vspace{10mm}
2578 
\textbf{\LARGE Description:}{\LARGE \par}
2579 
\vspace{5mm}
2580 
\begin{quotation}
2581 
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical OR operation. The result is placed into general register rA.}{\large \par}
2582 
\end{quotation}
2583 
\vspace{10mm}
2584 
\textbf{\LARGE Operation:}{\LARGE \par}
2585 
\vspace{5mm}
2586 
\begin{quotation}
2587 
rA <- rB OR rC
2588 
\end{quotation}
2589 
\vspace{10mm}
2590 
\textbf{\LARGE Notes:}{\LARGE \par}
2591 
\vspace{5mm}
2592 
\begin{quotation}
2593 
 
2594 
\end{quotation}
2595 
\vspace{10mm}
2596 
\vfill
2597 
Class 1:
2598 
{\centering \begin{tabular}{|c|c|c|}
2599 
\hline
2600 
Architecture Level&
2601 
Execution Mode&
2602 
Implementation\\
2603 
\hline
2604 
Core CPU&User and Supervisor&Mandatory always\\
2605 
\hline
2606 
\end{tabular}\par}
2607 
 
2608 
 
2609 
 
2610 
\newpage
2611 
\vspace{10mm}
2612 
\lyxline{\small}\vspace{-1\parskip}
2613 
\vspace{10mm}
2614 
{\raggedright \begin{tabular}{ccc}
2615 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2616 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2617 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2618 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2619 
\textbf{\huge l.xor32}&
2620 
\multicolumn{1}{c}{\textbf{\huge Exclusive Or}}&
2621 
\textbf{\huge l.xor32}\\
2622 
\end{tabular}\par}
2623 
\bigskip{}
2624 
 
2625 
\vspace{10mm}
2626 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2627 
\hline
2628 
31&
2629 
&
2630 
&
2631 
&
2632 
&
2633 
&
2634 
&
2635 
24&
2636 
23&
2637 
&
2638 
&
2639 
20&
2640 
19&
2641 
&
2642 
&
2643 
16&
2644 
15&
2645 
&
2646 
&
2647 
12&
2648 
11&
2649 
&
2650 
&
2651 
8&
2652 
7&
2653 
&
2654 
&
2655 
&
2656 
&
2657 
&
2658 
&
2659 
0\\
2660 
\hline
2661 
\multicolumn{8}{|c|}{opcode 0x2c}&
2662 
\multicolumn{4}{c|}{A}&
2663 
\multicolumn{4}{c|}{B}&
2664 
\multicolumn{4}{c|}{C}&
2665 
\multicolumn{4}{c|}{opcode 0x6}&
2666 
\multicolumn{8}{c|}{reserved}\\
2667 
 
2668 
\hline
2669 
\multicolumn{8}{|c|}{8 bits}&
2670 
\multicolumn{4}{c|}{4 bits}&
2671 
\multicolumn{4}{c|}{4 bits}&
2672 
\multicolumn{4}{c|}{4 bits}&
2673 
\multicolumn{4}{c|}{4 bits}&
2674 
\multicolumn{8}{c|}{8 bits}\\
2675 
 
2676 
\hline
2677 
\end{tabular}\par}
2678 
\vspace{15mm}
2679 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2680 
\vspace{5mm}
2681 
\begin{quotation}
2682 
\texttt{\large l.xor32\ rA,rB,rC}{\large \par}
2683 
\end{quotation}
2684 
\vspace{10mm}
2685 
\textbf{\LARGE Description:}{\LARGE \par}
2686 
\vspace{5mm}
2687 
\begin{quotation}
2688 
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical XOR operation. The result is placed into general register rA.}{\large \par}
2689 
\end{quotation}
2690 
\vspace{10mm}
2691 
\textbf{\LARGE Operation:}{\LARGE \par}
2692 
\vspace{5mm}
2693 
\begin{quotation}
2694 
rA <- rB XOR rC
2695 
\end{quotation}
2696 
\vspace{10mm}
2697 
\textbf{\LARGE Notes:}{\LARGE \par}
2698 
\vspace{5mm}
2699 
\begin{quotation}
2700 
 
2701 
\end{quotation}
2702 
\vspace{10mm}
2703 
\vfill
2704 
Class 1:
2705 
{\centering \begin{tabular}{|c|c|c|}
2706 
\hline
2707 
Architecture Level&
2708 
Execution Mode&
2709 
Implementation\\
2710 
\hline
2711 
Core CPU&User and Supervisor&Mandatory always\\
2712 
\hline
2713 
\end{tabular}\par}
2714 
 
2715 
 
2716 
 
2717 
\newpage
2718 
\vspace{10mm}
2719 
\lyxline{\small}\vspace{-1\parskip}
2720 
\vspace{10mm}
2721 
{\raggedright \begin{tabular}{ccc}
2722 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2723 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2724 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2725 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2726 
\textbf{\huge l.mul32s}&
2727 
\multicolumn{1}{c}{\textbf{\huge Multiply Signed}}&
2728 
\textbf{\huge l.mul32s}\\
2729 
\end{tabular}\par}
2730 
\bigskip{}
2731 
 
2732 
\vspace{10mm}
2733 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2734 
\hline
2735 
31&
2736 
&
2737 
&
2738 
&
2739 
&
2740 
&
2741 
&
2742 
24&
2743 
23&
2744 
&
2745 
&
2746 
20&
2747 
19&
2748 
&
2749 
&
2750 
16&
2751 
15&
2752 
&
2753 
&
2754 
12&
2755 
11&
2756 
&
2757 
&
2758 
8&
2759 
7&
2760 
&
2761 
&
2762 
&
2763 
&
2764 
&
2765 
&
2766 
0\\
2767 
\hline
2768 
\multicolumn{8}{|c|}{opcode 0x2c}&
2769 
\multicolumn{4}{c|}{A}&
2770 
\multicolumn{4}{c|}{B}&
2771 
\multicolumn{4}{c|}{C}&
2772 
\multicolumn{4}{c|}{opcode 0x7}&
2773 
\multicolumn{8}{c|}{reserved}\\
2774 
 
2775 
\hline
2776 
\multicolumn{8}{|c|}{8 bits}&
2777 
\multicolumn{4}{c|}{4 bits}&
2778 
\multicolumn{4}{c|}{4 bits}&
2779 
\multicolumn{4}{c|}{4 bits}&
2780 
\multicolumn{4}{c|}{4 bits}&
2781 
\multicolumn{8}{c|}{8 bits}\\
2782 
 
2783 
\hline
2784 
\end{tabular}\par}
2785 
\vspace{15mm}
2786 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2787 
\vspace{5mm}
2788 
\begin{quotation}
2789 
\texttt{\large l.mul32s\ rA,rB,rC}{\large \par}
2790 
\end{quotation}
2791 
\vspace{10mm}
2792 
\textbf{\LARGE Description:}{\LARGE \par}
2793 
\vspace{5mm}
2794 
\begin{quotation}
2795 
\texttt{\large The contents of general register rB and the contents of general register rC are multiplied and the result is truncated to 32 bits and placed into general register rA. Both operands are treated as unsigned integers.}{\large \par}
2796 
\end{quotation}
2797 
\vspace{10mm}
2798 
\textbf{\LARGE Operation:}{\LARGE \par}
2799 
\vspace{5mm}
2800 
\begin{quotation}
2801 
rA <- rB * rC
2802 
\end{quotation}
2803 
\vspace{10mm}
2804 
\textbf{\LARGE Notes:}{\LARGE \par}
2805 
\vspace{5mm}
2806 
\begin{quotation}
2807 
 
2808 
\end{quotation}
2809 
\vspace{10mm}
2810 
\vfill
2811 
Class 2:
2812 
{\centering \begin{tabular}{|c|c|c|}
2813 
\hline
2814 
Architecture Level&
2815 
Execution Mode&
2816 
Implementation\\
2817 
\hline
2818 
Core CPU&User and Supervisor&Recommended\\
2819 
\hline
2820 
\end{tabular}\par}
2821 
 
2822 
 
2823 
 
2824 
\newpage
2825 
\vspace{10mm}
2826 
\lyxline{\small}\vspace{-1\parskip}
2827 
\vspace{10mm}
2828 
{\raggedright \begin{tabular}{ccc}
2829 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2830 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2831 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2832 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2833 
\textbf{\huge l.mul32u}&
2834 
\multicolumn{1}{c}{\textbf{\huge Multiply Unsigned}}&
2835 
\textbf{\huge l.mul32u}\\
2836 
\end{tabular}\par}
2837 
\bigskip{}
2838 
 
2839 
\vspace{10mm}
2840 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2841 
\hline
2842 
31&
2843 
&
2844 
&
2845 
&
2846 
&
2847 
&
2848 
&
2849 
24&
2850 
23&
2851 
&
2852 
&
2853 
20&
2854 
19&
2855 
&
2856 
&
2857 
16&
2858 
15&
2859 
&
2860 
&
2861 
12&
2862 
11&
2863 
&
2864 
&
2865 
8&
2866 
7&
2867 
&
2868 
&
2869 
&
2870 
&
2871 
&
2872 
&
2873 
0\\
2874 
\hline
2875 
\multicolumn{8}{|c|}{opcode 0x2c}&
2876 
\multicolumn{4}{c|}{A}&
2877 
\multicolumn{4}{c|}{B}&
2878 
\multicolumn{4}{c|}{C}&
2879 
\multicolumn{4}{c|}{opcode 0x8}&
2880 
\multicolumn{8}{c|}{reserved}\\
2881 
 
2882 
\hline
2883 
\multicolumn{8}{|c|}{8 bits}&
2884 
\multicolumn{4}{c|}{4 bits}&
2885 
\multicolumn{4}{c|}{4 bits}&
2886 
\multicolumn{4}{c|}{4 bits}&
2887 
\multicolumn{4}{c|}{4 bits}&
2888 
\multicolumn{8}{c|}{8 bits}\\
2889 
 
2890 
\hline
2891 
\end{tabular}\par}
2892 
\vspace{15mm}
2893 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2894 
\vspace{5mm}
2895 
\begin{quotation}
2896 
\texttt{\large l.mul32u\ rA,rB,rC}{\large \par}
2897 
\end{quotation}
2898 
\vspace{10mm}
2899 
\textbf{\LARGE Description:}{\LARGE \par}
2900 
\vspace{5mm}
2901 
\begin{quotation}
2902 
\texttt{\large The contents of general register rB and the contents of general register rC are multiplied and the result is truncated to 32 bits and placed into general register rA. Both operands are treated as unsigned integers.}{\large \par}
2903 
\end{quotation}
2904 
\vspace{10mm}
2905 
\textbf{\LARGE Operation:}{\LARGE \par}
2906 
\vspace{5mm}
2907 
\begin{quotation}
2908 
rA <- rB * rC
2909 
\end{quotation}
2910 
\vspace{10mm}
2911 
\textbf{\LARGE Notes:}{\LARGE \par}
2912 
\vspace{5mm}
2913 
\begin{quotation}
2914 
 
2915 
\end{quotation}
2916 
\vspace{10mm}
2917 
\vfill
2918 
Class 2:
2919 
{\centering \begin{tabular}{|c|c|c|}
2920 
\hline
2921 
Architecture Level&
2922 
Execution Mode&
2923 
Implementation\\
2924 
\hline
2925 
Core CPU&User and Supervisor&Recommended\\
2926 
\hline
2927 
\end{tabular}\par}
2928 
 
2929 
 
2930 
 
2931 
\newpage
2932 
\vspace{10mm}
2933 
\lyxline{\small}\vspace{-1\parskip}
2934 
\vspace{10mm}
2935 
{\raggedright \begin{tabular}{ccc}
2936 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2937 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2938 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2939 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2940 
\textbf{\huge l.div32s}&
2941 
\multicolumn{1}{c}{\textbf{\huge Divide Signed}}&
2942 
\textbf{\huge l.div32s}\\
2943 
\end{tabular}\par}
2944 
\bigskip{}
2945 
 
2946 
\vspace{10mm}
2947 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2948 
\hline
2949 
31&
2950 
&
2951 
&
2952 
&
2953 
&
2954 
&
2955 
&
2956 
24&
2957 
23&
2958 
&
2959 
&
2960 
20&
2961 
19&
2962 
&
2963 
&
2964 
16&
2965 
15&
2966 
&
2967 
&
2968 
12&
2969 
11&
2970 
&
2971 
&
2972 
8&
2973 
7&
2974 
&
2975 
&
2976 
&
2977 
&
2978 
&
2979 
&
2980 
0\\
2981 
\hline
2982 
\multicolumn{8}{|c|}{opcode 0x2c}&
2983 
\multicolumn{4}{c|}{A}&
2984 
\multicolumn{4}{c|}{B}&
2985 
\multicolumn{4}{c|}{C}&
2986 
\multicolumn{4}{c|}{opcode 0x9}&
2987 
\multicolumn{8}{c|}{reserved}\\
2988 
 
2989 
\hline
2990 
\multicolumn{8}{|c|}{8 bits}&
2991 
\multicolumn{4}{c|}{4 bits}&
2992 
\multicolumn{4}{c|}{4 bits}&
2993 
\multicolumn{4}{c|}{4 bits}&
2994 
\multicolumn{4}{c|}{4 bits}&
2995 
\multicolumn{8}{c|}{8 bits}\\
2996 
 
2997 
\hline
2998 
\end{tabular}\par}
2999 
\vspace{15mm}
3000 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3001 
\vspace{5mm}
3002 
\begin{quotation}
3003 
\texttt{\large l.div32s\ rA,rB,rC}{\large \par}
3004 
\end{quotation}
3005 
\vspace{10mm}
3006 
\textbf{\LARGE Description:}{\LARGE \par}
3007 
\vspace{5mm}
3008 
\begin{quotation}
3009 
\texttt{\large The contents of general register rB are divided by the contents of general register rC and the result is placed into general register rA. Both operands are treated as signed integers. A divisor flag is set when the divisor is zero.}{\large \par}
3010 
\end{quotation}
3011 
\vspace{10mm}
3012 
\textbf{\LARGE Operation:}{\LARGE \par}
3013 
\vspace{5mm}
3014 
\begin{quotation}
3015 
rA <- rB / rC
3016 
\end{quotation}
3017 
\vspace{10mm}
3018 
\textbf{\LARGE Notes:}{\LARGE \par}
3019 
\vspace{5mm}
3020 
\begin{quotation}
3021 
 
3022 
\end{quotation}
3023 
\vspace{10mm}
3024 
\vfill
3025 
Class 3:
3026 
{\centering \begin{tabular}{|c|c|c|}
3027 
\hline
3028 
Architecture Level&
3029 
Execution Mode&
3030 
Implementation\\
3031 
\hline
3032 
Core CPU&User and Supervisor&Optional\\
3033 
\hline
3034 
\end{tabular}\par}
3035 
 
3036 
 
3037 
 
3038 
\newpage
3039 
\vspace{10mm}
3040 
\lyxline{\small}\vspace{-1\parskip}
3041 
\vspace{10mm}
3042 
{\raggedright \begin{tabular}{ccc}
3043 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3044 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3045 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3046 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3047 
\textbf{\huge l.div32u}&
3048 
\multicolumn{1}{c}{\textbf{\huge Divide Unsigned}}&
3049 
\textbf{\huge l.div32u}\\
3050 
\end{tabular}\par}
3051 
\bigskip{}
3052 
 
3053 
\vspace{10mm}
3054 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
3055 
\hline
3056 
31&
3057 
&
3058 
&
3059 
&
3060 
&
3061 
&
3062 
&
3063 
24&
3064 
23&
3065 
&
3066 
&
3067 
20&
3068 
19&
3069 
&
3070 
&
3071 
16&
3072 
15&
3073 
&
3074 
&
3075 
12&
3076 
11&
3077 
&
3078 
&
3079 
8&
3080 
7&
3081 
&
3082 
&
3083 
&
3084 
&
3085 
&
3086 
&
3087 
0\\
3088 
\hline
3089 
\multicolumn{8}{|c|}{opcode 0x2c}&
3090 
\multicolumn{4}{c|}{A}&
3091 
\multicolumn{4}{c|}{B}&
3092 
\multicolumn{4}{c|}{C}&
3093 
\multicolumn{4}{c|}{opcode 0xa}&
3094 
\multicolumn{8}{c|}{reserved}\\
3095 
 
3096 
\hline
3097 
\multicolumn{8}{|c|}{8 bits}&
3098 
\multicolumn{4}{c|}{4 bits}&
3099 
\multicolumn{4}{c|}{4 bits}&
3100 
\multicolumn{4}{c|}{4 bits}&
3101 
\multicolumn{4}{c|}{4 bits}&
3102 
\multicolumn{8}{c|}{8 bits}\\
3103 
 
3104 
\hline
3105 
\end{tabular}\par}
3106 
\vspace{15mm}
3107 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3108 
\vspace{5mm}
3109 
\begin{quotation}
3110 
\texttt{\large l.div32u\ rA,rB,rC}{\large \par}
3111 
\end{quotation}
3112 
\vspace{10mm}
3113 
\textbf{\LARGE Description:}{\LARGE \par}
3114 
\vspace{5mm}
3115 
\begin{quotation}
3116 
\texttt{\large The contents of general register rB are divided by the contents of general register rC and the result is placed into general register rA. Both operands are treated as unsigned integers. A divisor flag is set when the divisor is zero.}{\large \par}
3117 
\end{quotation}
3118 
\vspace{10mm}
3119 
\textbf{\LARGE Operation:}{\LARGE \par}
3120 
\vspace{5mm}
3121 
\begin{quotation}
3122 
rA <- rB / rC
3123 
\end{quotation}
3124 
\vspace{10mm}
3125 
\textbf{\LARGE Notes:}{\LARGE \par}
3126 
\vspace{5mm}
3127 
\begin{quotation}
3128 
 
3129 
\end{quotation}
3130 
\vspace{10mm}
3131 
\vfill
3132 
Class 3:
3133 
{\centering \begin{tabular}{|c|c|c|}
3134 
\hline
3135 
Architecture Level&
3136 
Execution Mode&
3137 
Implementation\\
3138 
\hline
3139 
Core CPU&User and Supervisor&Optional\\
3140 
\hline
3141 
\end{tabular}\par}
3142 
 
3143 
 
3144 
 
3145 
\newpage
3146 
\vspace{10mm}
3147 
\lyxline{\small}\vspace{-1\parskip}
3148 
\vspace{10mm}
3149 
{\raggedright \begin{tabular}{ccc}
3150 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3151 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3152 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3153 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3154 
\textbf{\huge l.dcbf}&
3155 
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Flush}}&
3156 
\textbf{\huge l.dcbf}\\
3157 
\end{tabular}\par}
3158 
\bigskip{}
3159 
 
3160 
\vspace{10mm}
3161 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3162 
\hline
3163 
31&
3164 
&
3165 
&
3166 
&
3167 
&
3168 
&
3169 
&
3170 
24&
3171 
23&
3172 
&
3173 
&
3174 
20&
3175 
19&
3176 
&
3177 
&
3178 
&
3179 
&
3180 
&
3181 
&
3182 
12&
3183 
11&
3184 
&
3185 
&
3186 
8&
3187 
7&
3188 
&
3189 
&
3190 
&
3191 
&
3192 
&
3193 
&
3194 
0\\
3195 
\hline
3196 
\multicolumn{8}{|c|}{opcode 0x30}&
3197 
\multicolumn{4}{c|}{A}&
3198 
\multicolumn{8}{c|}{J}&
3199 
\multicolumn{4}{c|}{opcode 0x0}&
3200 
\multicolumn{8}{c|}{J}\\
3201 
 
3202 
\hline
3203 
\multicolumn{8}{|c|}{8 bits}&
3204 
\multicolumn{4}{c|}{4 bits}&
3205 
\multicolumn{8}{c|}{8 bits}&
3206 
\multicolumn{4}{c|}{4 bits}&
3207 
\multicolumn{8}{c|}{8 bits}\\
3208 
 
3209 
\hline
3210 
\end{tabular}\par}
3211 
\vspace{15mm}
3212 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3213 
\vspace{5mm}
3214 
\begin{quotation}
3215 
\texttt{\large l.dcbf\ J(rA)}{\large \par}
3216 
\end{quotation}
3217 
\vspace{10mm}
3218 
\textbf{\LARGE Description:}{\LARGE \par}
3219 
\vspace{5mm}
3220 
\begin{quotation}
3221 
\texttt{\large TBD}{\large \par}
3222 
\end{quotation}
3223 
\vspace{10mm}
3224 
\textbf{\LARGE Operation:}{\LARGE \par}
3225 
\vspace{5mm}
3226 
\begin{quotation}
3227 
 
3228 
\end{quotation}
3229 
\vspace{10mm}
3230 
\textbf{\LARGE Notes:}{\LARGE \par}
3231 
\vspace{5mm}
3232 
\begin{quotation}
3233 
 
3234 
\end{quotation}
3235 
\vspace{10mm}
3236 
\vfill
3237 
Class 5:
3238 
{\centering \begin{tabular}{|c|c|c|}
3239 
\hline
3240 
Architecture Level&
3241 
Execution Mode&
3242 
Implementation\\
3243 
\hline
3244 
Cache Management&Supervisor only&Mandatory if cache supported\\
3245 
\hline
3246 
\end{tabular}\par}
3247 
 
3248 
 
3249 
 
3250 
\newpage
3251 
\vspace{10mm}
3252 
\lyxline{\small}\vspace{-1\parskip}
3253 
\vspace{10mm}
3254 
{\raggedright \begin{tabular}{ccc}
3255 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3256 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3257 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3258 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3259 
\textbf{\huge l.dcbt}&
3260 
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Touch}}&
3261 
\textbf{\huge l.dcbt}\\
3262 
\end{tabular}\par}
3263 
\bigskip{}
3264 
 
3265 
\vspace{10mm}
3266 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3267 
\hline
3268 
31&
3269 
&
3270 
&
3271 
&
3272 
&
3273 
&
3274 
&
3275 
24&
3276 
23&
3277 
&
3278 
&
3279 
20&
3280 
19&
3281 
&
3282 
&
3283 
&
3284 
&
3285 
&
3286 
&
3287 
12&
3288 
11&
3289 
&
3290 
&
3291 
8&
3292 
7&
3293 
&
3294 
&
3295 
&
3296 
&
3297 
&
3298 
&
3299 
0\\
3300 
\hline
3301 
\multicolumn{8}{|c|}{opcode 0x30}&
3302 
\multicolumn{4}{c|}{A}&
3303 
\multicolumn{8}{c|}{J}&
3304 
\multicolumn{4}{c|}{opcode 0x1}&
3305 
\multicolumn{8}{c|}{J}\\
3306 
 
3307 
\hline
3308 
\multicolumn{8}{|c|}{8 bits}&
3309 
\multicolumn{4}{c|}{4 bits}&
3310 
\multicolumn{8}{c|}{8 bits}&
3311 
\multicolumn{4}{c|}{4 bits}&
3312 
\multicolumn{8}{c|}{8 bits}\\
3313 
 
3314 
\hline
3315 
\end{tabular}\par}
3316 
\vspace{15mm}
3317 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3318 
\vspace{5mm}
3319 
\begin{quotation}
3320 
\texttt{\large l.dcbt\ J(rA)}{\large \par}
3321 
\end{quotation}
3322 
\vspace{10mm}
3323 
\textbf{\LARGE Description:}{\LARGE \par}
3324 
\vspace{5mm}
3325 
\begin{quotation}
3326 
\texttt{\large TBD}{\large \par}
3327 
\end{quotation}
3328 
\vspace{10mm}
3329 
\textbf{\LARGE Operation:}{\LARGE \par}
3330 
\vspace{5mm}
3331 
\begin{quotation}
3332 
 
3333 
\end{quotation}
3334 
\vspace{10mm}
3335 
\textbf{\LARGE Notes:}{\LARGE \par}
3336 
\vspace{5mm}
3337 
\begin{quotation}
3338 
 
3339 
\end{quotation}
3340 
\vspace{10mm}
3341 
\vfill
3342 
Class 5:
3343 
{\centering \begin{tabular}{|c|c|c|}
3344 
\hline
3345 
Architecture Level&
3346 
Execution Mode&
3347 
Implementation\\
3348 
\hline
3349 
Cache Management&Supervisor only&Mandatory if cache supported\\
3350 
\hline
3351 
\end{tabular}\par}
3352 
 
3353 
 
3354 
 
3355 
\newpage
3356 
\vspace{10mm}
3357 
\lyxline{\small}\vspace{-1\parskip}
3358 
\vspace{10mm}
3359 
{\raggedright \begin{tabular}{ccc}
3360 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3361 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3362 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3363 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3364 
\textbf{\huge l.dcbi}&
3365 
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Invalidate}}&
3366 
\textbf{\huge l.dcbi}\\
3367 
\end{tabular}\par}
3368 
\bigskip{}
3369 
 
3370 
\vspace{10mm}
3371 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3372 
\hline
3373 
31&
3374 
&
3375 
&
3376 
&
3377 
&
3378 
&
3379 
&
3380 
24&
3381 
23&
3382 
&
3383 
&
3384 
20&
3385 
19&
3386 
&
3387 
&
3388 
&
3389 
&
3390 
&
3391 
&
3392 
12&
3393 
11&
3394 
&
3395 
&
3396 
8&
3397 
7&
3398 
&
3399 
&
3400 
&
3401 
&
3402 
&
3403 
&
3404 
0\\
3405 
\hline
3406 
\multicolumn{8}{|c|}{opcode 0x30}&
3407 
\multicolumn{4}{c|}{A}&
3408 
\multicolumn{8}{c|}{J}&
3409 
\multicolumn{4}{c|}{opcode 0x2}&
3410 
\multicolumn{8}{c|}{J}\\
3411 
 
3412 
\hline
3413 
\multicolumn{8}{|c|}{8 bits}&
3414 
\multicolumn{4}{c|}{4 bits}&
3415 
\multicolumn{8}{c|}{8 bits}&
3416 
\multicolumn{4}{c|}{4 bits}&
3417 
\multicolumn{8}{c|}{8 bits}\\
3418 
 
3419 
\hline
3420 
\end{tabular}\par}
3421 
\vspace{15mm}
3422 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3423 
\vspace{5mm}
3424 
\begin{quotation}
3425 
\texttt{\large l.dcbi\ J(rA)}{\large \par}
3426 
\end{quotation}
3427 
\vspace{10mm}
3428 
\textbf{\LARGE Description:}{\LARGE \par}
3429 
\vspace{5mm}
3430 
\begin{quotation}
3431 
\texttt{\large TBD}{\large \par}
3432 
\end{quotation}
3433 
\vspace{10mm}
3434 
\textbf{\LARGE Operation:}{\LARGE \par}
3435 
\vspace{5mm}
3436 
\begin{quotation}
3437 
 
3438 
\end{quotation}
3439 
\vspace{10mm}
3440 
\textbf{\LARGE Notes:}{\LARGE \par}
3441 
\vspace{5mm}
3442 
\begin{quotation}
3443 
 
3444 
\end{quotation}
3445 
\vspace{10mm}
3446 
\vfill
3447 
Class 5:
3448 
{\centering \begin{tabular}{|c|c|c|}
3449 
\hline
3450 
Architecture Level&
3451 
Execution Mode&
3452 
Implementation\\
3453 
\hline
3454 
Cache Management&Supervisor only&Mandatory if cache supported\\
3455 
\hline
3456 
\end{tabular}\par}
3457 
 
3458 
 
3459 
 
3460 
\newpage
3461 
\vspace{10mm}
3462 
\lyxline{\small}\vspace{-1\parskip}
3463 
\vspace{10mm}
3464 
{\raggedright \begin{tabular}{ccc}
3465 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3466 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3467 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3468 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3469 
\textbf{\huge l.dcia}&
3470 
\multicolumn{1}{c}{\textbf{\huge Data Cache Invalidate All}}&
3471 
\textbf{\huge l.dcia}\\
3472 
\end{tabular}\par}
3473 
\bigskip{}
3474 
 
3475 
\vspace{10mm}
3476 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3477 
\hline
3478 
31&
3479 
&
3480 
&
3481 
&
3482 
&
3483 
&
3484 
&
3485 
24&
3486 
23&
3487 
&
3488 
&
3489 
20&
3490 
19&
3491 
&
3492 
&
3493 
&
3494 
&
3495 
&
3496 
&
3497 
12&
3498 
11&
3499 
&
3500 
&
3501 
8&
3502 
7&
3503 
&
3504 
&
3505 
&
3506 
&
3507 
&
3508 
&
3509 
0\\
3510 
\hline
3511 
\multicolumn{8}{|c|}{opcode 0x30}&
3512 
\multicolumn{4}{c|}{A}&
3513 
\multicolumn{8}{c|}{reserved}&
3514 
\multicolumn{4}{c|}{opcode 0x3}&
3515 
\multicolumn{8}{c|}{reserved}\\
3516 
 
3517 
\hline
3518 
\multicolumn{8}{|c|}{8 bits}&
3519 
\multicolumn{4}{c|}{4 bits}&
3520 
\multicolumn{8}{c|}{8 bits}&
3521 
\multicolumn{4}{c|}{4 bits}&
3522 
\multicolumn{8}{c|}{8 bits}\\
3523 
 
3524 
\hline
3525 
\end{tabular}\par}
3526 
\vspace{15mm}
3527 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3528 
\vspace{5mm}
3529 
\begin{quotation}
3530 
\texttt{\large l.dcia\ }{\large \par}
3531 
\end{quotation}
3532 
\vspace{10mm}
3533 
\textbf{\LARGE Description:}{\LARGE \par}
3534 
\vspace{5mm}
3535 
\begin{quotation}
3536 
\texttt{\large TBD}{\large \par}
3537 
\end{quotation}
3538 
\vspace{10mm}
3539 
\textbf{\LARGE Operation:}{\LARGE \par}
3540 
\vspace{5mm}
3541 
\begin{quotation}
3542 
 
3543 
\end{quotation}
3544 
\vspace{10mm}
3545 
\textbf{\LARGE Notes:}{\LARGE \par}
3546 
\vspace{5mm}
3547 
\begin{quotation}
3548 
 
3549 
\end{quotation}
3550 
\vspace{10mm}
3551 
\vfill
3552 
Class 5:
3553 
{\centering \begin{tabular}{|c|c|c|}
3554 
\hline
3555 
Architecture Level&
3556 
Execution Mode&
3557 
Implementation\\
3558 
\hline
3559 
Cache Management&Supervisor only&Mandatory if cache supported\\
3560 
\hline
3561 
\end{tabular}\par}
3562 
 
3563 
 
3564 
 
3565 
\newpage
3566 
\vspace{10mm}
3567 
\lyxline{\small}\vspace{-1\parskip}
3568 
\vspace{10mm}
3569 
{\raggedright \begin{tabular}{ccc}
3570 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3571 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3572 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3573 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3574 
\textbf{\huge l.dcfa}&
3575 
\multicolumn{1}{c}{\textbf{\huge Data Cache Flush All}}&
3576 
\textbf{\huge l.dcfa}\\
3577 
\end{tabular}\par}
3578 
\bigskip{}
3579 
 
3580 
\vspace{10mm}
3581 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3582 
\hline
3583 
31&
3584 
&
3585 
&
3586 
&
3587 
&
3588 
&
3589 
&
3590 
24&
3591 
23&
3592 
&
3593 
&
3594 
20&
3595 
19&
3596 
&
3597 
&
3598 
&
3599 
&
3600 
&
3601 
&
3602 
12&
3603 
11&
3604 
&
3605 
&
3606 
8&
3607 
7&
3608 
&
3609 
&
3610 
&
3611 
&
3612 
&
3613 
&
3614 
0\\
3615 
\hline
3616 
\multicolumn{8}{|c|}{opcode 0x30}&
3617 
\multicolumn{4}{c|}{A}&
3618 
\multicolumn{8}{c|}{reserved}&
3619 
\multicolumn{4}{c|}{opcode 0x4}&
3620 
\multicolumn{8}{c|}{reserved}\\
3621 
 
3622 
\hline
3623 
\multicolumn{8}{|c|}{8 bits}&
3624 
\multicolumn{4}{c|}{4 bits}&
3625 
\multicolumn{8}{c|}{8 bits}&
3626 
\multicolumn{4}{c|}{4 bits}&
3627 
\multicolumn{8}{c|}{8 bits}\\
3628 
 
3629 
\hline
3630 
\end{tabular}\par}
3631 
\vspace{15mm}
3632 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3633 
\vspace{5mm}
3634 
\begin{quotation}
3635 
\texttt{\large l.dcfa\ }{\large \par}
3636 
\end{quotation}
3637 
\vspace{10mm}
3638 
\textbf{\LARGE Description:}{\LARGE \par}
3639 
\vspace{5mm}
3640 
\begin{quotation}
3641 
\texttt{\large TBD}{\large \par}
3642 
\end{quotation}
3643 
\vspace{10mm}
3644 
\textbf{\LARGE Operation:}{\LARGE \par}
3645 
\vspace{5mm}
3646 
\begin{quotation}
3647 
 
3648 
\end{quotation}
3649 
\vspace{10mm}
3650 
\textbf{\LARGE Notes:}{\LARGE \par}
3651 
\vspace{5mm}
3652 
\begin{quotation}
3653 
 
3654 
\end{quotation}
3655 
\vspace{10mm}
3656 
\vfill
3657 
Class 5:
3658 
{\centering \begin{tabular}{|c|c|c|}
3659 
\hline
3660 
Architecture Level&
3661 
Execution Mode&
3662 
Implementation\\
3663 
\hline
3664 
Cache Management&Supervisor only&Mandatory if cache supported\\
3665 
\hline
3666 
\end{tabular}\par}
3667 
 
3668 
 
3669 
 
3670 
\newpage
3671 
\vspace{10mm}
3672 
\lyxline{\small}\vspace{-1\parskip}
3673 
\vspace{10mm}
3674 
{\raggedright \begin{tabular}{ccc}
3675 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3676 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3677 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3678 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3679 
\textbf{\huge l.tlbia}&
3680 
\multicolumn{1}{c}{\textbf{\huge TLB Invalidate All}}&
3681 
\textbf{\huge l.tlbia}\\
3682 
\end{tabular}\par}
3683 
\bigskip{}
3684 
 
3685 
\vspace{10mm}
3686 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3687 
\hline
3688 
31&
3689 
&
3690 
&
3691 
&
3692 
&
3693 
&
3694 
&
3695 
24&
3696 
23&
3697 
&
3698 
&
3699 
20&
3700 
19&
3701 
&
3702 
&
3703 
&
3704 
&
3705 
&
3706 
&
3707 
12&
3708 
11&
3709 
&
3710 
&
3711 
8&
3712 
7&
3713 
&
3714 
&
3715 
&
3716 
&
3717 
&
3718 
&
3719 
0\\
3720 
\hline
3721 
\multicolumn{8}{|c|}{opcode 0x30}&
3722 
\multicolumn{4}{c|}{A}&
3723 
\multicolumn{8}{c|}{reserved}&
3724 
\multicolumn{4}{c|}{opcode 0x5}&
3725 
\multicolumn{8}{c|}{reserved}\\
3726 
 
3727 
\hline
3728 
\multicolumn{8}{|c|}{8 bits}&
3729 
\multicolumn{4}{c|}{4 bits}&
3730 
\multicolumn{8}{c|}{8 bits}&
3731 
\multicolumn{4}{c|}{4 bits}&
3732 
\multicolumn{8}{c|}{8 bits}\\
3733 
 
3734 
\hline
3735 
\end{tabular}\par}
3736 
\vspace{15mm}
3737 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3738 
\vspace{5mm}
3739 
\begin{quotation}
3740 
\texttt{\large l.tlbia\ }{\large \par}
3741 
\end{quotation}
3742 
\vspace{10mm}
3743 
\textbf{\LARGE Description:}{\LARGE \par}
3744 
\vspace{5mm}
3745 
\begin{quotation}
3746 
\texttt{\large TBD}{\large \par}
3747 
\end{quotation}
3748 
\vspace{10mm}
3749 
\textbf{\LARGE Operation:}{\LARGE \par}
3750 
\vspace{5mm}
3751 
\begin{quotation}
3752 
 
3753 
\end{quotation}
3754 
\vspace{10mm}
3755 
\textbf{\LARGE Notes:}{\LARGE \par}
3756 
\vspace{5mm}
3757 
\begin{quotation}
3758 
 
3759 
\end{quotation}
3760 
\vspace{10mm}
3761 
\vfill
3762 
Class 6:
3763 
{\centering \begin{tabular}{|c|c|c|}
3764 
\hline
3765 
Architecture Level&
3766 
Execution Mode&
3767 
Implementation\\
3768 
\hline
3769 
Virtual Memory&Supervisor only&Mandatory if MMU supported\\
3770 
\hline
3771 
\end{tabular}\par}
3772 
 
3773 
 
3774 
 
3775 
\newpage
3776 
\vspace{10mm}
3777 
\lyxline{\small}\vspace{-1\parskip}
3778 
\vspace{10mm}
3779 
{\raggedright \begin{tabular}{ccc}
3780 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3781 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3782 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3783 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3784 
\textbf{\huge l.mtsr}&
3785 
\multicolumn{1}{c}{\textbf{\huge Move To Special Register}}&
3786 
\textbf{\huge l.mtsr}\\
3787 
\end{tabular}\par}
3788 
\bigskip{}
3789 
 
3790 
\vspace{10mm}
3791 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3792 
\hline
3793 
31&
3794 
&
3795 
&
3796 
&
3797 
&
3798 
&
3799 
&
3800 
24&
3801 
23&
3802 
&
3803 
&
3804 
20&
3805 
19&
3806 
&
3807 
&
3808 
&
3809 
&
3810 
&
3811 
&
3812 
12&
3813 
11&
3814 
&
3815 
&
3816 
8&
3817 
7&
3818 
&
3819 
&
3820 
&
3821 
&
3822 
&
3823 
&
3824 
0\\
3825 
\hline
3826 
\multicolumn{8}{|c|}{opcode 0x30}&
3827 
\multicolumn{4}{c|}{A}&
3828 
\multicolumn{8}{c|}{S}&
3829 
\multicolumn{4}{c|}{opcode 0x6}&
3830 
\multicolumn{8}{c|}{S}\\
3831 
 
3832 
\hline
3833 
\multicolumn{8}{|c|}{8 bits}&
3834 
\multicolumn{4}{c|}{4 bits}&
3835 
\multicolumn{8}{c|}{8 bits}&
3836 
\multicolumn{4}{c|}{4 bits}&
3837 
\multicolumn{8}{c|}{8 bits}\\
3838 
 
3839 
\hline
3840 
\end{tabular}\par}
3841 
\vspace{15mm}
3842 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3843 
\vspace{5mm}
3844 
\begin{quotation}
3845 
\texttt{\large l.mtsr\ rS,rA}{\large \par}
3846 
\end{quotation}
3847 
\vspace{10mm}
3848 
\textbf{\LARGE Description:}{\LARGE \par}
3849 
\vspace{5mm}
3850 
\begin{quotation}
3851 
\texttt{\large The contents of general register rA are moved into special register rS.}{\large \par}
3852 
\end{quotation}
3853 
\vspace{10mm}
3854 
\textbf{\LARGE Operation:}{\LARGE \par}
3855 
\vspace{5mm}
3856 
\begin{quotation}
3857 
rS <- rA
3858 
\end{quotation}
3859 
\vspace{10mm}
3860 
\textbf{\LARGE Notes:}{\LARGE \par}
3861 
\vspace{5mm}
3862 
\begin{quotation}
3863 
 
3864 
\end{quotation}
3865 
\vspace{10mm}
3866 
\vfill
3867 
Class 4:
3868 
{\centering \begin{tabular}{|c|c|c|}
3869 
\hline
3870 
Architecture Level&
3871 
Execution Mode&
3872 
Implementation\\
3873 
\hline
3874 
System Management&Supervisor only&Mandatory always\\
3875 
\hline
3876 
\end{tabular}\par}
3877 
 
3878 
 
3879 
 
3880 
\newpage
3881 
\vspace{10mm}
3882 
\lyxline{\small}\vspace{-1\parskip}
3883 
\vspace{10mm}
3884 
{\raggedright \begin{tabular}{ccc}
3885 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3886 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3887 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3888 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3889 
\textbf{\huge l.mfsr}&
3890 
\multicolumn{1}{c}{\textbf{\huge Move From Special Register}}&
3891 
\textbf{\huge l.mfsr}\\
3892 
\end{tabular}\par}
3893 
\bigskip{}
3894 
 
3895 
\vspace{10mm}
3896 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3897 
\hline
3898 
31&
3899 
&
3900 
&
3901 
&
3902 
&
3903 
&
3904 
&
3905 
24&
3906 
23&
3907 
&
3908 
&
3909 
20&
3910 
19&
3911 
&
3912 
&
3913 
&
3914 
&
3915 
&
3916 
&
3917 
12&
3918 
11&
3919 
&
3920 
&
3921 
8&
3922 
7&
3923 
&
3924 
&
3925 
&
3926 
&
3927 
&
3928 
&
3929 
0\\
3930 
\hline
3931 
\multicolumn{8}{|c|}{opcode 0x30}&
3932 
\multicolumn{4}{c|}{A}&
3933 
\multicolumn{8}{c|}{S}&
3934 
\multicolumn{4}{c|}{opcode 0x7}&
3935 
\multicolumn{8}{c|}{S}\\
3936 
 
3937 
\hline
3938 
\multicolumn{8}{|c|}{8 bits}&
3939 
\multicolumn{4}{c|}{4 bits}&
3940 
\multicolumn{8}{c|}{8 bits}&
3941 
\multicolumn{4}{c|}{4 bits}&
3942 
\multicolumn{8}{c|}{8 bits}\\
3943 
 
3944 
\hline
3945 
\end{tabular}\par}
3946 
\vspace{15mm}
3947 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3948 
\vspace{5mm}
3949 
\begin{quotation}
3950 
\texttt{\large l.mfsr\ rA,rS}{\large \par}
3951 
\end{quotation}
3952 
\vspace{10mm}
3953 
\textbf{\LARGE Description:}{\LARGE \par}
3954 
\vspace{5mm}
3955 
\begin{quotation}
3956 
\texttt{\large The contents of special register rS are moved into general register rA.}{\large \par}
3957 
\end{quotation}
3958 
\vspace{10mm}
3959 
\textbf{\LARGE Operation:}{\LARGE \par}
3960 
\vspace{5mm}
3961 
\begin{quotation}
3962 
rA <- rS
3963 
\end{quotation}
3964 
\vspace{10mm}
3965 
\textbf{\LARGE Notes:}{\LARGE \par}
3966 
\vspace{5mm}
3967 
\begin{quotation}
3968 
 
3969 
\end{quotation}
3970 
\vspace{10mm}
3971 
\vfill
3972 
Class 4:
3973 
{\centering \begin{tabular}{|c|c|c|}
3974 
\hline
3975 
Architecture Level&
3976 
Execution Mode&
3977 
Implementation\\
3978 
\hline
3979 
System Management&Supervisor only&Mandatory always\\
3980 
\hline
3981 
\end{tabular}\par}
3982 
 
3983 
 
3984 
 
3985 
\newpage
3986 
\vspace{10mm}
3987 
\lyxline{\small}\vspace{-1\parskip}
3988 
\vspace{10mm}
3989 
{\raggedright \begin{tabular}{ccc}
3990 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3991 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3992 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3993 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3994 
\textbf{\huge h.sfeq32}&
3995 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Equal}}&
3996 
\textbf{\huge h.sfeq32}\\
3997 
\end{tabular}\par}
3998 
\bigskip{}
3999 
 
4000 
\vspace{10mm}
4001 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4002 
\hline
4003 
15&
4004 
&
4005 
&
4006 
&
4007 
&
4008 
&
4009 
&
4010 
8&
4011 
7&
4012 
&
4013 
&
4014 
4&
4015 
3&
4016 
&
4017 
&
4018 
0\\
4019 
\hline
4020 
\multicolumn{8}{|c|}{opcode 0x40}&
4021 
\multicolumn{4}{c|}{A}&
4022 
\multicolumn{4}{c|}{B}\\
4023 
 
4024 
\hline
4025 
\multicolumn{8}{|c|}{8 bits}&
4026 
\multicolumn{4}{c|}{4 bits}&
4027 
\multicolumn{4}{c|}{4 bits}\\
4028 
 
4029 
\hline
4030 
\end{tabular}\par}
4031 
\vspace{15mm}
4032 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4033 
\vspace{5mm}
4034 
\begin{quotation}
4035 
\texttt{\large h.sfeq32\ rA,rB}{\large \par}
4036 
\end{quotation}
4037 
\vspace{10mm}
4038 
\textbf{\LARGE Description:}{\LARGE \par}
4039 
\vspace{5mm}
4040 
\begin{quotation}
4041 
\texttt{\large The contents of general register rA and the contents of general register rB are compared. If the two registers are equal, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4042 
\end{quotation}
4043 
\vspace{10mm}
4044 
\textbf{\LARGE Operation:}{\LARGE \par}
4045 
\vspace{5mm}
4046 
\begin{quotation}
4047 
flag <- rA == rB
4048 
\end{quotation}
4049 
\vspace{10mm}
4050 
\textbf{\LARGE Notes:}{\LARGE \par}
4051 
\vspace{5mm}
4052 
\begin{quotation}
4053 
 
4054 
\end{quotation}
4055 
\vspace{10mm}
4056 
\vfill
4057 
Class 1:
4058 
{\centering \begin{tabular}{|c|c|c|}
4059 
\hline
4060 
Architecture Level&
4061 
Execution Mode&
4062 
Implementation\\
4063 
\hline
4064 
Core CPU&User and Supervisor&Mandatory always\\
4065 
\hline
4066 
\end{tabular}\par}
4067 
 
4068 
 
4069 
 
4070 
\newpage
4071 
\vspace{10mm}
4072 
\lyxline{\small}\vspace{-1\parskip}
4073 
\vspace{10mm}
4074 
{\raggedright \begin{tabular}{ccc}
4075 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4076 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4077 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4078 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4079 
\textbf{\huge h.sfne32}&
4080 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Not Equal}}&
4081 
\textbf{\huge h.sfne32}\\
4082 
\end{tabular}\par}
4083 
\bigskip{}
4084 
 
4085 
\vspace{10mm}
4086 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4087 
\hline
4088 
15&
4089 
&
4090 
&
4091 
&
4092 
&
4093 
&
4094 
&
4095 
8&
4096 
7&
4097 
&
4098 
&
4099 
4&
4100 
3&
4101 
&
4102 
&
4103 
0\\
4104 
\hline
4105 
\multicolumn{8}{|c|}{opcode 0x41}&
4106 
\multicolumn{4}{c|}{A}&
4107 
\multicolumn{4}{c|}{B}\\
4108 
 
4109 
\hline
4110 
\multicolumn{8}{|c|}{8 bits}&
4111 
\multicolumn{4}{c|}{4 bits}&
4112 
\multicolumn{4}{c|}{4 bits}\\
4113 
 
4114 
\hline
4115 
\end{tabular}\par}
4116 
\vspace{15mm}
4117 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4118 
\vspace{5mm}
4119 
\begin{quotation}
4120 
\texttt{\large h.sfne32\ rA,rB}{\large \par}
4121 
\end{quotation}
4122 
\vspace{10mm}
4123 
\textbf{\LARGE Description:}{\LARGE \par}
4124 
\vspace{5mm}
4125 
\begin{quotation}
4126 
\texttt{\large The contents of general register rA and the contents of general register rB are compared. If the two registers are not equal, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4127 
\end{quotation}
4128 
\vspace{10mm}
4129 
\textbf{\LARGE Operation:}{\LARGE \par}
4130 
\vspace{5mm}
4131 
\begin{quotation}
4132 
flag <- rA != rB
4133 
\end{quotation}
4134 
\vspace{10mm}
4135 
\textbf{\LARGE Notes:}{\LARGE \par}
4136 
\vspace{5mm}
4137 
\begin{quotation}
4138 
 
4139 
\end{quotation}
4140 
\vspace{10mm}
4141 
\vfill
4142 
Class 1:
4143 
{\centering \begin{tabular}{|c|c|c|}
4144 
\hline
4145 
Architecture Level&
4146 
Execution Mode&
4147 
Implementation\\
4148 
\hline
4149 
Core CPU&User and Supervisor&Mandatory always\\
4150 
\hline
4151 
\end{tabular}\par}
4152 
 
4153 
 
4154 
 
4155 
\newpage
4156 
\vspace{10mm}
4157 
\lyxline{\small}\vspace{-1\parskip}
4158 
\vspace{10mm}
4159 
{\raggedright \begin{tabular}{ccc}
4160 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4161 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4162 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4163 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4164 
\textbf{\huge h.sfgt32s}&
4165 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater Than Signed}}&
4166 
\textbf{\huge h.sfgt32s}\\
4167 
\end{tabular}\par}
4168 
\bigskip{}
4169 
 
4170 
\vspace{10mm}
4171 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4172 
\hline
4173 
15&
4174 
&
4175 
&
4176 
&
4177 
&
4178 
&
4179 
&
4180 
8&
4181 
7&
4182 
&
4183 
&
4184 
4&
4185 
3&
4186 
&
4187 
&
4188 
0\\
4189 
\hline
4190 
\multicolumn{8}{|c|}{opcode 0x42}&
4191 
\multicolumn{4}{c|}{A}&
4192 
\multicolumn{4}{c|}{B}\\
4193 
 
4194 
\hline
4195 
\multicolumn{8}{|c|}{8 bits}&
4196 
\multicolumn{4}{c|}{4 bits}&
4197 
\multicolumn{4}{c|}{4 bits}\\
4198 
 
4199 
\hline
4200 
\end{tabular}\par}
4201 
\vspace{15mm}
4202 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4203 
\vspace{5mm}
4204 
\begin{quotation}
4205 
\texttt{\large h.sfgt32s\ rA,rB}{\large \par}
4206 
\end{quotation}
4207 
\vspace{10mm}
4208 
\textbf{\LARGE Description:}{\LARGE \par}
4209 
\vspace{5mm}
4210 
\begin{quotation}
4211 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are greater than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4212 
\end{quotation}
4213 
\vspace{10mm}
4214 
\textbf{\LARGE Operation:}{\LARGE \par}
4215 
\vspace{5mm}
4216 
\begin{quotation}
4217 
flag <- rA > rB
4218 
\end{quotation}
4219 
\vspace{10mm}
4220 
\textbf{\LARGE Notes:}{\LARGE \par}
4221 
\vspace{5mm}
4222 
\begin{quotation}
4223 
 
4224 
\end{quotation}
4225 
\vspace{10mm}
4226 
\vfill
4227 
Class 1:
4228 
{\centering \begin{tabular}{|c|c|c|}
4229 
\hline
4230 
Architecture Level&
4231 
Execution Mode&
4232 
Implementation\\
4233 
\hline
4234 
Core CPU&User and Supervisor&Mandatory always\\
4235 
\hline
4236 
\end{tabular}\par}
4237 
 
4238 
 
4239 
 
4240 
\newpage
4241 
\vspace{10mm}
4242 
\lyxline{\small}\vspace{-1\parskip}
4243 
\vspace{10mm}
4244 
{\raggedright \begin{tabular}{ccc}
4245 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4246 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4247 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4248 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4249 
\textbf{\huge h.sfge32s}&
4250 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater or Equal Than Signed}}&
4251 
\textbf{\huge h.sfge32s}\\
4252 
\end{tabular}\par}
4253 
\bigskip{}
4254 
 
4255 
\vspace{10mm}
4256 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4257 
\hline
4258 
15&
4259 
&
4260 
&
4261 
&
4262 
&
4263 
&
4264 
&
4265 
8&
4266 
7&
4267 
&
4268 
&
4269 
4&
4270 
3&
4271 
&
4272 
&
4273 
0\\
4274 
\hline
4275 
\multicolumn{8}{|c|}{opcode 0x43}&
4276 
\multicolumn{4}{c|}{A}&
4277 
\multicolumn{4}{c|}{B}\\
4278 
 
4279 
\hline
4280 
\multicolumn{8}{|c|}{8 bits}&
4281 
\multicolumn{4}{c|}{4 bits}&
4282 
\multicolumn{4}{c|}{4 bits}\\
4283 
 
4284 
\hline
4285 
\end{tabular}\par}
4286 
\vspace{15mm}
4287 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4288 
\vspace{5mm}
4289 
\begin{quotation}
4290 
\texttt{\large h.sfge32s\ rA,rB}{\large \par}
4291 
\end{quotation}
4292 
\vspace{10mm}
4293 
\textbf{\LARGE Description:}{\LARGE \par}
4294 
\vspace{5mm}
4295 
\begin{quotation}
4296 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are greater or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4297 
\end{quotation}
4298 
\vspace{10mm}
4299 
\textbf{\LARGE Operation:}{\LARGE \par}
4300 
\vspace{5mm}
4301 
\begin{quotation}
4302 
flag <- rA >= rB
4303 
\end{quotation}
4304 
\vspace{10mm}
4305 
\textbf{\LARGE Notes:}{\LARGE \par}
4306 
\vspace{5mm}
4307 
\begin{quotation}
4308 
 
4309 
\end{quotation}
4310 
\vspace{10mm}
4311 
\vfill
4312 
Class 1:
4313 
{\centering \begin{tabular}{|c|c|c|}
4314 
\hline
4315 
Architecture Level&
4316 
Execution Mode&
4317 
Implementation\\
4318 
\hline
4319 
Core CPU&User and Supervisor&Mandatory always\\
4320 
\hline
4321 
\end{tabular}\par}
4322 
 
4323 
 
4324 
 
4325 
\newpage
4326 
\vspace{10mm}
4327 
\lyxline{\small}\vspace{-1\parskip}
4328 
\vspace{10mm}
4329 
{\raggedright \begin{tabular}{ccc}
4330 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4331 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4332 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4333 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4334 
\textbf{\huge h.sflt32s}&
4335 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less Than Signed}}&
4336 
\textbf{\huge h.sflt32s}\\
4337 
\end{tabular}\par}
4338 
\bigskip{}
4339 
 
4340 
\vspace{10mm}
4341 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4342 
\hline
4343 
15&
4344 
&
4345 
&
4346 
&
4347 
&
4348 
&
4349 
&
4350 
8&
4351 
7&
4352 
&
4353 
&
4354 
4&
4355 
3&
4356 
&
4357 
&
4358 
0\\
4359 
\hline
4360 
\multicolumn{8}{|c|}{opcode 0x44}&
4361 
\multicolumn{4}{c|}{A}&
4362 
\multicolumn{4}{c|}{B}\\
4363 
 
4364 
\hline
4365 
\multicolumn{8}{|c|}{8 bits}&
4366 
\multicolumn{4}{c|}{4 bits}&
4367 
\multicolumn{4}{c|}{4 bits}\\
4368 
 
4369 
\hline
4370 
\end{tabular}\par}
4371 
\vspace{15mm}
4372 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4373 
\vspace{5mm}
4374 
\begin{quotation}
4375 
\texttt{\large h.sflt32s\ rA,rB}{\large \par}
4376 
\end{quotation}
4377 
\vspace{10mm}
4378 
\textbf{\LARGE Description:}{\LARGE \par}
4379 
\vspace{5mm}
4380 
\begin{quotation}
4381 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are less than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4382 
\end{quotation}
4383 
\vspace{10mm}
4384 
\textbf{\LARGE Operation:}{\LARGE \par}
4385 
\vspace{5mm}
4386 
\begin{quotation}
4387 
flag <- rA < rB
4388 
\end{quotation}
4389 
\vspace{10mm}
4390 
\textbf{\LARGE Notes:}{\LARGE \par}
4391 
\vspace{5mm}
4392 
\begin{quotation}
4393 
 
4394 
\end{quotation}
4395 
\vspace{10mm}
4396 
\vfill
4397 
Class 1:
4398 
{\centering \begin{tabular}{|c|c|c|}
4399 
\hline
4400 
Architecture Level&
4401 
Execution Mode&
4402 
Implementation\\
4403 
\hline
4404 
Core CPU&User and Supervisor&Mandatory always\\
4405 
\hline
4406 
\end{tabular}\par}
4407 
 
4408 
 
4409 
 
4410 
\newpage
4411 
\vspace{10mm}
4412 
\lyxline{\small}\vspace{-1\parskip}
4413 
\vspace{10mm}
4414 
{\raggedright \begin{tabular}{ccc}
4415 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4416 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4417 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4418 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4419 
\textbf{\huge h.sfle32s}&
4420 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less or Equal Than Signed}}&
4421 
\textbf{\huge h.sfle32s}\\
4422 
\end{tabular}\par}
4423 
\bigskip{}
4424 
 
4425 
\vspace{10mm}
4426 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4427 
\hline
4428 
15&
4429 
&
4430 
&
4431 
&
4432 
&
4433 
&
4434 
&
4435 
8&
4436 
7&
4437 
&
4438 
&
4439 
4&
4440 
3&
4441 
&
4442 
&
4443 
0\\
4444 
\hline
4445 
\multicolumn{8}{|c|}{opcode 0x45}&
4446 
\multicolumn{4}{c|}{A}&
4447 
\multicolumn{4}{c|}{B}\\
4448 
 
4449 
\hline
4450 
\multicolumn{8}{|c|}{8 bits}&
4451 
\multicolumn{4}{c|}{4 bits}&
4452 
\multicolumn{4}{c|}{4 bits}\\
4453 
 
4454 
\hline
4455 
\end{tabular}\par}
4456 
\vspace{15mm}
4457 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4458 
\vspace{5mm}
4459 
\begin{quotation}
4460 
\texttt{\large h.sfle32s\ rA,rB}{\large \par}
4461 
\end{quotation}
4462 
\vspace{10mm}
4463 
\textbf{\LARGE Description:}{\LARGE \par}
4464 
\vspace{5mm}
4465 
\begin{quotation}
4466 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are less or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4467 
\end{quotation}
4468 
\vspace{10mm}
4469 
\textbf{\LARGE Operation:}{\LARGE \par}
4470 
\vspace{5mm}
4471 
\begin{quotation}
4472 
flag <- rA <= rB
4473 
\end{quotation}
4474 
\vspace{10mm}
4475 
\textbf{\LARGE Notes:}{\LARGE \par}
4476 
\vspace{5mm}
4477 
\begin{quotation}
4478 
 
4479 
\end{quotation}
4480 
\vspace{10mm}
4481 
\vfill
4482 
Class 1:
4483 
{\centering \begin{tabular}{|c|c|c|}
4484 
\hline
4485 
Architecture Level&
4486 
Execution Mode&
4487 
Implementation\\
4488 
\hline
4489 
Core CPU&User and Supervisor&Mandatory always\\
4490 
\hline
4491 
\end{tabular}\par}
4492 
 
4493 
 
4494 
 
4495 
\newpage
4496 
\vspace{10mm}
4497 
\lyxline{\small}\vspace{-1\parskip}
4498 
\vspace{10mm}
4499 
{\raggedright \begin{tabular}{ccc}
4500 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4501 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4502 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4503 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4504 
\textbf{\huge h.sfgt32u}&
4505 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater Than Unsigned}}&
4506 
\textbf{\huge h.sfgt32u}\\
4507 
\end{tabular}\par}
4508 
\bigskip{}
4509 
 
4510 
\vspace{10mm}
4511 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4512 
\hline
4513 
15&
4514 
&
4515 
&
4516 
&
4517 
&
4518 
&
4519 
&
4520 
8&
4521 
7&
4522 
&
4523 
&
4524 
4&
4525 
3&
4526 
&
4527 
&
4528 
0\\
4529 
\hline
4530 
\multicolumn{8}{|c|}{opcode 0x46}&
4531 
\multicolumn{4}{c|}{A}&
4532 
\multicolumn{4}{c|}{B}\\
4533 
 
4534 
\hline
4535 
\multicolumn{8}{|c|}{8 bits}&
4536 
\multicolumn{4}{c|}{4 bits}&
4537 
\multicolumn{4}{c|}{4 bits}\\
4538 
 
4539 
\hline
4540 
\end{tabular}\par}
4541 
\vspace{15mm}
4542 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4543 
\vspace{5mm}
4544 
\begin{quotation}
4545 
\texttt{\large h.sfgt32u\ rA,rB}{\large \par}
4546 
\end{quotation}
4547 
\vspace{10mm}
4548 
\textbf{\LARGE Description:}{\LARGE \par}
4549 
\vspace{5mm}
4550 
\begin{quotation}
4551 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are greater than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4552 
\end{quotation}
4553 
\vspace{10mm}
4554 
\textbf{\LARGE Operation:}{\LARGE \par}
4555 
\vspace{5mm}
4556 
\begin{quotation}
4557 
flag <- rA > rB
4558 
\end{quotation}
4559 
\vspace{10mm}
4560 
\textbf{\LARGE Notes:}{\LARGE \par}
4561 
\vspace{5mm}
4562 
\begin{quotation}
4563 
 
4564 
\end{quotation}
4565 
\vspace{10mm}
4566 
\vfill
4567 
Class 1:
4568 
{\centering \begin{tabular}{|c|c|c|}
4569 
\hline
4570 
Architecture Level&
4571 
Execution Mode&
4572 
Implementation\\
4573 
\hline
4574 
Core CPU&User and Supervisor&Mandatory always\\
4575 
\hline
4576 
\end{tabular}\par}
4577 
 
4578 
 
4579 
 
4580 
\newpage
4581 
\vspace{10mm}
4582 
\lyxline{\small}\vspace{-1\parskip}
4583 
\vspace{10mm}
4584 
{\raggedright \begin{tabular}{ccc}
4585 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4586 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4587 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4588 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4589 
\textbf{\huge h.sfge32u}&
4590 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater or Equal Than Unsigned}}&
4591 
\textbf{\huge h.sfge32u}\\
4592 
\end{tabular}\par}
4593 
\bigskip{}
4594 
 
4595 
\vspace{10mm}
4596 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4597 
\hline
4598 
15&
4599 
&
4600 
&
4601 
&
4602 
&
4603 
&
4604 
&
4605 
8&
4606 
7&
4607 
&
4608 
&
4609 
4&
4610 
3&
4611 
&
4612 
&
4613 
0\\
4614 
\hline
4615 
\multicolumn{8}{|c|}{opcode 0x47}&
4616 
\multicolumn{4}{c|}{A}&
4617 
\multicolumn{4}{c|}{B}\\
4618 
 
4619 
\hline
4620 
\multicolumn{8}{|c|}{8 bits}&
4621 
\multicolumn{4}{c|}{4 bits}&
4622 
\multicolumn{4}{c|}{4 bits}\\
4623 
 
4624 
\hline
4625 
\end{tabular}\par}
4626 
\vspace{15mm}
4627 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4628 
\vspace{5mm}
4629 
\begin{quotation}
4630 
\texttt{\large h.sfge32u\ rA,rB}{\large \par}
4631 
\end{quotation}
4632 
\vspace{10mm}
4633 
\textbf{\LARGE Description:}{\LARGE \par}
4634 
\vspace{5mm}
4635 
\begin{quotation}
4636 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are greater or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4637 
\end{quotation}
4638 
\vspace{10mm}
4639 
\textbf{\LARGE Operation:}{\LARGE \par}
4640 
\vspace{5mm}
4641 
\begin{quotation}
4642 
flag <- rA >= rB
4643 
\end{quotation}
4644 
\vspace{10mm}
4645 
\textbf{\LARGE Notes:}{\LARGE \par}
4646 
\vspace{5mm}
4647 
\begin{quotation}
4648 
 
4649 
\end{quotation}
4650 
\vspace{10mm}
4651 
\vfill
4652 
Class 1:
4653 
{\centering \begin{tabular}{|c|c|c|}
4654 
\hline
4655 
Architecture Level&
4656 
Execution Mode&
4657 
Implementation\\
4658 
\hline
4659 
Core CPU&User and Supervisor&Mandatory always\\
4660 
\hline
4661 
\end{tabular}\par}
4662 
 
4663 
 
4664 
 
4665 
\newpage
4666 
\vspace{10mm}
4667 
\lyxline{\small}\vspace{-1\parskip}
4668 
\vspace{10mm}
4669 
{\raggedright \begin{tabular}{ccc}
4670 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4671 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4672 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4673 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4674 
\textbf{\huge h.sflt32u}&
4675 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less Than Unsigned}}&
4676 
\textbf{\huge h.sflt32u}\\
4677 
\end{tabular}\par}
4678 
\bigskip{}
4679 
 
4680 
\vspace{10mm}
4681 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4682 
\hline
4683 
15&
4684 
&
4685 
&
4686 
&
4687 
&
4688 
&
4689 
&
4690 
8&
4691 
7&
4692 
&
4693 
&
4694 
4&
4695 
3&
4696 
&
4697 
&
4698 
0\\
4699 
\hline
4700 
\multicolumn{8}{|c|}{opcode 0x48}&
4701 
\multicolumn{4}{c|}{A}&
4702 
\multicolumn{4}{c|}{B}\\
4703 
 
4704 
\hline
4705 
\multicolumn{8}{|c|}{8 bits}&
4706 
\multicolumn{4}{c|}{4 bits}&
4707 
\multicolumn{4}{c|}{4 bits}\\
4708 
 
4709 
\hline
4710 
\end{tabular}\par}
4711 
\vspace{15mm}
4712 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4713 
\vspace{5mm}
4714 
\begin{quotation}
4715 
\texttt{\large h.sflt32u\ rA,rB}{\large \par}
4716 
\end{quotation}
4717 
\vspace{10mm}
4718 
\textbf{\LARGE Description:}{\LARGE \par}
4719 
\vspace{5mm}
4720 
\begin{quotation}
4721 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are less than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4722 
\end{quotation}
4723 
\vspace{10mm}
4724 
\textbf{\LARGE Operation:}{\LARGE \par}
4725 
\vspace{5mm}
4726 
\begin{quotation}
4727 
flag <- rA < rB
4728 
\end{quotation}
4729 
\vspace{10mm}
4730 
\textbf{\LARGE Notes:}{\LARGE \par}
4731 
\vspace{5mm}
4732 
\begin{quotation}
4733 
 
4734 
\end{quotation}
4735 
\vspace{10mm}
4736 
\vfill
4737 
Class 1:
4738 
{\centering \begin{tabular}{|c|c|c|}
4739 
\hline
4740 
Architecture Level&
4741 
Execution Mode&
4742 
Implementation\\
4743 
\hline
4744 
Core CPU&User and Supervisor&Mandatory always\\
4745 
\hline
4746 
\end{tabular}\par}
4747 
 
4748 
 
4749 
 
4750 
\newpage
4751 
\vspace{10mm}
4752 
\lyxline{\small}\vspace{-1\parskip}
4753 
\vspace{10mm}
4754 
{\raggedright \begin{tabular}{ccc}
4755 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4756 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4757 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4758 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4759 
\textbf{\huge h.sfle32u}&
4760 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less or Equal Than Unsigned}}&
4761 
\textbf{\huge h.sfle32u}\\
4762 
\end{tabular}\par}
4763 
\bigskip{}
4764 
 
4765 
\vspace{10mm}
4766 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4767 
\hline
4768 
15&
4769 
&
4770 
&
4771 
&
4772 
&
4773 
&
4774 
&
4775 
8&
4776 
7&
4777 
&
4778 
&
4779 
4&
4780 
3&
4781 
&
4782 
&
4783 
0\\
4784 
\hline
4785 
\multicolumn{8}{|c|}{opcode 0x49}&
4786 
\multicolumn{4}{c|}{A}&
4787 
\multicolumn{4}{c|}{B}\\
4788 
 
4789 
\hline
4790 
\multicolumn{8}{|c|}{8 bits}&
4791 
\multicolumn{4}{c|}{4 bits}&
4792 
\multicolumn{4}{c|}{4 bits}\\
4793 
 
4794 
\hline
4795 
\end{tabular}\par}
4796 
\vspace{15mm}
4797 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4798 
\vspace{5mm}
4799 
\begin{quotation}
4800 
\texttt{\large h.sfle32u\ rA,rB}{\large \par}
4801 
\end{quotation}
4802 
\vspace{10mm}
4803 
\textbf{\LARGE Description:}{\LARGE \par}
4804 
\vspace{5mm}
4805 
\begin{quotation}
4806 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are less or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4807 
\end{quotation}
4808 
\vspace{10mm}
4809 
\textbf{\LARGE Operation:}{\LARGE \par}
4810 
\vspace{5mm}
4811 
\begin{quotation}
4812 
flag <- rA <= rB
4813 
\end{quotation}
4814 
\vspace{10mm}
4815 
\textbf{\LARGE Notes:}{\LARGE \par}
4816 
\vspace{5mm}
4817 
\begin{quotation}
4818 
 
4819 
\end{quotation}
4820 
\vspace{10mm}
4821 
\vfill
4822 
Class 1:
4823 
{\centering \begin{tabular}{|c|c|c|}
4824 
\hline
4825 
Architecture Level&
4826 
Execution Mode&
4827 
Implementation\\
4828 
\hline
4829 
Core CPU&User and Supervisor&Mandatory always\\
4830 
\hline
4831 
\end{tabular}\par}
4832 
 
4833 
 
4834 
 
4835 
\newpage
4836 
\vspace{10mm}
4837 
\lyxline{\small}\vspace{-1\parskip}
4838 
\vspace{10mm}
4839 
{\raggedright \begin{tabular}{ccc}
4840 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4841 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4842 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4843 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4844 
\textbf{\huge h.mov32}&
4845 
\multicolumn{1}{c}{\textbf{\huge Move}}&
4846 
\textbf{\huge h.mov32}\\
4847 
\end{tabular}\par}
4848 
\bigskip{}
4849 
 
4850 
\vspace{10mm}
4851 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4852 
\hline
4853 
15&
4854 
&
4855 
&
4856 
&
4857 
&
4858 
&
4859 
&
4860 
8&
4861 
7&
4862 
&
4863 
&
4864 
4&
4865 
3&
4866 
&
4867 
&
4868 
0\\
4869 
\hline
4870 
\multicolumn{8}{|c|}{opcode 0x4a}&
4871 
\multicolumn{4}{c|}{A}&
4872 
\multicolumn{4}{c|}{B}\\
4873 
 
4874 
\hline
4875 
\multicolumn{8}{|c|}{8 bits}&
4876 
\multicolumn{4}{c|}{4 bits}&
4877 
\multicolumn{4}{c|}{4 bits}\\
4878 
 
4879 
\hline
4880 
\end{tabular}\par}
4881 
\vspace{15mm}
4882 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4883 
\vspace{5mm}
4884 
\begin{quotation}
4885 
\texttt{\large h.mov32\ rA,rB}{\large \par}
4886 
\end{quotation}
4887 
\vspace{10mm}
4888 
\textbf{\LARGE Description:}{\LARGE \par}
4889 
\vspace{5mm}
4890 
\begin{quotation}
4891 
\texttt{\large The contents of general register rB are moved into general register rA.}{\large \par}
4892 
\end{quotation}
4893 
\vspace{10mm}
4894 
\textbf{\LARGE Operation:}{\LARGE \par}
4895 
\vspace{5mm}
4896 
\begin{quotation}
4897 
rA <- rB
4898 
\end{quotation}
4899 
\vspace{10mm}
4900 
\textbf{\LARGE Notes:}{\LARGE \par}
4901 
\vspace{5mm}
4902 
\begin{quotation}
4903 
 
4904 
\end{quotation}
4905 
\vspace{10mm}
4906 
\vfill
4907 
Class 2:
4908 
{\centering \begin{tabular}{|c|c|c|}
4909 
\hline
4910 
Architecture Level&
4911 
Execution Mode&
4912 
Implementation\\
4913 
\hline
4914 
Core CPU&User and Supervisor&Recommended\\
4915 
\hline
4916 
\end{tabular}\par}
4917 
 
4918 
 
4919 
 
4920 
\newpage
4921 
\vspace{10mm}
4922 
\lyxline{\small}\vspace{-1\parskip}
4923 
\vspace{10mm}
4924 
{\raggedright \begin{tabular}{ccc}
4925 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4926 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4927 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4928 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4929 
\textbf{\huge h.ext16s}&
4930 
\multicolumn{1}{c}{\textbf{\huge Extend Half Word with Sign}}&
4931 
\textbf{\huge h.ext16s}\\
4932 
\end{tabular}\par}
4933 
\bigskip{}
4934 
 
4935 
\vspace{10mm}
4936 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
4937 
\hline
4938 
15&
4939 
&
4940 
&
4941 
&
4942 
&
4943 
&
4944 
&
4945 
8&
4946 
7&
4947 
&
4948 
&
4949 
4&
4950 
3&
4951 
2&
4952 
&
4953 
0\\
4954 
\hline
4955 
\multicolumn{8}{|c|}{opcode 0x4b}&
4956 
\multicolumn{4}{c|}{A}&
4957 
\multicolumn{1}{c|}{reserved}&
4958 
\multicolumn{3}{c|}{opcode 0x0}\\
4959 
 
4960 
\hline
4961 
\multicolumn{8}{|c|}{8 bits}&
4962 
\multicolumn{4}{c|}{4 bits}&
4963 
\multicolumn{1}{c|}{1 bits}&
4964 
\multicolumn{3}{c|}{3 bits}\\
4965 
 
4966 
\hline
4967 
\end{tabular}\par}
4968 
\vspace{15mm}
4969 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4970 
\vspace{5mm}
4971 
\begin{quotation}
4972 
\texttt{\large h.ext16s\ rA}{\large \par}
4973 
\end{quotation}
4974 
\vspace{10mm}
4975 
\textbf{\LARGE Description:}{\LARGE \par}
4976 
\vspace{5mm}
4977 
\begin{quotation}
4978 
\texttt{\large Bit 15 of general register rA is placed in high-order 16 bits of general register rA. The low-order 16 bits of general register rA are left unchanged.}{\large \par}
4979 
\end{quotation}
4980 
\vspace{10mm}
4981 
\textbf{\LARGE Operation:}{\LARGE \par}
4982 
\vspace{5mm}
4983 
\begin{quotation}
4984 
rA{[}31:16{]} <- rA{[}15{]}
4985 
\end{quotation}
4986 
\vspace{10mm}
4987 
\textbf{\LARGE Notes:}{\LARGE \par}
4988 
\vspace{5mm}
4989 
\begin{quotation}
4990 
 
4991 
\end{quotation}
4992 
\vspace{10mm}
4993 
\vfill
4994 
Class 2:
4995 
{\centering \begin{tabular}{|c|c|c|}
4996 
\hline
4997 
Architecture Level&
4998 
Execution Mode&
4999 
Implementation\\
5000 
\hline
5001 
Core CPU&User and Supervisor&Recommended\\
5002 
\hline
5003 
\end{tabular}\par}
5004 
 
5005 
 
5006 
 
5007 
\newpage
5008 
\vspace{10mm}
5009 
\lyxline{\small}\vspace{-1\parskip}
5010 
\vspace{10mm}
5011 
{\raggedright \begin{tabular}{ccc}
5012 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5013 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5014 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5015 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5016 
\textbf{\huge h.ext16z}&
5017 
\multicolumn{1}{c}{\textbf{\huge Extend Half Word with Zero}}&
5018 
\textbf{\huge h.ext16z}\\
5019 
\end{tabular}\par}
5020 
\bigskip{}
5021 
 
5022 
\vspace{10mm}
5023 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5024 
\hline
5025 
15&
5026 
&
5027 
&
5028 
&
5029 
&
5030 
&
5031 
&
5032 
8&
5033 
7&
5034 
&
5035 
&
5036 
4&
5037 
3&
5038 
2&
5039 
&
5040 
0\\
5041 
\hline
5042 
\multicolumn{8}{|c|}{opcode 0x4b}&
5043 
\multicolumn{4}{c|}{A}&
5044 
\multicolumn{1}{c|}{reserved}&
5045 
\multicolumn{3}{c|}{opcode 0x1}\\
5046 
 
5047 
\hline
5048 
\multicolumn{8}{|c|}{8 bits}&
5049 
\multicolumn{4}{c|}{4 bits}&
5050 
\multicolumn{1}{c|}{1 bits}&
5051 
\multicolumn{3}{c|}{3 bits}\\
5052 
 
5053 
\hline
5054 
\end{tabular}\par}
5055 
\vspace{15mm}
5056 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5057 
\vspace{5mm}
5058 
\begin{quotation}
5059 
\texttt{\large h.ext16z\ rA}{\large \par}
5060 
\end{quotation}
5061 
\vspace{10mm}
5062 
\textbf{\LARGE Description:}{\LARGE \par}
5063 
\vspace{5mm}
5064 
\begin{quotation}
5065 
\texttt{\large Zero is placed in high-order 16 bits of general register rA. The low-order 16 bits of general register rA are left unchanged.}{\large \par}
5066 
\end{quotation}
5067 
\vspace{10mm}
5068 
\textbf{\LARGE Operation:}{\LARGE \par}
5069 
\vspace{5mm}
5070 
\begin{quotation}
5071 
rA{[}31:16{]} <- 0
5072 
\end{quotation}
5073 
\vspace{10mm}
5074 
\textbf{\LARGE Notes:}{\LARGE \par}
5075 
\vspace{5mm}
5076 
\begin{quotation}
5077 
 
5078 
\end{quotation}
5079 
\vspace{10mm}
5080 
\vfill
5081 
Class 2:
5082 
{\centering \begin{tabular}{|c|c|c|}
5083 
\hline
5084 
Architecture Level&
5085 
Execution Mode&
5086 
Implementation\\
5087 
\hline
5088 
Core CPU&User and Supervisor&Recommended\\
5089 
\hline
5090 
\end{tabular}\par}
5091 
 
5092 
 
5093 
 
5094 
\newpage
5095 
\vspace{10mm}
5096 
\lyxline{\small}\vspace{-1\parskip}
5097 
\vspace{10mm}
5098 
{\raggedright \begin{tabular}{ccc}
5099 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5100 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5101 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5102 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5103 
\textbf{\huge h.ext8s}&
5104 
\multicolumn{1}{c}{\textbf{\huge Extend Byte with Sign}}&
5105 
\textbf{\huge h.ext8s}\\
5106 
\end{tabular}\par}
5107 
\bigskip{}
5108 
 
5109 
\vspace{10mm}
5110 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5111 
\hline
5112 
15&
5113 
&
5114 
&
5115 
&
5116 
&
5117 
&
5118 
&
5119 
8&
5120 
7&
5121 
&
5122 
&
5123 
4&
5124 
3&
5125 
2&
5126 
&
5127 
0\\
5128 
\hline
5129 
\multicolumn{8}{|c|}{opcode 0x4b}&
5130 
\multicolumn{4}{c|}{A}&
5131 
\multicolumn{1}{c|}{reserved}&
5132 
\multicolumn{3}{c|}{opcode 0x2}\\
5133 
 
5134 
\hline
5135 
\multicolumn{8}{|c|}{8 bits}&
5136 
\multicolumn{4}{c|}{4 bits}&
5137 
\multicolumn{1}{c|}{1 bits}&
5138 
\multicolumn{3}{c|}{3 bits}\\
5139 
 
5140 
\hline
5141 
\end{tabular}\par}
5142 
\vspace{15mm}
5143 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5144 
\vspace{5mm}
5145 
\begin{quotation}
5146 
\texttt{\large h.ext8s\ rA}{\large \par}
5147 
\end{quotation}
5148 
\vspace{10mm}
5149 
\textbf{\LARGE Description:}{\LARGE \par}
5150 
\vspace{5mm}
5151 
\begin{quotation}
5152 
\texttt{\large Bit 7 of general register rA is placed in high-order 24 bits of general register rA. The low-order eight bits of general register rA are left unchanged.}{\large \par}
5153 
\end{quotation}
5154 
\vspace{10mm}
5155 
\textbf{\LARGE Operation:}{\LARGE \par}
5156 
\vspace{5mm}
5157 
\begin{quotation}
5158 
rA{[}31:8{]} <- rA{[}7{]}
5159 
\end{quotation}
5160 
\vspace{10mm}
5161 
\textbf{\LARGE Notes:}{\LARGE \par}
5162 
\vspace{5mm}
5163 
\begin{quotation}
5164 
 
5165 
\end{quotation}
5166 
\vspace{10mm}
5167 
\vfill
5168 
Class 2:
5169 
{\centering \begin{tabular}{|c|c|c|}
5170 
\hline
5171 
Architecture Level&
5172 
Execution Mode&
5173 
Implementation\\
5174 
\hline
5175 
Core CPU&User and Supervisor&Recommended\\
5176 
\hline
5177 
\end{tabular}\par}
5178 
 
5179 
 
5180 
 
5181 
\newpage
5182 
\vspace{10mm}
5183 
\lyxline{\small}\vspace{-1\parskip}
5184 
\vspace{10mm}
5185 
{\raggedright \begin{tabular}{ccc}
5186 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5187 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5188 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5189 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5190 
\textbf{\huge h.ext8z}&
5191 
\multicolumn{1}{c}{\textbf{\huge Extend Byte with Zero}}&
5192 
\textbf{\huge h.ext8z}\\
5193 
\end{tabular}\par}
5194 
\bigskip{}
5195 
 
5196 
\vspace{10mm}
5197 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5198 
\hline
5199 
15&
5200 
&
5201 
&
5202 
&
5203 
&
5204 
&
5205 
&
5206 
8&
5207 
7&
5208 
&
5209 
&
5210 
4&
5211 
3&
5212 
2&
5213 
&
5214 
0\\
5215 
\hline
5216 
\multicolumn{8}{|c|}{opcode 0x4b}&
5217 
\multicolumn{4}{c|}{A}&
5218 
\multicolumn{1}{c|}{reserved}&
5219 
\multicolumn{3}{c|}{opcode 0x3}\\
5220 
 
5221 
\hline
5222 
\multicolumn{8}{|c|}{8 bits}&
5223 
\multicolumn{4}{c|}{4 bits}&
5224 
\multicolumn{1}{c|}{1 bits}&
5225 
\multicolumn{3}{c|}{3 bits}\\
5226 
 
5227 
\hline
5228 
\end{tabular}\par}
5229 
\vspace{15mm}
5230 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5231 
\vspace{5mm}
5232 
\begin{quotation}
5233 
\texttt{\large h.ext8z\ rA}{\large \par}
5234 
\end{quotation}
5235 
\vspace{10mm}
5236 
\textbf{\LARGE Description:}{\LARGE \par}
5237 
\vspace{5mm}
5238 
\begin{quotation}
5239 
\texttt{\large Zero is placed in high-order 24 bits of general register rA. The low-order eight bits of general register rA are left unchanged.}{\large \par}
5240 
\end{quotation}
5241 
\vspace{10mm}
5242 
\textbf{\LARGE Operation:}{\LARGE \par}
5243 
\vspace{5mm}
5244 
\begin{quotation}
5245 
rA{[}31:8{]} <- 0
5246 
\end{quotation}
5247 
\vspace{10mm}
5248 
\textbf{\LARGE Notes:}{\LARGE \par}
5249 
\vspace{5mm}
5250 
\begin{quotation}
5251 
 
5252 
\end{quotation}
5253 
\vspace{10mm}
5254 
\vfill
5255 
Class 2:
5256 
{\centering \begin{tabular}{|c|c|c|}
5257 
\hline
5258 
Architecture Level&
5259 
Execution Mode&
5260 
Implementation\\
5261 
\hline
5262 
Core CPU&User and Supervisor&Recommended\\
5263 
\hline
5264 
\end{tabular}\par}
5265 
 
5266 
 
5267 
 
5268 
\newpage
5269 
\vspace{10mm}
5270 
\lyxline{\small}\vspace{-1\parskip}
5271 
\vspace{10mm}
5272 
{\raggedright \begin{tabular}{ccc}
5273 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5274 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5275 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5276 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5277 
\textbf{\huge h.nop}&
5278 
\multicolumn{1}{c}{\textbf{\huge No Operation}}&
5279 
\textbf{\huge h.nop}\\
5280 
\end{tabular}\par}
5281 
\bigskip{}
5282 
 
5283 
\vspace{10mm}
5284 
{\centering \begin{tabular}{|cccccccc|ccccc|ccc|}
5285 
\hline
5286 
15&
5287 
&
5288 
&
5289 
&
5290 
&
5291 
&
5292 
&
5293 
8&
5294 
7&
5295 
&
5296 
&
5297 
&
5298 
3&
5299 
2&
5300 
&
5301 
0\\
5302 
\hline
5303 
\multicolumn{8}{|c|}{opcode 0x4b}&
5304 
\multicolumn{5}{c|}{reserved}&
5305 
\multicolumn{3}{c|}{opcode 0x4}\\
5306 
 
5307 
\hline
5308 
\multicolumn{8}{|c|}{8 bits}&
5309 
\multicolumn{5}{c|}{5 bits}&
5310 
\multicolumn{3}{c|}{3 bits}\\
5311 
 
5312 
\hline
5313 
\end{tabular}\par}
5314 
\vspace{15mm}
5315 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5316 
\vspace{5mm}
5317 
\begin{quotation}
5318 
\texttt{\large h.nop\ }{\large \par}
5319 
\end{quotation}
5320 
\vspace{10mm}
5321 
\textbf{\LARGE Description:}{\LARGE \par}
5322 
\vspace{5mm}
5323 
\begin{quotation}
5324 
\texttt{\large This instruction does not do anything except it takes at least one clock cycle to complete. It is usually used to fill gaps between 16 bit and 32 bit instructions.}{\large \par}
5325 
\end{quotation}
5326 
\vspace{10mm}
5327 
\textbf{\LARGE Operation:}{\LARGE \par}
5328 
\vspace{5mm}
5329 
\begin{quotation}
5330 
 
5331 
\end{quotation}
5332 
\vspace{10mm}
5333 
\textbf{\LARGE Notes:}{\LARGE \par}
5334 
\vspace{5mm}
5335 
\begin{quotation}
5336 
 
5337 
\end{quotation}
5338 
\vspace{10mm}
5339 
\vfill
5340 
Class 1:
5341 
{\centering \begin{tabular}{|c|c|c|}
5342 
\hline
5343 
Architecture Level&
5344 
Execution Mode&
5345 
Implementation\\
5346 
\hline
5347 
Core CPU&User and Supervisor&Mandatory always\\
5348 
\hline
5349 
\end{tabular}\par}
5350 
 
5351 
 
5352 
 
5353 
\newpage
5354 
\vspace{10mm}
5355 
\lyxline{\small}\vspace{-1\parskip}
5356 
\vspace{10mm}
5357 
{\raggedright \begin{tabular}{ccc}
5358 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5359 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5360 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5361 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5362 
\textbf{\huge h.jalr}&
5363 
\multicolumn{1}{c}{\textbf{\huge Jump and Link Register}}&
5364 
\textbf{\huge h.jalr}\\
5365 
\end{tabular}\par}
5366 
\bigskip{}
5367 
 
5368 
\vspace{10mm}
5369 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5370 
\hline
5371 
15&
5372 
&
5373 
&
5374 
&
5375 
&
5376 
&
5377 
&
5378 
8&
5379 
7&
5380 
&
5381 
&
5382 
4&
5383 
3&
5384 
2&
5385 
&
5386 
0\\
5387 
\hline
5388 
\multicolumn{8}{|c|}{opcode 0x4b}&
5389 
\multicolumn{4}{c|}{A}&
5390 
\multicolumn{1}{c|}{reserved}&
5391 
\multicolumn{3}{c|}{opcode 0x5}\\
5392 
 
5393 
\hline
5394 
\multicolumn{8}{|c|}{8 bits}&
5395 
\multicolumn{4}{c|}{4 bits}&
5396 
\multicolumn{1}{c|}{1 bits}&
5397 
\multicolumn{3}{c|}{3 bits}\\
5398 
 
5399 
\hline
5400 
\end{tabular}\par}
5401 
\vspace{15mm}
5402 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5403 
\vspace{5mm}
5404 
\begin{quotation}
5405 
\texttt{\large h.jalr\ rA}{\large \par}
5406 
\end{quotation}
5407 
\vspace{10mm}
5408 
\textbf{\LARGE Description:}{\LARGE \par}
5409 
\vspace{5mm}
5410 
\begin{quotation}
5411 
\texttt{\large The contents of general register rA is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
5412 
\end{quotation}
5413 
\vspace{10mm}
5414 
\textbf{\LARGE Operation:}{\LARGE \par}
5415 
\vspace{5mm}
5416 
\begin{quotation}
5417 
PC <- rA\\LR <- DelayInsnAddr + 4
5418 
\end{quotation}
5419 
\vspace{10mm}
5420 
\textbf{\LARGE Notes:}{\LARGE \par}
5421 
\vspace{5mm}
5422 
\begin{quotation}
5423 
 
5424 
\end{quotation}
5425 
\vspace{10mm}
5426 
\vfill
5427 
Class 1:
5428 
{\centering \begin{tabular}{|c|c|c|}
5429 
\hline
5430 
Architecture Level&
5431 
Execution Mode&
5432 
Implementation\\
5433 
\hline
5434 
Core CPU&User and Supervisor&Mandatory always\\
5435 
\hline
5436 
\end{tabular}\par}
5437 
 
5438 
 
5439 
 
5440 
\newpage
5441 
\vspace{10mm}
5442 
\lyxline{\small}\vspace{-1\parskip}
5443 
\vspace{10mm}
5444 
{\raggedright \begin{tabular}{ccc}
5445 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5446 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5447 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5448 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5449 
\textbf{\huge h.load32u}&
5450 
\multicolumn{1}{c}{\textbf{\huge Load Word and Extend with Zero}}&
5451 
\textbf{\huge h.load32u}\\
5452 
\end{tabular}\par}
5453 
\bigskip{}
5454 
 
5455 
\vspace{10mm}
5456 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
5457 
\hline
5458 
15&
5459 
&
5460 
&
5461 
12&
5462 
11&
5463 
&
5464 
&
5465 
8&
5466 
7&
5467 
&
5468 
&
5469 
4&
5470 
3&
5471 
&
5472 
&
5473 
0\\
5474 
\hline
5475 
\multicolumn{4}{|c|}{opcode 0x5}&
5476 
\multicolumn{4}{c|}{N}&
5477 
\multicolumn{4}{c|}{A}&
5478 
\multicolumn{4}{c|}{B}\\
5479 
 
5480 
\hline
5481 
\multicolumn{4}{|c|}{4 bits}&
5482 
\multicolumn{4}{c|}{4 bits}&
5483 
\multicolumn{4}{c|}{4 bits}&
5484 
\multicolumn{4}{c|}{4 bits}\\
5485 
 
5486 
\hline
5487 
\end{tabular}\par}
5488 
\vspace{15mm}
5489 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5490 
\vspace{5mm}
5491 
\begin{quotation}
5492 
\texttt{\large h.load32u\ rA,N(rB)}{\large \par}
5493 
\end{quotation}
5494 
\vspace{10mm}
5495 
\textbf{\LARGE Description:}{\LARGE \par}
5496 
\vspace{5mm}
5497 
\begin{quotation}
5498 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The word in memory addressed by EA is loaded into general register rA. }{\large \par}
5499 
\end{quotation}
5500 
\vspace{10mm}
5501 
\textbf{\LARGE Operation:}{\LARGE \par}
5502 
\vspace{5mm}
5503 
\begin{quotation}
5504 
EA <- exts(Immediate) + rB\\rA <- (EA){[}31:0{]}
5505 
\end{quotation}
5506 
\vspace{10mm}
5507 
\textbf{\LARGE Notes:}{\LARGE \par}
5508 
\vspace{5mm}
5509 
\begin{quotation}
5510 
 
5511 
\end{quotation}
5512 
\vspace{10mm}
5513 
\vfill
5514 
Class 2:
5515 
{\centering \begin{tabular}{|c|c|c|}
5516 
\hline
5517 
Architecture Level&
5518 
Execution Mode&
5519 
Implementation\\
5520 
\hline
5521 
Core CPU&User and Supervisor&Recommended\\
5522 
\hline
5523 
\end{tabular}\par}
5524 
 
5525 
 
5526 
 
5527 
\newpage
5528 
\vspace{10mm}
5529 
\lyxline{\small}\vspace{-1\parskip}
5530 
\vspace{10mm}
5531 
{\raggedright \begin{tabular}{ccc}
5532 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5533 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5534 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5535 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5536 
\textbf{\huge h.stor32}&
5537 
\multicolumn{1}{c}{\textbf{\huge Store Word}}&
5538 
\textbf{\huge h.stor32}\\
5539 
\end{tabular}\par}
5540 
\bigskip{}
5541 
 
5542 
\vspace{10mm}
5543 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
5544 
\hline
5545 
15&
5546 
&
5547 
&
5548 
12&
5549 
11&
5550 
&
5551 
&
5552 
8&
5553 
7&
5554 
&
5555 
&
5556 
4&
5557 
3&
5558 
&
5559 
&
5560 
0\\
5561 
\hline
5562 
\multicolumn{4}{|c|}{opcode 0x6}&
5563 
\multicolumn{4}{c|}{N}&
5564 
\multicolumn{4}{c|}{A}&
5565 
\multicolumn{4}{c|}{B}\\
5566 
 
5567 
\hline
5568 
\multicolumn{4}{|c|}{4 bits}&
5569 
\multicolumn{4}{c|}{4 bits}&
5570 
\multicolumn{4}{c|}{4 bits}&
5571 
\multicolumn{4}{c|}{4 bits}\\
5572 
 
5573 
\hline
5574 
\end{tabular}\par}
5575 
\vspace{15mm}
5576 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5577 
\vspace{5mm}
5578 
\begin{quotation}
5579 
\texttt{\large h.stor32\ N(rA),rB}{\large \par}
5580 
\end{quotation}
5581 
\vspace{10mm}
5582 
\textbf{\LARGE Description:}{\LARGE \par}
5583 
\vspace{5mm}
5584 
\begin{quotation}
5585 
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The word in general register rB is stored to memory addressed by EA. }{\large \par}
5586 
\end{quotation}
5587 
\vspace{10mm}
5588 
\textbf{\LARGE Operation:}{\LARGE \par}
5589 
\vspace{5mm}
5590 
\begin{quotation}
5591 
EA <- exts(Immediate) + rA\\(EA){[}31:0{]} <- rB
5592 
\end{quotation}
5593 
\vspace{10mm}
5594 
\textbf{\LARGE Notes:}{\LARGE \par}
5595 
\vspace{5mm}
5596 
\begin{quotation}
5597 
 
5598 
\end{quotation}
5599 
\vspace{10mm}
5600 
\vfill
5601 
Class 2:
5602 
{\centering \begin{tabular}{|c|c|c|}
5603 
\hline
5604 
Architecture Level&
5605 
Execution Mode&
5606 
Implementation\\
5607 
\hline
5608 
Core CPU&User and Supervisor&Recommended\\
5609 
\hline
5610 
\end{tabular}\par}
5611 
 
5612 
 
5613 
 
5614 
\newpage
5615 
\vspace{10mm}
5616 
\lyxline{\small}\vspace{-1\parskip}
5617 
\vspace{10mm}
5618 
{\raggedright \begin{tabular}{ccc}
5619 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5620 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5621 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5622 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5623 
\textbf{\huge h.add32s}&
5624 
\multicolumn{1}{c}{\textbf{\huge Add Signed}}&
5625 
\textbf{\huge h.add32s}\\
5626 
\end{tabular}\par}
5627 
\bigskip{}
5628 
 
5629 
\vspace{10mm}
5630 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
5631 
\hline
5632 
15&
5633 
&
5634 
&
5635 
12&
5636 
11&
5637 
&
5638 
&
5639 
8&
5640 
7&
5641 
&
5642 
&
5643 
4&
5644 
3&
5645 
&
5646 
&
5647 
0\\
5648 
\hline
5649 
\multicolumn{4}{|c|}{opcode 0x7}&
5650 
\multicolumn{4}{c|}{D}&
5651 
\multicolumn{4}{c|}{A}&
5652 
\multicolumn{4}{c|}{B}\\
5653 
 
5654 
\hline
5655 
\multicolumn{4}{|c|}{4 bits}&
5656 
\multicolumn{4}{c|}{4 bits}&
5657 
\multicolumn{4}{c|}{4 bits}&
5658 
\multicolumn{4}{c|}{4 bits}\\
5659 
 
5660 
\hline
5661 
\end{tabular}\par}
5662 
\vspace{15mm}
5663 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5664 
\vspace{5mm}
5665 
\begin{quotation}
5666 
\texttt{\large h.add32s\ rA,rB,rD}{\large \par}
5667 
\end{quotation}
5668 
\vspace{10mm}
5669 
\textbf{\LARGE Description:}{\LARGE \par}
5670 
\vspace{5mm}
5671 
\begin{quotation}
5672 
\texttt{\large The contents of general register rC is added to the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
5673 
\end{quotation}
5674 
\vspace{10mm}
5675 
\textbf{\LARGE Operation:}{\LARGE \par}
5676 
\vspace{5mm}
5677 
\begin{quotation}
5678 
rA <- rB + rC
5679 
\end{quotation}
5680 
\vspace{10mm}
5681 
\textbf{\LARGE Notes:}{\LARGE \par}
5682 
\vspace{5mm}
5683 
\begin{quotation}
5684 
 
5685 
\end{quotation}
5686 
\vspace{10mm}
5687 
\vfill
5688 
Class 1:
5689 
{\centering \begin{tabular}{|c|c|c|}
5690 
\hline
5691 
Architecture Level&
5692 
Execution Mode&
5693 
Implementation\\
5694 
\hline
5695 
Core CPU&User and Supervisor&Mandatory always\\
5696 
\hline
5697 
\end{tabular}\par}
5698 
 
5699 
 
5700 
 
5701 
\newpage
5702 
\vspace{10mm}
5703 
\lyxline{\small}\vspace{-1\parskip}
5704 
\vspace{10mm}
5705 
{\raggedright \begin{tabular}{ccc}
5706 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5707 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5708 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5709 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5710 
\textbf{\huge h.immch32s}&
5711 
\multicolumn{1}{c}{\textbf{\huge Immediate Byte Signed}}&
5712 
\textbf{\huge h.immch32s}\\
5713 
\end{tabular}\par}
5714 
\bigskip{}
5715 
 
5716 
\vspace{10mm}
5717 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
5718 
\hline
5719 
15&
5720 
&
5721 
&
5722 
12&
5723 
11&
5724 
&
5725 
&
5726 
8&
5727 
7&
5728 
&
5729 
&
5730 
4&
5731 
3&
5732 
&
5733 
&
5734 
0\\
5735 
\hline
5736 
\multicolumn{4}{|c|}{opcode 0x8}&
5737 
\multicolumn{4}{c|}{M}&
5738 
\multicolumn{4}{c|}{A}&
5739 
\multicolumn{4}{c|}{M}\\
5740 
 
5741 
\hline
5742 
\multicolumn{4}{|c|}{4 bits}&
5743 
\multicolumn{4}{c|}{4 bits}&
5744 
\multicolumn{4}{c|}{4 bits}&
5745 
\multicolumn{4}{c|}{4 bits}\\
5746 
 
5747 
\hline
5748 
\end{tabular}\par}
5749 
\vspace{15mm}
5750 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5751 
\vspace{5mm}
5752 
\begin{quotation}
5753 
\texttt{\large h.immch32s\ rA,M}{\large \par}
5754 
\end{quotation}
5755 
\vspace{10mm}
5756 
\textbf{\LARGE Description:}{\LARGE \par}
5757 
\vspace{5mm}
5758 
\begin{quotation}
5759 
\texttt{\large 8 bit immediate is sign-extended to 32 bits and placed into general register rA.}{\large \par}
5760 
\end{quotation}
5761 
\vspace{10mm}
5762 
\textbf{\LARGE Operation:}{\LARGE \par}
5763 
\vspace{5mm}
5764 
\begin{quotation}
5765 
rA <- exts(Immediate)
5766 
\end{quotation}
5767 
\vspace{10mm}
5768 
\textbf{\LARGE Notes:}{\LARGE \par}
5769 
\vspace{5mm}
5770 
\begin{quotation}
5771 
 
5772 
\end{quotation}
5773 
\vspace{10mm}
5774 
\vfill
5775 
Class 2:
5776 
{\centering \begin{tabular}{|c|c|c|}
5777 
\hline
5778 
Architecture Level&
5779 
Execution Mode&
5780 
Implementation\\
5781 
\hline
5782 
Core CPU&User and Supervisor&Recommended\\
5783 
\hline
5784 
\end{tabular}\par}
5785 
 
5786 
 
5787 
 
5788 
\newpage
5789 
\vspace{10mm}
5790 
\lyxline{\small}\vspace{-1\parskip}
5791 
\vspace{10mm}
5792 
{\raggedright \begin{tabular}{ccc}
5793 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5794 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5795 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5796 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5797 
\textbf{\huge h.jal}&
5798 
\multicolumn{1}{c}{\textbf{\huge Jump and Link}}&
5799 
\textbf{\huge h.jal}\\
5800 
\end{tabular}\par}
5801 
\bigskip{}
5802 
 
5803 
\vspace{10mm}
5804 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
5805 
\hline
5806 
15&
5807 
&
5808 
&
5809 
12&
5810 
11&
5811 
&
5812 
&
5813 
&
5814 
&
5815 
&
5816 
&
5817 
&
5818 
&
5819 
&
5820 
&
5821 
0\\
5822 
\hline
5823 
\multicolumn{4}{|c|}{opcode 0x9}&
5824 
\multicolumn{12}{c|}{X}\\
5825 
 
5826 
\hline
5827 
\multicolumn{4}{|c|}{4 bits}&
5828 
\multicolumn{12}{c|}{12 bits}\\
5829 
 
5830 
\hline
5831 
\end{tabular}\par}
5832 
\vspace{15mm}
5833 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5834 
\vspace{5mm}
5835 
\begin{quotation}
5836 
\texttt{\large h.jal\ X}{\large \par}
5837 
\end{quotation}
5838 
\vspace{10mm}
5839 
\textbf{\LARGE Description:}{\LARGE \par}
5840 
\vspace{5mm}
5841 
\begin{quotation}
5842 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
5843 
\end{quotation}
5844 
\vspace{10mm}
5845 
\textbf{\LARGE Operation:}{\LARGE \par}
5846 
\vspace{5mm}
5847 
\begin{quotation}
5848 
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
5849 
\end{quotation}
5850 
\vspace{10mm}
5851 
\textbf{\LARGE Notes:}{\LARGE \par}
5852 
\vspace{5mm}
5853 
\begin{quotation}
5854 
 
5855 
\end{quotation}
5856 
\vspace{10mm}
5857 
\vfill
5858 
Class 2:
5859 
{\centering \begin{tabular}{|c|c|c|}
5860 
\hline
5861 
Architecture Level&
5862 
Execution Mode&
5863 
Implementation\\
5864 
\hline
5865 
Core CPU&User and Supervisor&Recommended\\
5866 
\hline
5867 
\end{tabular}\par}
5868 
 
5869 
 
5870 
 
5871 
\newpage
5872 
\vspace{10mm}
5873 
\lyxline{\small}\vspace{-1\parskip}
5874 
\vspace{10mm}
5875 
{\raggedright \begin{tabular}{ccc}
5876 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5877 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5878 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5879 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5880 
\textbf{\huge h.jal}&
5881 
\multicolumn{1}{c}{\textbf{\huge Jump and Link}}&
5882 
\textbf{\huge h.jal}\\
5883 
\end{tabular}\par}
5884 
\bigskip{}
5885 
 
5886 
\vspace{10mm}
5887 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
5888 
\hline
5889 
15&
5890 
&
5891 
&
5892 
12&
5893 
11&
5894 
&
5895 
&
5896 
&
5897 
&
5898 
&
5899 
&
5900 
&
5901 
&
5902 
&
5903 
&
5904 
0\\
5905 
\hline
5906 
\multicolumn{4}{|c|}{opcode 0xa}&
5907 
\multicolumn{12}{c|}{X}\\
5908 
 
5909 
\hline
5910 
\multicolumn{4}{|c|}{4 bits}&
5911 
\multicolumn{12}{c|}{12 bits}\\
5912 
 
5913 
\hline
5914 
\end{tabular}\par}
5915 
\vspace{15mm}
5916 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5917 
\vspace{5mm}
5918 
\begin{quotation}
5919 
\texttt{\large h.jal\ X}{\large \par}
5920 
\end{quotation}
5921 
\vspace{10mm}
5922 
\textbf{\LARGE Description:}{\LARGE \par}
5923 
\vspace{5mm}
5924 
\begin{quotation}
5925 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
5926 
\end{quotation}
5927 
\vspace{10mm}
5928 
\textbf{\LARGE Operation:}{\LARGE \par}
5929 
\vspace{5mm}
5930 
\begin{quotation}
5931 
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
5932 
\end{quotation}
5933 
\vspace{10mm}
5934 
\textbf{\LARGE Notes:}{\LARGE \par}
5935 
\vspace{5mm}
5936 
\begin{quotation}
5937 
 
5938 
\end{quotation}
5939 
\vspace{10mm}
5940 
\vfill
5941 
Class 2:
5942 
{\centering \begin{tabular}{|c|c|c|}
5943 
\hline
5944 
Architecture Level&
5945 
Execution Mode&
5946 
Implementation\\
5947 
\hline
5948 
Core CPU&User and Supervisor&Recommended\\
5949 
\hline
5950 
\end{tabular}\par}
5951 
 
5952 
 
5953 
 
5954 
\newpage
5955 
\vspace{10mm}
5956 
\lyxline{\small}\vspace{-1\parskip}
5957 
\vspace{10mm}
5958 
{\raggedright \begin{tabular}{ccc}
5959 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5960 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5961 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5962 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5963 
\textbf{\huge h.bnf}&
5964 
\multicolumn{1}{c}{\textbf{\huge Branch if No Flag}}&
5965 
\textbf{\huge h.bnf}\\
5966 
\end{tabular}\par}
5967 
\bigskip{}
5968 
 
5969 
\vspace{10mm}
5970 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
5971 
\hline
5972 
15&
5973 
&
5974 
&
5975 
12&
5976 
11&
5977 
&
5978 
&
5979 
&
5980 
&
5981 
&
5982 
&
5983 
&
5984 
&
5985 
&
5986 
&
5987 
0\\
5988 
\hline
5989 
\multicolumn{4}{|c|}{opcode 0xb}&
5990 
\multicolumn{12}{c|}{X}\\
5991 
 
5992 
\hline
5993 
\multicolumn{4}{|c|}{4 bits}&
5994 
\multicolumn{12}{c|}{12 bits}\\
5995 
 
5996 
\hline
5997 
\end{tabular}\par}
5998 
\vspace{15mm}
5999 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6000 
\vspace{5mm}
6001 
\begin{quotation}
6002 
\texttt{\large h.bnf\ X}{\large \par}
6003 
\end{quotation}
6004 
\vspace{10mm}
6005 
\textbf{\LARGE Description:}{\LARGE \par}
6006 
\vspace{5mm}
6007 
\begin{quotation}
6008 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is cleared, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
6009 
\end{quotation}
6010 
\vspace{10mm}
6011 
\textbf{\LARGE Operation:}{\LARGE \par}
6012 
\vspace{5mm}
6013 
\begin{quotation}
6014 
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared
6015 
\end{quotation}
6016 
\vspace{10mm}
6017 
\textbf{\LARGE Notes:}{\LARGE \par}
6018 
\vspace{5mm}
6019 
\begin{quotation}
6020 
 
6021 
\end{quotation}
6022 
\vspace{10mm}
6023 
\vfill
6024 
Class 2:
6025 
{\centering \begin{tabular}{|c|c|c|}
6026 
\hline
6027 
Architecture Level&
6028 
Execution Mode&
6029 
Implementation\\
6030 
\hline
6031 
Core CPU&User and Supervisor&Recommended\\
6032 
\hline
6033 
\end{tabular}\par}
6034 
 
6035 
 
6036 
 
6037 
\newpage
6038 
\vspace{10mm}
6039 
\lyxline{\small}\vspace{-1\parskip}
6040 
\vspace{10mm}
6041 
{\raggedright \begin{tabular}{ccc}
6042 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6043 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6044 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6045 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6046 
\textbf{\huge h.bf}&
6047 
\multicolumn{1}{c}{\textbf{\huge Branch if Flag}}&
6048 
\textbf{\huge h.bf}\\
6049 
\end{tabular}\par}
6050 
\bigskip{}
6051 
 
6052 
\vspace{10mm}
6053 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
6054 
\hline
6055 
15&
6056 
&
6057 
&
6058 
12&
6059 
11&
6060 
&
6061 
&
6062 
&
6063 
&
6064 
&
6065 
&
6066 
&
6067 
&
6068 
&
6069 
&
6070 
0\\
6071 
\hline
6072 
\multicolumn{4}{|c|}{opcode 0xc}&
6073 
\multicolumn{12}{c|}{X}\\
6074 
 
6075 
\hline
6076 
\multicolumn{4}{|c|}{4 bits}&
6077 
\multicolumn{12}{c|}{12 bits}\\
6078 
 
6079 
\hline
6080 
\end{tabular}\par}
6081 
\vspace{15mm}
6082 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6083 
\vspace{5mm}
6084 
\begin{quotation}
6085 
\texttt{\large h.bf\ X}{\large \par}
6086 
\end{quotation}
6087 
\vspace{10mm}
6088 
\textbf{\LARGE Description:}{\LARGE \par}
6089 
\vspace{5mm}
6090 
\begin{quotation}
6091 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is set, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
6092 
\end{quotation}
6093 
\vspace{10mm}
6094 
\textbf{\LARGE Operation:}{\LARGE \par}
6095 
\vspace{5mm}
6096 
\begin{quotation}
6097 
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set
6098 
\end{quotation}
6099 
\vspace{10mm}
6100 
\textbf{\LARGE Notes:}{\LARGE \par}
6101 
\vspace{5mm}
6102 
\begin{quotation}
6103 
 
6104 
\end{quotation}
6105 
\vspace{10mm}
6106 
\vfill
6107 
Class 2:
6108 
{\centering \begin{tabular}{|c|c|c|}
6109 
\hline
6110 
Architecture Level&
6111 
Execution Mode&
6112 
Implementation\\
6113 
\hline
6114 
Core CPU&User and Supervisor&Recommended\\
6115 
\hline
6116 
\end{tabular}\par}
6117 
 
6118 
 
6119 
 
6120 
\newpage
6121 
\vspace{10mm}
6122 
\lyxline{\small}\vspace{-1\parskip}
6123 
\vspace{10mm}
6124 
{\raggedright \begin{tabular}{ccc}
6125 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6126 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6127 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6128 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6129 
\textbf{\huge h.sched}&
6130 
\multicolumn{1}{c}{\textbf{\huge Schedule}}&
6131 
\textbf{\huge h.sched}\\
6132 
\end{tabular}\par}
6133 
\bigskip{}
6134 
 
6135 
\vspace{10mm}
6136 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
6137 
\hline
6138 
15&
6139 
&
6140 
&
6141 
12&
6142 
11&
6143 
&
6144 
&
6145 
&
6146 
&
6147 
&
6148 
&
6149 
&
6150 
&
6151 
&
6152 
&
6153 
0\\
6154 
\hline
6155 
\multicolumn{4}{|c|}{opcode 0xf}&
6156 
\multicolumn{12}{c|}{Z}\\
6157 
 
6158 
\hline
6159 
\multicolumn{4}{|c|}{4 bits}&
6160 
\multicolumn{12}{c|}{12 bits}\\
6161 
 
6162 
\hline
6163 
\end{tabular}\par}
6164 
\vspace{15mm}
6165 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6166 
\vspace{5mm}
6167 
\begin{quotation}
6168 
\texttt{\large h.sched\ Z}{\large \par}
6169 
\end{quotation}
6170 
\vspace{10mm}
6171 
\textbf{\LARGE Description:}{\LARGE \par}
6172 
\vspace{5mm}
6173 
\begin{quotation}
6174 
\texttt{\large Immediate carries static scheduling information about instruction scheduling. This information is generated by an optimizing compiler.}{\large \par}
6175 
\end{quotation}
6176 
\vspace{10mm}
6177 
\textbf{\LARGE Operation:}{\LARGE \par}
6178 
\vspace{5mm}
6179 
\begin{quotation}
6180 
 
6181 
\end{quotation}
6182 
\vspace{10mm}
6183 
\textbf{\LARGE Notes:}{\LARGE \par}
6184 
\vspace{5mm}
6185 
\begin{quotation}
6186 
 
6187 
\end{quotation}
6188 
\vspace{10mm}
6189 
\vfill
6190 
Class 3:
6191 
{\centering \begin{tabular}{|c|c|c|}
6192 
\hline
6193 
Architecture Level&
6194 
Execution Mode&
6195 
Implementation\\
6196 
\hline
6197 
Core CPU&User and Supervisor&Optional\\
6198 
\hline
6199 
\end{tabular}\par}
6200 
 
6201 
 
6202 
\end{document}

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