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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [alpha/] [gen_or1k_isa/] [tmp/] [isa.tex] - Blame information for rev 1765

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1 14 lampret 
%% This LaTeX-file was created by <root> Sun Nov  7 03:44:37 1999
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%% LyX 1.0 (C) 1995-1999 by Matthias Ettrich and the LyX Team
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%% Do not edit this file unless you know what you are doing.
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\documentclass[oneside]{amsbook}
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\geometry{verbose,a4paper,lmargin=20mm,rmargin=20mm}
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\makeatletter
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\usepackage[T1]{fontenc}
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\usepackage{a4}
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\pagestyle{fancy}
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\makeatletter
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\usepackage[T1]{fontenc}
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\makeatletter
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\makeatother
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\makeatother
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\makeatother
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\makeatother
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\begin{document}
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\vspace{50mm}\section{OpenRISC 1000 Instruction Set}
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Draft, Do not distribute
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\newpage
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\vspace{10mm}
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\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
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{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
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\textbf{\huge l.illegal}&
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\multicolumn{1}{c}{\textbf{\huge Illegal instruction}}&
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\textbf{\huge l.illegal}\\
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\end{tabular}\par}
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\bigskip{}
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\vspace{10mm}
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{\centering \begin{tabular}{|cccccccccccccccccccccccccccccccc|}
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\hline
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0\\
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\hline
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\multicolumn{32}{|c|}{opcode 0x0}\\
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\hline
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\multicolumn{32}{|c|}{32 bits}\\
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\hline
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\end{tabular}\par}
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\vspace{15mm}
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{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
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\vspace{5mm}
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\begin{quotation}
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\texttt{\large l.illegal\ }{\large \par}
129 
\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Description:}{\LARGE \par}
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\vspace{5mm}
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\begin{quotation}
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\texttt{\large The result of this instruction is always an illegal instruction exception.}{\large \par}
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\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Operation:}{\LARGE \par}
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\vspace{5mm}
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\begin{quotation}
140 
PC <- address of illegal instruction exception handler
141 
\end{quotation}
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\vspace{10mm}
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\textbf{\LARGE Notes:}{\LARGE \par}
144 
\vspace{5mm}
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\begin{quotation}
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147 
\end{quotation}
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\vspace{10mm}
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\vfill
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Class 1:
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{\centering \begin{tabular}{|c|c|c|}
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\hline
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Architecture Level&
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Execution Mode&
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Implementation\\
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\hline
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Core CPU&User and Supervisor&Mandatory always\\
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\hline
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\end{tabular}\par}
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161 
 
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\newpage
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\vspace{10mm}
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\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
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{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
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\textbf{\huge l.j}&
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\multicolumn{1}{c}{\textbf{\huge Jump}}&
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\textbf{\huge l.j}\\
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\end{tabular}\par}
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\bigskip{}
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\vspace{10mm}
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{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
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\hline
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0\\
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\hline
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\multicolumn{6}{|c|}{opcode 0x0}&
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\multicolumn{26}{c|}{X}\\
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\hline
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\multicolumn{6}{|c|}{6 bits}&
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\multicolumn{26}{c|}{26 bits}\\
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\hline
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\end{tabular}\par}
223 
\vspace{15mm}
224 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
225 
\vspace{5mm}
226 
\begin{quotation}
227 
\texttt{\large l.j\ X}{\large \par}
228 
\end{quotation}
229 
\vspace{10mm}
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\textbf{\LARGE Description:}{\LARGE \par}
231 
\vspace{5mm}
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\begin{quotation}
233 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
234 
\end{quotation}
235 
\vspace{10mm}
236 
\textbf{\LARGE Operation:}{\LARGE \par}
237 
\vspace{5mm}
238 
\begin{quotation}
239 
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
240 
\end{quotation}
241 
\vspace{10mm}
242 
\textbf{\LARGE Notes:}{\LARGE \par}
243 
\vspace{5mm}
244 
\begin{quotation}
245 
 
246 
\end{quotation}
247 
\vspace{10mm}
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\vfill
249 
Class 1:
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{\centering \begin{tabular}{|c|c|c|}
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\hline
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Architecture Level&
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Execution Mode&
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Implementation\\
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\hline
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Core CPU&User and Supervisor&Mandatory always\\
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\hline
258 
\end{tabular}\par}
259 
 
260 
 
261 
 
262 
\newpage
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\vspace{10mm}
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\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
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{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
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\textbf{\huge l.jal}&
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\multicolumn{1}{c}{\textbf{\huge Jump and Link}}&
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\textbf{\huge l.jal}\\
274 
\end{tabular}\par}
275 
\bigskip{}
276 
 
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\vspace{10mm}
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{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
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\hline
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31&
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0\\
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\hline
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\multicolumn{6}{|c|}{opcode 0x1}&
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\multicolumn{26}{c|}{X}\\
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\hline
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\multicolumn{6}{|c|}{6 bits}&
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\multicolumn{26}{c|}{26 bits}\\
319 
 
320 
\hline
321 
\end{tabular}\par}
322 
\vspace{15mm}
323 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
324 
\vspace{5mm}
325 
\begin{quotation}
326 
\texttt{\large l.jal\ X}{\large \par}
327 
\end{quotation}
328 
\vspace{10mm}
329 
\textbf{\LARGE Description:}{\LARGE \par}
330 
\vspace{5mm}
331 
\begin{quotation}
332 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
333 
\end{quotation}
334 
\vspace{10mm}
335 
\textbf{\LARGE Operation:}{\LARGE \par}
336 
\vspace{5mm}
337 
\begin{quotation}
338 
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
339 
\end{quotation}
340 
\vspace{10mm}
341 
\textbf{\LARGE Notes:}{\LARGE \par}
342 
\vspace{5mm}
343 
\begin{quotation}
344 
 
345 
\end{quotation}
346 
\vspace{10mm}
347 
\vfill
348 
Class 1:
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{\centering \begin{tabular}{|c|c|c|}
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\hline
351 
Architecture Level&
352 
Execution Mode&
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Implementation\\
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\hline
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Core CPU&User and Supervisor&Mandatory always\\
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\hline
357 
\end{tabular}\par}
358 
 
359 
 
360 
 
361 
\newpage
362 
\vspace{10mm}
363 
\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
365 
{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
370 
\textbf{\huge l.bnf}&
371 
\multicolumn{1}{c}{\textbf{\huge Branch if No Flag}}&
372 
\textbf{\huge l.bnf}\\
373 
\end{tabular}\par}
374 
\bigskip{}
375 
 
376 
\vspace{10mm}
377 
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
378 
\hline
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31&
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0\\
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\hline
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\multicolumn{6}{|c|}{opcode 0x2}&
413 
\multicolumn{26}{c|}{X}\\
414 
 
415 
\hline
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\multicolumn{6}{|c|}{6 bits}&
417 
\multicolumn{26}{c|}{26 bits}\\
418 
 
419 
\hline
420 
\end{tabular}\par}
421 
\vspace{15mm}
422 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
423 
\vspace{5mm}
424 
\begin{quotation}
425 
\texttt{\large l.bnf\ X}{\large \par}
426 
\end{quotation}
427 
\vspace{10mm}
428 
\textbf{\LARGE Description:}{\LARGE \par}
429 
\vspace{5mm}
430 
\begin{quotation}
431 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is cleared, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
432 
\end{quotation}
433 
\vspace{10mm}
434 
\textbf{\LARGE Operation:}{\LARGE \par}
435 
\vspace{5mm}
436 
\begin{quotation}
437 
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared
438 
\end{quotation}
439 
\vspace{10mm}
440 
\textbf{\LARGE Notes:}{\LARGE \par}
441 
\vspace{5mm}
442 
\begin{quotation}
443 
 
444 
\end{quotation}
445 
\vspace{10mm}
446 
\vfill
447 
Class 1:
448 
{\centering \begin{tabular}{|c|c|c|}
449 
\hline
450 
Architecture Level&
451 
Execution Mode&
452 
Implementation\\
453 
\hline
454 
Core CPU&User and Supervisor&Mandatory always\\
455 
\hline
456 
\end{tabular}\par}
457 
 
458 
 
459 
 
460 
\newpage
461 
\vspace{10mm}
462 
\lyxline{\small}\vspace{-1\parskip}
463 
\vspace{10mm}
464 
{\raggedright \begin{tabular}{ccc}
465 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
467 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
468 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
469 
\textbf{\huge l.bf}&
470 
\multicolumn{1}{c}{\textbf{\huge Branch if Flag}}&
471 
\textbf{\huge l.bf}\\
472 
\end{tabular}\par}
473 
\bigskip{}
474 
 
475 
\vspace{10mm}
476 
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
477 
\hline
478 
31&
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\hline
511 
\multicolumn{6}{|c|}{opcode 0x3}&
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\multicolumn{26}{c|}{X}\\
513 
 
514 
\hline
515 
\multicolumn{6}{|c|}{6 bits}&
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\multicolumn{26}{c|}{26 bits}\\
517 
 
518 
\hline
519 
\end{tabular}\par}
520 
\vspace{15mm}
521 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
522 
\vspace{5mm}
523 
\begin{quotation}
524 
\texttt{\large l.bf\ X}{\large \par}
525 
\end{quotation}
526 
\vspace{10mm}
527 
\textbf{\LARGE Description:}{\LARGE \par}
528 
\vspace{5mm}
529 
\begin{quotation}
530 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is set, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
531 
\end{quotation}
532 
\vspace{10mm}
533 
\textbf{\LARGE Operation:}{\LARGE \par}
534 
\vspace{5mm}
535 
\begin{quotation}
536 
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set
537 
\end{quotation}
538 
\vspace{10mm}
539 
\textbf{\LARGE Notes:}{\LARGE \par}
540 
\vspace{5mm}
541 
\begin{quotation}
542 
 
543 
\end{quotation}
544 
\vspace{10mm}
545 
\vfill
546 
Class 1:
547 
{\centering \begin{tabular}{|c|c|c|}
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\hline
549 
Architecture Level&
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Execution Mode&
551 
Implementation\\
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\hline
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Core CPU&User and Supervisor&Mandatory always\\
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\hline
555 
\end{tabular}\par}
556 
 
557 
 
558 
 
559 
\newpage
560 
\vspace{10mm}
561 
\lyxline{\small}\vspace{-1\parskip}
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\vspace{10mm}
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{\raggedright \begin{tabular}{ccc}
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\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
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Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
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\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
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\textbf{\huge l.bfnez}&
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\multicolumn{1}{c}{\textbf{\huge }}&
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\textbf{\huge l.bfnez}\\
571 
\end{tabular}\par}
572 
\bigskip{}
573 
 
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\vspace{10mm}
575 
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
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\hline
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0\\
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\hline
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\multicolumn{6}{|c|}{opcode 0x3}&
611 
\multicolumn{26}{c|}{X}\\
612 
 
613 
\hline
614 
\multicolumn{6}{|c|}{6 bits}&
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\multicolumn{26}{c|}{26 bits}\\
616 
 
617 
\hline
618 
\end{tabular}\par}
619 
\vspace{15mm}
620 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
621 
\vspace{5mm}
622 
\begin{quotation}
623 
\texttt{\large l.bfnez\ X}{\large \par}
624 
\end{quotation}
625 
\vspace{10mm}
626 
\textbf{\LARGE Description:}{\LARGE \par}
627 
\vspace{5mm}
628 
\begin{quotation}
629 
\texttt{\large }{\large \par}
630 
\end{quotation}
631 
\vspace{10mm}
632 
\textbf{\LARGE Operation:}{\LARGE \par}
633 
\vspace{5mm}
634 
\begin{quotation}
635 
 
636 
\end{quotation}
637 
\vspace{10mm}
638 
\textbf{\LARGE Notes:}{\LARGE \par}
639 
\vspace{5mm}
640 
\begin{quotation}
641 
 
642 
\end{quotation}
643 
\vspace{10mm}
644 
\vfill
645 
Class 0:
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{\centering \begin{tabular}{|c|c|c|}
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\hline
648 
Architecture Level&
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Execution Mode&
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Implementation\\
651 
\hline
652 
&&\\
653 
\hline
654 
\end{tabular}\par}
655 
 
656 
 
657 
 
658 
\newpage
659 
\vspace{10mm}
660 
\lyxline{\small}\vspace{-1\parskip}
661 
\vspace{10mm}
662 
{\raggedright \begin{tabular}{ccc}
663 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
664 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
665 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
666 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
667 
\textbf{\huge l.bfeqz}&
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\multicolumn{1}{c}{\textbf{\huge }}&
669 
\textbf{\huge l.bfeqz}\\
670 
\end{tabular}\par}
671 
\bigskip{}
672 
 
673 
\vspace{10mm}
674 
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
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\hline
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0\\
708 
\hline
709 
\multicolumn{6}{|c|}{opcode 0x2}&
710 
\multicolumn{26}{c|}{X}\\
711 
 
712 
\hline
713 
\multicolumn{6}{|c|}{6 bits}&
714 
\multicolumn{26}{c|}{26 bits}\\
715 
 
716 
\hline
717 
\end{tabular}\par}
718 
\vspace{15mm}
719 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
720 
\vspace{5mm}
721 
\begin{quotation}
722 
\texttt{\large l.bfeqz\ X}{\large \par}
723 
\end{quotation}
724 
\vspace{10mm}
725 
\textbf{\LARGE Description:}{\LARGE \par}
726 
\vspace{5mm}
727 
\begin{quotation}
728 
\texttt{\large }{\large \par}
729 
\end{quotation}
730 
\vspace{10mm}
731 
\textbf{\LARGE Operation:}{\LARGE \par}
732 
\vspace{5mm}
733 
\begin{quotation}
734 
 
735 
\end{quotation}
736 
\vspace{10mm}
737 
\textbf{\LARGE Notes:}{\LARGE \par}
738 
\vspace{5mm}
739 
\begin{quotation}
740 
 
741 
\end{quotation}
742 
\vspace{10mm}
743 
\vfill
744 
Class 0:
745 
{\centering \begin{tabular}{|c|c|c|}
746 
\hline
747 
Architecture Level&
748 
Execution Mode&
749 
Implementation\\
750 
\hline
751 
&&\\
752 
\hline
753 
\end{tabular}\par}
754 
 
755 
 
756 
 
757 
\newpage
758 
\vspace{10mm}
759 
\lyxline{\small}\vspace{-1\parskip}
760 
\vspace{10mm}
761 
{\raggedright \begin{tabular}{ccc}
762 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
763 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
764 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
765 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
766 
\textbf{\huge l.jmp}&
767 
\multicolumn{1}{c}{\textbf{\huge }}&
768 
\textbf{\huge l.jmp}\\
769 
\end{tabular}\par}
770 
\bigskip{}
771 
 
772 
\vspace{10mm}
773 
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
774 
\hline
775 
31&
776 
&
777 
&
778 
&
779 
&
780 
26&
781 
25&
782 
&
783 
&
784 
&
785 
&
786 
&
787 
&
788 
&
789 
&
790 
&
791 
&
792 
&
793 
&
794 
&
795 
&
796 
&
797 
&
798 
&
799 
&
800 
&
801 
&
802 
&
803 
&
804 
&
805 
&
806 
0\\
807 
\hline
808 
\multicolumn{6}{|c|}{opcode 0x0}&
809 
\multicolumn{26}{c|}{X}\\
810 
 
811 
\hline
812 
\multicolumn{6}{|c|}{6 bits}&
813 
\multicolumn{26}{c|}{26 bits}\\
814 
 
815 
\hline
816 
\end{tabular}\par}
817 
\vspace{15mm}
818 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
819 
\vspace{5mm}
820 
\begin{quotation}
821 
\texttt{\large l.jmp\ X}{\large \par}
822 
\end{quotation}
823 
\vspace{10mm}
824 
\textbf{\LARGE Description:}{\LARGE \par}
825 
\vspace{5mm}
826 
\begin{quotation}
827 
\texttt{\large }{\large \par}
828 
\end{quotation}
829 
\vspace{10mm}
830 
\textbf{\LARGE Operation:}{\LARGE \par}
831 
\vspace{5mm}
832 
\begin{quotation}
833 
 
834 
\end{quotation}
835 
\vspace{10mm}
836 
\textbf{\LARGE Notes:}{\LARGE \par}
837 
\vspace{5mm}
838 
\begin{quotation}
839 
 
840 
\end{quotation}
841 
\vspace{10mm}
842 
\vfill
843 
Class 0:
844 
{\centering \begin{tabular}{|c|c|c|}
845 
\hline
846 
Architecture Level&
847 
Execution Mode&
848 
Implementation\\
849 
\hline
850 
&&\\
851 
\hline
852 
\end{tabular}\par}
853 
 
854 
 
855 
 
856 
\newpage
857 
\vspace{10mm}
858 
\lyxline{\small}\vspace{-1\parskip}
859 
\vspace{10mm}
860 
{\raggedright \begin{tabular}{ccc}
861 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
862 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
863 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
864 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
865 
\textbf{\huge l.load32u}&
866 
\multicolumn{1}{c}{\textbf{\huge Load Word and Extend with Zero}}&
867 
\textbf{\huge l.load32u}\\
868 
\end{tabular}\par}
869 
\bigskip{}
870 
 
871 
\vspace{10mm}
872 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
873 
\hline
874 
31&
875 
&
876 
&
877 
&
878 
&
879 
&
880 
25&
881 
24&
882 
23&
883 
&
884 
&
885 
20&
886 
19&
887 
&
888 
&
889 
16&
890 
15&
891 
&
892 
&
893 
&
894 
&
895 
&
896 
&
897 
&
898 
&
899 
&
900 
&
901 
&
902 
&
903 
&
904 
&
905 
0\\
906 
\hline
907 
\multicolumn{7}{|c|}{opcode 0x8}&
908 
\multicolumn{1}{c|}{J}&
909 
\multicolumn{4}{c|}{A}&
910 
\multicolumn{4}{c|}{B}&
911 
\multicolumn{16}{c|}{J}\\
912 
 
913 
\hline
914 
\multicolumn{7}{|c|}{7 bits}&
915 
\multicolumn{1}{c|}{1 bits}&
916 
\multicolumn{4}{c|}{4 bits}&
917 
\multicolumn{4}{c|}{4 bits}&
918 
\multicolumn{16}{c|}{16 bits}\\
919 
 
920 
\hline
921 
\end{tabular}\par}
922 
\vspace{15mm}
923 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
924 
\vspace{5mm}
925 
\begin{quotation}
926 
\texttt{\large l.load32u\ rA,J(rB)}{\large \par}
927 
\end{quotation}
928 
\vspace{10mm}
929 
\textbf{\LARGE Description:}{\LARGE \par}
930 
\vspace{5mm}
931 
\begin{quotation}
932 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The word in memory addressed by EA is loaded into general register rA. }{\large \par}
933 
\end{quotation}
934 
\vspace{10mm}
935 
\textbf{\LARGE Operation:}{\LARGE \par}
936 
\vspace{5mm}
937 
\begin{quotation}
938 
EA <- exts(Immediate) + rB\\rA <- (EA){[}31:0{]}
939 
\end{quotation}
940 
\vspace{10mm}
941 
\textbf{\LARGE Notes:}{\LARGE \par}
942 
\vspace{5mm}
943 
\begin{quotation}
944 
 
945 
\end{quotation}
946 
\vspace{10mm}
947 
\vfill
948 
Class 1:
949 
{\centering \begin{tabular}{|c|c|c|}
950 
\hline
951 
Architecture Level&
952 
Execution Mode&
953 
Implementation\\
954 
\hline
955 
Core CPU&User and Supervisor&Mandatory always\\
956 
\hline
957 
\end{tabular}\par}
958 
 
959 
 
960 
 
961 
\newpage
962 
\vspace{10mm}
963 
\lyxline{\small}\vspace{-1\parskip}
964 
\vspace{10mm}
965 
{\raggedright \begin{tabular}{ccc}
966 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
967 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
968 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
969 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
970 
\textbf{\huge l.load16u}&
971 
\multicolumn{1}{c}{\textbf{\huge Load Half Word and Extend with Zero}}&
972 
\textbf{\huge l.load16u}\\
973 
\end{tabular}\par}
974 
\bigskip{}
975 
 
976 
\vspace{10mm}
977 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
978 
\hline
979 
31&
980 
&
981 
&
982 
&
983 
&
984 
&
985 
25&
986 
24&
987 
23&
988 
&
989 
&
990 
20&
991 
19&
992 
&
993 
&
994 
16&
995 
15&
996 
&
997 
&
998 
&
999 
&
1000 
&
1001 
&
1002 
&
1003 
&
1004 
&
1005 
&
1006 
&
1007 
&
1008 
&
1009 
&
1010 
0\\
1011 
\hline
1012 
\multicolumn{7}{|c|}{opcode 0x9}&
1013 
\multicolumn{1}{c|}{J}&
1014 
\multicolumn{4}{c|}{A}&
1015 
\multicolumn{4}{c|}{B}&
1016 
\multicolumn{16}{c|}{J}\\
1017 
 
1018 
\hline
1019 
\multicolumn{7}{|c|}{7 bits}&
1020 
\multicolumn{1}{c|}{1 bits}&
1021 
\multicolumn{4}{c|}{4 bits}&
1022 
\multicolumn{4}{c|}{4 bits}&
1023 
\multicolumn{16}{c|}{16 bits}\\
1024 
 
1025 
\hline
1026 
\end{tabular}\par}
1027 
\vspace{15mm}
1028 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1029 
\vspace{5mm}
1030 
\begin{quotation}
1031 
\texttt{\large l.load16u\ rA,J(rB)}{\large \par}
1032 
\end{quotation}
1033 
\vspace{10mm}
1034 
\textbf{\LARGE Description:}{\LARGE \par}
1035 
\vspace{5mm}
1036 
\begin{quotation}
1037 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The half word in memory addressed by EA is loaded into the low-order 16 bits of general register rA. High-order 16 bits of general register rA are replaced with zero.}{\large \par}
1038 
\end{quotation}
1039 
\vspace{10mm}
1040 
\textbf{\LARGE Operation:}{\LARGE \par}
1041 
\vspace{5mm}
1042 
\begin{quotation}
1043 
EA <- exts(Immediate) + rB\\rA{[}15:0{]} <- (EA){[}15:0{]}\\rA{[}31:16{]} <- 0
1044 
\end{quotation}
1045 
\vspace{10mm}
1046 
\textbf{\LARGE Notes:}{\LARGE \par}
1047 
\vspace{5mm}
1048 
\begin{quotation}
1049 
 
1050 
\end{quotation}
1051 
\vspace{10mm}
1052 
\vfill
1053 
Class 1:
1054 
{\centering \begin{tabular}{|c|c|c|}
1055 
\hline
1056 
Architecture Level&
1057 
Execution Mode&
1058 
Implementation\\
1059 
\hline
1060 
Core CPU&User and Supervisor&Mandatory always\\
1061 
\hline
1062 
\end{tabular}\par}
1063 
 
1064 
 
1065 
 
1066 
\newpage
1067 
\vspace{10mm}
1068 
\lyxline{\small}\vspace{-1\parskip}
1069 
\vspace{10mm}
1070 
{\raggedright \begin{tabular}{ccc}
1071 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1072 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1073 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1074 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1075 
\textbf{\huge l.load16s}&
1076 
\multicolumn{1}{c}{\textbf{\huge Load Half Word and Extend with Sign}}&
1077 
\textbf{\huge l.load16s}\\
1078 
\end{tabular}\par}
1079 
\bigskip{}
1080 
 
1081 
\vspace{10mm}
1082 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1083 
\hline
1084 
31&
1085 
&
1086 
&
1087 
&
1088 
&
1089 
&
1090 
25&
1091 
24&
1092 
23&
1093 
&
1094 
&
1095 
20&
1096 
19&
1097 
&
1098 
&
1099 
16&
1100 
15&
1101 
&
1102 
&
1103 
&
1104 
&
1105 
&
1106 
&
1107 
&
1108 
&
1109 
&
1110 
&
1111 
&
1112 
&
1113 
&
1114 
&
1115 
0\\
1116 
\hline
1117 
\multicolumn{7}{|c|}{opcode 0xa}&
1118 
\multicolumn{1}{c|}{J}&
1119 
\multicolumn{4}{c|}{A}&
1120 
\multicolumn{4}{c|}{B}&
1121 
\multicolumn{16}{c|}{J}\\
1122 
 
1123 
\hline
1124 
\multicolumn{7}{|c|}{7 bits}&
1125 
\multicolumn{1}{c|}{1 bits}&
1126 
\multicolumn{4}{c|}{4 bits}&
1127 
\multicolumn{4}{c|}{4 bits}&
1128 
\multicolumn{16}{c|}{16 bits}\\
1129 
 
1130 
\hline
1131 
\end{tabular}\par}
1132 
\vspace{15mm}
1133 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1134 
\vspace{5mm}
1135 
\begin{quotation}
1136 
\texttt{\large l.load16s\ rA,J(rB)}{\large \par}
1137 
\end{quotation}
1138 
\vspace{10mm}
1139 
\textbf{\LARGE Description:}{\LARGE \par}
1140 
\vspace{5mm}
1141 
\begin{quotation}
1142 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The half word in memory addressed by EA is loaded into the low-order 16 bits of general register rA. High-order 16 bits of general register rA are replaced with bit 15 of the loaded value.}{\large \par}
1143 
\end{quotation}
1144 
\vspace{10mm}
1145 
\textbf{\LARGE Operation:}{\LARGE \par}
1146 
\vspace{5mm}
1147 
\begin{quotation}
1148 
EA <- exts(Immediate) + rB\\rA{[}15:0{]} <- (EA){[}15:0{]}\\rA{[}31:16{]} <- rA{[}15{]}
1149 
\end{quotation}
1150 
\vspace{10mm}
1151 
\textbf{\LARGE Notes:}{\LARGE \par}
1152 
\vspace{5mm}
1153 
\begin{quotation}
1154 
 
1155 
\end{quotation}
1156 
\vspace{10mm}
1157 
\vfill
1158 
Class 1:
1159 
{\centering \begin{tabular}{|c|c|c|}
1160 
\hline
1161 
Architecture Level&
1162 
Execution Mode&
1163 
Implementation\\
1164 
\hline
1165 
Core CPU&User and Supervisor&Mandatory always\\
1166 
\hline
1167 
\end{tabular}\par}
1168 
 
1169 
 
1170 
 
1171 
\newpage
1172 
\vspace{10mm}
1173 
\lyxline{\small}\vspace{-1\parskip}
1174 
\vspace{10mm}
1175 
{\raggedright \begin{tabular}{ccc}
1176 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1177 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1178 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1179 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1180 
\textbf{\huge l.load8u}&
1181 
\multicolumn{1}{c}{\textbf{\huge Load Byte and Extend with Zero}}&
1182 
\textbf{\huge l.load8u}\\
1183 
\end{tabular}\par}
1184 
\bigskip{}
1185 
 
1186 
\vspace{10mm}
1187 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1188 
\hline
1189 
31&
1190 
&
1191 
&
1192 
&
1193 
&
1194 
&
1195 
25&
1196 
24&
1197 
23&
1198 
&
1199 
&
1200 
20&
1201 
19&
1202 
&
1203 
&
1204 
16&
1205 
15&
1206 
&
1207 
&
1208 
&
1209 
&
1210 
&
1211 
&
1212 
&
1213 
&
1214 
&
1215 
&
1216 
&
1217 
&
1218 
&
1219 
&
1220 
0\\
1221 
\hline
1222 
\multicolumn{7}{|c|}{opcode 0xb}&
1223 
\multicolumn{1}{c|}{J}&
1224 
\multicolumn{4}{c|}{A}&
1225 
\multicolumn{4}{c|}{B}&
1226 
\multicolumn{16}{c|}{J}\\
1227 
 
1228 
\hline
1229 
\multicolumn{7}{|c|}{7 bits}&
1230 
\multicolumn{1}{c|}{1 bits}&
1231 
\multicolumn{4}{c|}{4 bits}&
1232 
\multicolumn{4}{c|}{4 bits}&
1233 
\multicolumn{16}{c|}{16 bits}\\
1234 
 
1235 
\hline
1236 
\end{tabular}\par}
1237 
\vspace{15mm}
1238 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1239 
\vspace{5mm}
1240 
\begin{quotation}
1241 
\texttt{\large l.load8u\ rA,J(rB)}{\large \par}
1242 
\end{quotation}
1243 
\vspace{10mm}
1244 
\textbf{\LARGE Description:}{\LARGE \par}
1245 
\vspace{5mm}
1246 
\begin{quotation}
1247 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The byte in memory addressed by EA is loaded into the low-order eight bits of general register rA. High-order 24 bits of general register rA are replaced with zero.}{\large \par}
1248 
\end{quotation}
1249 
\vspace{10mm}
1250 
\textbf{\LARGE Operation:}{\LARGE \par}
1251 
\vspace{5mm}
1252 
\begin{quotation}
1253 
EA <- exts(Immediate) + rB\\rA{[}7:0{]} <- (EA){[}7:0{]}\\rA{[}31:8{]} <- 0
1254 
\end{quotation}
1255 
\vspace{10mm}
1256 
\textbf{\LARGE Notes:}{\LARGE \par}
1257 
\vspace{5mm}
1258 
\begin{quotation}
1259 
 
1260 
\end{quotation}
1261 
\vspace{10mm}
1262 
\vfill
1263 
Class 1:
1264 
{\centering \begin{tabular}{|c|c|c|}
1265 
\hline
1266 
Architecture Level&
1267 
Execution Mode&
1268 
Implementation\\
1269 
\hline
1270 
Core CPU&User and Supervisor&Mandatory always\\
1271 
\hline
1272 
\end{tabular}\par}
1273 
 
1274 
 
1275 
 
1276 
\newpage
1277 
\vspace{10mm}
1278 
\lyxline{\small}\vspace{-1\parskip}
1279 
\vspace{10mm}
1280 
{\raggedright \begin{tabular}{ccc}
1281 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1282 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1283 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1284 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1285 
\textbf{\huge l.load8s}&
1286 
\multicolumn{1}{c}{\textbf{\huge Load Byte and Extend with Sign}}&
1287 
\textbf{\huge l.load8s}\\
1288 
\end{tabular}\par}
1289 
\bigskip{}
1290 
 
1291 
\vspace{10mm}
1292 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1293 
\hline
1294 
31&
1295 
&
1296 
&
1297 
&
1298 
&
1299 
&
1300 
25&
1301 
24&
1302 
23&
1303 
&
1304 
&
1305 
20&
1306 
19&
1307 
&
1308 
&
1309 
16&
1310 
15&
1311 
&
1312 
&
1313 
&
1314 
&
1315 
&
1316 
&
1317 
&
1318 
&
1319 
&
1320 
&
1321 
&
1322 
&
1323 
&
1324 
&
1325 
0\\
1326 
\hline
1327 
\multicolumn{7}{|c|}{opcode 0xc}&
1328 
\multicolumn{1}{c|}{J}&
1329 
\multicolumn{4}{c|}{A}&
1330 
\multicolumn{4}{c|}{B}&
1331 
\multicolumn{16}{c|}{J}\\
1332 
 
1333 
\hline
1334 
\multicolumn{7}{|c|}{7 bits}&
1335 
\multicolumn{1}{c|}{1 bits}&
1336 
\multicolumn{4}{c|}{4 bits}&
1337 
\multicolumn{4}{c|}{4 bits}&
1338 
\multicolumn{16}{c|}{16 bits}\\
1339 
 
1340 
\hline
1341 
\end{tabular}\par}
1342 
\vspace{15mm}
1343 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1344 
\vspace{5mm}
1345 
\begin{quotation}
1346 
\texttt{\large l.load8s\ rA,J(rB)}{\large \par}
1347 
\end{quotation}
1348 
\vspace{10mm}
1349 
\textbf{\LARGE Description:}{\LARGE \par}
1350 
\vspace{5mm}
1351 
\begin{quotation}
1352 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The byte in memory addressed by EA is loaded into the low-order eight bits of general register rA. High-order 24 bits of general register rA are replaced with bit 7 of the loaded value.}{\large \par}
1353 
\end{quotation}
1354 
\vspace{10mm}
1355 
\textbf{\LARGE Operation:}{\LARGE \par}
1356 
\vspace{5mm}
1357 
\begin{quotation}
1358 
EA <- exts(Immediate) + rB\\rA{[}7:0{]} <- (EA){[}7:0{]}\\rA{[}31:8{]} <- rA{[}8{]}
1359 
\end{quotation}
1360 
\vspace{10mm}
1361 
\textbf{\LARGE Notes:}{\LARGE \par}
1362 
\vspace{5mm}
1363 
\begin{quotation}
1364 
 
1365 
\end{quotation}
1366 
\vspace{10mm}
1367 
\vfill
1368 
Class 1:
1369 
{\centering \begin{tabular}{|c|c|c|}
1370 
\hline
1371 
Architecture Level&
1372 
Execution Mode&
1373 
Implementation\\
1374 
\hline
1375 
Core CPU&User and Supervisor&Mandatory always\\
1376 
\hline
1377 
\end{tabular}\par}
1378 
 
1379 
 
1380 
 
1381 
\newpage
1382 
\vspace{10mm}
1383 
\lyxline{\small}\vspace{-1\parskip}
1384 
\vspace{10mm}
1385 
{\raggedright \begin{tabular}{ccc}
1386 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1387 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1388 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1389 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1390 
\textbf{\huge l.stor32}&
1391 
\multicolumn{1}{c}{\textbf{\huge Store Word}}&
1392 
\textbf{\huge l.stor32}\\
1393 
\end{tabular}\par}
1394 
\bigskip{}
1395 
 
1396 
\vspace{10mm}
1397 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1398 
\hline
1399 
31&
1400 
&
1401 
&
1402 
&
1403 
&
1404 
&
1405 
25&
1406 
24&
1407 
23&
1408 
&
1409 
&
1410 
20&
1411 
19&
1412 
&
1413 
&
1414 
16&
1415 
15&
1416 
&
1417 
&
1418 
&
1419 
&
1420 
&
1421 
&
1422 
&
1423 
&
1424 
&
1425 
&
1426 
&
1427 
&
1428 
&
1429 
&
1430 
0\\
1431 
\hline
1432 
\multicolumn{7}{|c|}{opcode 0xd}&
1433 
\multicolumn{1}{c|}{J}&
1434 
\multicolumn{4}{c|}{A}&
1435 
\multicolumn{4}{c|}{B}&
1436 
\multicolumn{16}{c|}{J}\\
1437 
 
1438 
\hline
1439 
\multicolumn{7}{|c|}{7 bits}&
1440 
\multicolumn{1}{c|}{1 bits}&
1441 
\multicolumn{4}{c|}{4 bits}&
1442 
\multicolumn{4}{c|}{4 bits}&
1443 
\multicolumn{16}{c|}{16 bits}\\
1444 
 
1445 
\hline
1446 
\end{tabular}\par}
1447 
\vspace{15mm}
1448 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1449 
\vspace{5mm}
1450 
\begin{quotation}
1451 
\texttt{\large l.stor32\ J(rA),rB}{\large \par}
1452 
\end{quotation}
1453 
\vspace{10mm}
1454 
\textbf{\LARGE Description:}{\LARGE \par}
1455 
\vspace{5mm}
1456 
\begin{quotation}
1457 
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The word in general register rB is stored to memory addressed by EA. }{\large \par}
1458 
\end{quotation}
1459 
\vspace{10mm}
1460 
\textbf{\LARGE Operation:}{\LARGE \par}
1461 
\vspace{5mm}
1462 
\begin{quotation}
1463 
EA <- exts(Immediate) + rA\\(EA){[}31:0{]} <- rB
1464 
\end{quotation}
1465 
\vspace{10mm}
1466 
\textbf{\LARGE Notes:}{\LARGE \par}
1467 
\vspace{5mm}
1468 
\begin{quotation}
1469 
 
1470 
\end{quotation}
1471 
\vspace{10mm}
1472 
\vfill
1473 
Class 1:
1474 
{\centering \begin{tabular}{|c|c|c|}
1475 
\hline
1476 
Architecture Level&
1477 
Execution Mode&
1478 
Implementation\\
1479 
\hline
1480 
Core CPU&User and Supervisor&Mandatory always\\
1481 
\hline
1482 
\end{tabular}\par}
1483 
 
1484 
 
1485 
 
1486 
\newpage
1487 
\vspace{10mm}
1488 
\lyxline{\small}\vspace{-1\parskip}
1489 
\vspace{10mm}
1490 
{\raggedright \begin{tabular}{ccc}
1491 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1492 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1493 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1494 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1495 
\textbf{\huge l.stor16}&
1496 
\multicolumn{1}{c}{\textbf{\huge Store Half Word}}&
1497 
\textbf{\huge l.stor16}\\
1498 
\end{tabular}\par}
1499 
\bigskip{}
1500 
 
1501 
\vspace{10mm}
1502 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1503 
\hline
1504 
31&
1505 
&
1506 
&
1507 
&
1508 
&
1509 
&
1510 
25&
1511 
24&
1512 
23&
1513 
&
1514 
&
1515 
20&
1516 
19&
1517 
&
1518 
&
1519 
16&
1520 
15&
1521 
&
1522 
&
1523 
&
1524 
&
1525 
&
1526 
&
1527 
&
1528 
&
1529 
&
1530 
&
1531 
&
1532 
&
1533 
&
1534 
&
1535 
0\\
1536 
\hline
1537 
\multicolumn{7}{|c|}{opcode 0xe}&
1538 
\multicolumn{1}{c|}{J}&
1539 
\multicolumn{4}{c|}{A}&
1540 
\multicolumn{4}{c|}{B}&
1541 
\multicolumn{16}{c|}{J}\\
1542 
 
1543 
\hline
1544 
\multicolumn{7}{|c|}{7 bits}&
1545 
\multicolumn{1}{c|}{1 bits}&
1546 
\multicolumn{4}{c|}{4 bits}&
1547 
\multicolumn{4}{c|}{4 bits}&
1548 
\multicolumn{16}{c|}{16 bits}\\
1549 
 
1550 
\hline
1551 
\end{tabular}\par}
1552 
\vspace{15mm}
1553 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1554 
\vspace{5mm}
1555 
\begin{quotation}
1556 
\texttt{\large l.stor16\ J(rA),rB}{\large \par}
1557 
\end{quotation}
1558 
\vspace{10mm}
1559 
\textbf{\LARGE Description:}{\LARGE \par}
1560 
\vspace{5mm}
1561 
\begin{quotation}
1562 
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The low-order 16 bits of general register rB are stored to memory addressed by EA. }{\large \par}
1563 
\end{quotation}
1564 
\vspace{10mm}
1565 
\textbf{\LARGE Operation:}{\LARGE \par}
1566 
\vspace{5mm}
1567 
\begin{quotation}
1568 
EA <- exts(Immediate) + rA\\(EA){[}15:0{]} <- rB{[}15:0{]}
1569 
\end{quotation}
1570 
\vspace{10mm}
1571 
\textbf{\LARGE Notes:}{\LARGE \par}
1572 
\vspace{5mm}
1573 
\begin{quotation}
1574 
 
1575 
\end{quotation}
1576 
\vspace{10mm}
1577 
\vfill
1578 
Class 1:
1579 
{\centering \begin{tabular}{|c|c|c|}
1580 
\hline
1581 
Architecture Level&
1582 
Execution Mode&
1583 
Implementation\\
1584 
\hline
1585 
Core CPU&User and Supervisor&Mandatory always\\
1586 
\hline
1587 
\end{tabular}\par}
1588 
 
1589 
 
1590 
 
1591 
\newpage
1592 
\vspace{10mm}
1593 
\lyxline{\small}\vspace{-1\parskip}
1594 
\vspace{10mm}
1595 
{\raggedright \begin{tabular}{ccc}
1596 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1597 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1598 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1599 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1600 
\textbf{\huge l.stor8}&
1601 
\multicolumn{1}{c}{\textbf{\huge Store Byte}}&
1602 
\textbf{\huge l.stor8}\\
1603 
\end{tabular}\par}
1604 
\bigskip{}
1605 
 
1606 
\vspace{10mm}
1607 
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
1608 
\hline
1609 
31&
1610 
&
1611 
&
1612 
&
1613 
&
1614 
&
1615 
25&
1616 
24&
1617 
23&
1618 
&
1619 
&
1620 
20&
1621 
19&
1622 
&
1623 
&
1624 
16&
1625 
15&
1626 
&
1627 
&
1628 
&
1629 
&
1630 
&
1631 
&
1632 
&
1633 
&
1634 
&
1635 
&
1636 
&
1637 
&
1638 
&
1639 
&
1640 
0\\
1641 
\hline
1642 
\multicolumn{7}{|c|}{opcode 0xf}&
1643 
\multicolumn{1}{c|}{J}&
1644 
\multicolumn{4}{c|}{A}&
1645 
\multicolumn{4}{c|}{B}&
1646 
\multicolumn{16}{c|}{J}\\
1647 
 
1648 
\hline
1649 
\multicolumn{7}{|c|}{7 bits}&
1650 
\multicolumn{1}{c|}{1 bits}&
1651 
\multicolumn{4}{c|}{4 bits}&
1652 
\multicolumn{4}{c|}{4 bits}&
1653 
\multicolumn{16}{c|}{16 bits}\\
1654 
 
1655 
\hline
1656 
\end{tabular}\par}
1657 
\vspace{15mm}
1658 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1659 
\vspace{5mm}
1660 
\begin{quotation}
1661 
\texttt{\large l.stor8\ J(rA),rB}{\large \par}
1662 
\end{quotation}
1663 
\vspace{10mm}
1664 
\textbf{\LARGE Description:}{\LARGE \par}
1665 
\vspace{5mm}
1666 
\begin{quotation}
1667 
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The low-order 8 bits of general register rB are stored to memory addressed by EA. }{\large \par}
1668 
\end{quotation}
1669 
\vspace{10mm}
1670 
\textbf{\LARGE Operation:}{\LARGE \par}
1671 
\vspace{5mm}
1672 
\begin{quotation}
1673 
EA <- exts(Immediate) + rA\\(EA){[}7:0{]} <- rB{[}7:0{]}
1674 
\end{quotation}
1675 
\vspace{10mm}
1676 
\textbf{\LARGE Notes:}{\LARGE \par}
1677 
\vspace{5mm}
1678 
\begin{quotation}
1679 
 
1680 
\end{quotation}
1681 
\vspace{10mm}
1682 
\vfill
1683 
Class 1:
1684 
{\centering \begin{tabular}{|c|c|c|}
1685 
\hline
1686 
Architecture Level&
1687 
Execution Mode&
1688 
Implementation\\
1689 
\hline
1690 
Core CPU&User and Supervisor&Mandatory always\\
1691 
\hline
1692 
\end{tabular}\par}
1693 
 
1694 
 
1695 
 
1696 
\newpage
1697 
\vspace{10mm}
1698 
\lyxline{\small}\vspace{-1\parskip}
1699 
\vspace{10mm}
1700 
{\raggedright \begin{tabular}{ccc}
1701 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1702 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1703 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1704 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1705 
\textbf{\huge l.addi32s}&
1706 
\multicolumn{1}{c}{\textbf{\huge Add Immediate Signed}}&
1707 
\textbf{\huge l.addi32s}\\
1708 
\end{tabular}\par}
1709 
\bigskip{}
1710 
 
1711 
\vspace{10mm}
1712 
{\centering \begin{tabular}{|cccccc|cc|cccc|cccc|cccccccccccccccc|}
1713 
\hline
1714 
31&
1715 
&
1716 
&
1717 
&
1718 
&
1719 
26&
1720 
25&
1721 
24&
1722 
23&
1723 
&
1724 
&
1725 
20&
1726 
19&
1727 
&
1728 
&
1729 
16&
1730 
15&
1731 
&
1732 
&
1733 
&
1734 
&
1735 
&
1736 
&
1737 
&
1738 
&
1739 
&
1740 
&
1741 
&
1742 
&
1743 
&
1744 
&
1745 
0\\
1746 
\hline
1747 
\multicolumn{6}{|c|}{opcode 0x8}&
1748 
\multicolumn{2}{c|}{K}&
1749 
\multicolumn{4}{c|}{A}&
1750 
\multicolumn{4}{c|}{B}&
1751 
\multicolumn{16}{c|}{K}\\
1752 
 
1753 
\hline
1754 
\multicolumn{6}{|c|}{6 bits}&
1755 
\multicolumn{2}{c|}{2 bits}&
1756 
\multicolumn{4}{c|}{4 bits}&
1757 
\multicolumn{4}{c|}{4 bits}&
1758 
\multicolumn{16}{c|}{16 bits}\\
1759 
 
1760 
\hline
1761 
\end{tabular}\par}
1762 
\vspace{15mm}
1763 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1764 
\vspace{5mm}
1765 
\begin{quotation}
1766 
\texttt{\large l.addi32s\ rA,rB,K}{\large \par}
1767 
\end{quotation}
1768 
\vspace{10mm}
1769 
\textbf{\LARGE Description:}{\LARGE \par}
1770 
\vspace{5mm}
1771 
\begin{quotation}
1772 
\texttt{\large Immediate is signed-extended and added to the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
1773 
\end{quotation}
1774 
\vspace{10mm}
1775 
\textbf{\LARGE Operation:}{\LARGE \par}
1776 
\vspace{5mm}
1777 
\begin{quotation}
1778 
rA <- rB + exts(Immediate)
1779 
\end{quotation}
1780 
\vspace{10mm}
1781 
\textbf{\LARGE Notes:}{\LARGE \par}
1782 
\vspace{5mm}
1783 
\begin{quotation}
1784 
 
1785 
\end{quotation}
1786 
\vspace{10mm}
1787 
\vfill
1788 
Class 1:
1789 
{\centering \begin{tabular}{|c|c|c|}
1790 
\hline
1791 
Architecture Level&
1792 
Execution Mode&
1793 
Implementation\\
1794 
\hline
1795 
Core CPU&User and Supervisor&Mandatory always\\
1796 
\hline
1797 
\end{tabular}\par}
1798 
 
1799 
 
1800 
 
1801 
\newpage
1802 
\vspace{10mm}
1803 
\lyxline{\small}\vspace{-1\parskip}
1804 
\vspace{10mm}
1805 
{\raggedright \begin{tabular}{ccc}
1806 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1807 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1808 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1809 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1810 
\textbf{\huge l.subi32s}&
1811 
\multicolumn{1}{c}{\textbf{\huge Subtract Immediate Signed}}&
1812 
\textbf{\huge l.subi32s}\\
1813 
\end{tabular}\par}
1814 
\bigskip{}
1815 
 
1816 
\vspace{10mm}
1817 
{\centering \begin{tabular}{|cccccc|cc|cccc|cccc|cccccccccccccccc|}
1818 
\hline
1819 
31&
1820 
&
1821 
&
1822 
&
1823 
&
1824 
26&
1825 
25&
1826 
24&
1827 
23&
1828 
&
1829 
&
1830 
20&
1831 
19&
1832 
&
1833 
&
1834 
16&
1835 
15&
1836 
&
1837 
&
1838 
&
1839 
&
1840 
&
1841 
&
1842 
&
1843 
&
1844 
&
1845 
&
1846 
&
1847 
&
1848 
&
1849 
&
1850 
0\\
1851 
\hline
1852 
\multicolumn{6}{|c|}{opcode 0x9}&
1853 
\multicolumn{2}{c|}{K}&
1854 
\multicolumn{4}{c|}{A}&
1855 
\multicolumn{4}{c|}{B}&
1856 
\multicolumn{16}{c|}{K}\\
1857 
 
1858 
\hline
1859 
\multicolumn{6}{|c|}{6 bits}&
1860 
\multicolumn{2}{c|}{2 bits}&
1861 
\multicolumn{4}{c|}{4 bits}&
1862 
\multicolumn{4}{c|}{4 bits}&
1863 
\multicolumn{16}{c|}{16 bits}\\
1864 
 
1865 
\hline
1866 
\end{tabular}\par}
1867 
\vspace{15mm}
1868 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1869 
\vspace{5mm}
1870 
\begin{quotation}
1871 
\texttt{\large l.subi32s\ rA,rB,K}{\large \par}
1872 
\end{quotation}
1873 
\vspace{10mm}
1874 
\textbf{\LARGE Description:}{\LARGE \par}
1875 
\vspace{5mm}
1876 
\begin{quotation}
1877 
\texttt{\large Immediate is signed-extended and subtracted from the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
1878 
\end{quotation}
1879 
\vspace{10mm}
1880 
\textbf{\LARGE Operation:}{\LARGE \par}
1881 
\vspace{5mm}
1882 
\begin{quotation}
1883 
rA <- rB - exts(Immediate)
1884 
\end{quotation}
1885 
\vspace{10mm}
1886 
\textbf{\LARGE Notes:}{\LARGE \par}
1887 
\vspace{5mm}
1888 
\begin{quotation}
1889 
 
1890 
\end{quotation}
1891 
\vspace{10mm}
1892 
\vfill
1893 
Class 1:
1894 
{\centering \begin{tabular}{|c|c|c|}
1895 
\hline
1896 
Architecture Level&
1897 
Execution Mode&
1898 
Implementation\\
1899 
\hline
1900 
Core CPU&User and Supervisor&Mandatory always\\
1901 
\hline
1902 
\end{tabular}\par}
1903 
 
1904 
 
1905 
 
1906 
\newpage
1907 
\vspace{10mm}
1908 
\lyxline{\small}\vspace{-1\parskip}
1909 
\vspace{10mm}
1910 
{\raggedright \begin{tabular}{ccc}
1911 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
1912 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
1913 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
1914 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
1915 
\textbf{\huge l.muli32s}&
1916 
\multicolumn{1}{c}{\textbf{\huge Multiply Immediate Signed}}&
1917 
\textbf{\huge l.muli32s}\\
1918 
\end{tabular}\par}
1919 
\bigskip{}
1920 
 
1921 
\vspace{10mm}
1922 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
1923 
\hline
1924 
31&
1925 
&
1926 
&
1927 
&
1928 
&
1929 
&
1930 
&
1931 
24&
1932 
23&
1933 
&
1934 
&
1935 
20&
1936 
19&
1937 
&
1938 
&
1939 
16&
1940 
15&
1941 
&
1942 
&
1943 
&
1944 
&
1945 
&
1946 
&
1947 
&
1948 
&
1949 
&
1950 
&
1951 
&
1952 
&
1953 
&
1954 
&
1955 
0\\
1956 
\hline
1957 
\multicolumn{8}{|c|}{opcode 0x28}&
1958 
\multicolumn{4}{c|}{A}&
1959 
\multicolumn{4}{c|}{B}&
1960 
\multicolumn{16}{c|}{I}\\
1961 
 
1962 
\hline
1963 
\multicolumn{8}{|c|}{8 bits}&
1964 
\multicolumn{4}{c|}{4 bits}&
1965 
\multicolumn{4}{c|}{4 bits}&
1966 
\multicolumn{16}{c|}{16 bits}\\
1967 
 
1968 
\hline
1969 
\end{tabular}\par}
1970 
\vspace{15mm}
1971 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
1972 
\vspace{5mm}
1973 
\begin{quotation}
1974 
\texttt{\large l.muli32s\ rA,rB,I}{\large \par}
1975 
\end{quotation}
1976 
\vspace{10mm}
1977 
\textbf{\LARGE Description:}{\LARGE \par}
1978 
\vspace{5mm}
1979 
\begin{quotation}
1980 
\texttt{\large Immediate and the contents of general register rB are multiplied and the result is truncated to 32 bits and placed into general register rA.}{\large \par}
1981 
\end{quotation}
1982 
\vspace{10mm}
1983 
\textbf{\LARGE Operation:}{\LARGE \par}
1984 
\vspace{5mm}
1985 
\begin{quotation}
1986 
rA <- rB * Immediate
1987 
\end{quotation}
1988 
\vspace{10mm}
1989 
\textbf{\LARGE Notes:}{\LARGE \par}
1990 
\vspace{5mm}
1991 
\begin{quotation}
1992 
 
1993 
\end{quotation}
1994 
\vspace{10mm}
1995 
\vfill
1996 
Class 2:
1997 
{\centering \begin{tabular}{|c|c|c|}
1998 
\hline
1999 
Architecture Level&
2000 
Execution Mode&
2001 
Implementation\\
2002 
\hline
2003 
Core CPU&User and Supervisor&Recommended\\
2004 
\hline
2005 
\end{tabular}\par}
2006 
 
2007 
 
2008 
 
2009 
\newpage
2010 
\vspace{10mm}
2011 
\lyxline{\small}\vspace{-1\parskip}
2012 
\vspace{10mm}
2013 
{\raggedright \begin{tabular}{ccc}
2014 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2015 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2016 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2017 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2018 
\textbf{\huge l.xori16}&
2019 
\multicolumn{1}{c}{\textbf{\huge Exclusive Or Immediate Half Word}}&
2020 
\textbf{\huge l.xori16}\\
2021 
\end{tabular}\par}
2022 
\bigskip{}
2023 
 
2024 
\vspace{10mm}
2025 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
2026 
\hline
2027 
31&
2028 
&
2029 
&
2030 
&
2031 
&
2032 
&
2033 
&
2034 
24&
2035 
23&
2036 
&
2037 
&
2038 
20&
2039 
19&
2040 
&
2041 
&
2042 
16&
2043 
15&
2044 
&
2045 
&
2046 
&
2047 
&
2048 
&
2049 
&
2050 
&
2051 
&
2052 
&
2053 
&
2054 
&
2055 
&
2056 
&
2057 
&
2058 
0\\
2059 
\hline
2060 
\multicolumn{8}{|c|}{opcode 0x29}&
2061 
\multicolumn{4}{c|}{A}&
2062 
\multicolumn{4}{c|}{B}&
2063 
\multicolumn{16}{c|}{I}\\
2064 
 
2065 
\hline
2066 
\multicolumn{8}{|c|}{8 bits}&
2067 
\multicolumn{4}{c|}{4 bits}&
2068 
\multicolumn{4}{c|}{4 bits}&
2069 
\multicolumn{16}{c|}{16 bits}\\
2070 
 
2071 
\hline
2072 
\end{tabular}\par}
2073 
\vspace{15mm}
2074 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2075 
\vspace{5mm}
2076 
\begin{quotation}
2077 
\texttt{\large l.xori16\ rA,rB,I}{\large \par}
2078 
\end{quotation}
2079 
\vspace{10mm}
2080 
\textbf{\LARGE Description:}{\LARGE \par}
2081 
\vspace{5mm}
2082 
\begin{quotation}
2083 
\texttt{\large Immediate is zero-extended and combined with the contents of general register rB in a bit-wise logical XOR operation. The result is placed into general register rA.}{\large \par}
2084 
\end{quotation}
2085 
\vspace{10mm}
2086 
\textbf{\LARGE Operation:}{\LARGE \par}
2087 
\vspace{5mm}
2088 
\begin{quotation}
2089 
rA <- rB XOR exts(Immediate)
2090 
\end{quotation}
2091 
\vspace{10mm}
2092 
\textbf{\LARGE Notes:}{\LARGE \par}
2093 
\vspace{5mm}
2094 
\begin{quotation}
2095 
 
2096 
\end{quotation}
2097 
\vspace{10mm}
2098 
\vfill
2099 
Class 3:
2100 
{\centering \begin{tabular}{|c|c|c|}
2101 
\hline
2102 
Architecture Level&
2103 
Execution Mode&
2104 
Implementation\\
2105 
\hline
2106 
Core CPU&User and Supervisor&Optional\\
2107 
\hline
2108 
\end{tabular}\par}
2109 
 
2110 
 
2111 
 
2112 
\newpage
2113 
\vspace{10mm}
2114 
\lyxline{\small}\vspace{-1\parskip}
2115 
\vspace{10mm}
2116 
{\raggedright \begin{tabular}{ccc}
2117 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2118 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2119 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2120 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2121 
\textbf{\huge l.immlo16u}&
2122 
\multicolumn{1}{c}{\textbf{\huge Immediate Low-Order Half Word Unsigned}}&
2123 
\textbf{\huge l.immlo16u}\\
2124 
\end{tabular}\par}
2125 
\bigskip{}
2126 
 
2127 
\vspace{10mm}
2128 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
2129 
\hline
2130 
31&
2131 
&
2132 
&
2133 
&
2134 
&
2135 
&
2136 
&
2137 
24&
2138 
23&
2139 
&
2140 
&
2141 
20&
2142 
19&
2143 
&
2144 
&
2145 
16&
2146 
15&
2147 
&
2148 
&
2149 
&
2150 
&
2151 
&
2152 
&
2153 
&
2154 
&
2155 
&
2156 
&
2157 
&
2158 
&
2159 
&
2160 
&
2161 
0\\
2162 
\hline
2163 
\multicolumn{8}{|c|}{opcode 0x2a}&
2164 
\multicolumn{4}{c|}{A}&
2165 
\multicolumn{4}{c|}{reserved}&
2166 
\multicolumn{16}{c|}{I}\\
2167 
 
2168 
\hline
2169 
\multicolumn{8}{|c|}{8 bits}&
2170 
\multicolumn{4}{c|}{4 bits}&
2171 
\multicolumn{4}{c|}{4 bits}&
2172 
\multicolumn{16}{c|}{16 bits}\\
2173 
 
2174 
\hline
2175 
\end{tabular}\par}
2176 
\vspace{15mm}
2177 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2178 
\vspace{5mm}
2179 
\begin{quotation}
2180 
\texttt{\large l.immlo16u\ rA,lo(I)}{\large \par}
2181 
\end{quotation}
2182 
\vspace{10mm}
2183 
\textbf{\LARGE Description:}{\LARGE \par}
2184 
\vspace{5mm}
2185 
\begin{quotation}
2186 
\texttt{\large 16 bit immediate is placed into low-order 16 bits of general register rA.}{\large \par}
2187 
\end{quotation}
2188 
\vspace{10mm}
2189 
\textbf{\LARGE Operation:}{\LARGE \par}
2190 
\vspace{5mm}
2191 
\begin{quotation}
2192 
rA{[}15:0{]} <- Immediate
2193 
\end{quotation}
2194 
\vspace{10mm}
2195 
\textbf{\LARGE Notes:}{\LARGE \par}
2196 
\vspace{5mm}
2197 
\begin{quotation}
2198 
 
2199 
\end{quotation}
2200 
\vspace{10mm}
2201 
\vfill
2202 
Class 1:
2203 
{\centering \begin{tabular}{|c|c|c|}
2204 
\hline
2205 
Architecture Level&
2206 
Execution Mode&
2207 
Implementation\\
2208 
\hline
2209 
Core CPU&User and Supervisor&Mandatory always\\
2210 
\hline
2211 
\end{tabular}\par}
2212 
 
2213 
 
2214 
 
2215 
\newpage
2216 
\vspace{10mm}
2217 
\lyxline{\small}\vspace{-1\parskip}
2218 
\vspace{10mm}
2219 
{\raggedright \begin{tabular}{ccc}
2220 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2221 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2222 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2223 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2224 
\textbf{\huge l.immhi16u}&
2225 
\multicolumn{1}{c}{\textbf{\huge Immediate High-Order Half Word Unsigned}}&
2226 
\textbf{\huge l.immhi16u}\\
2227 
\end{tabular}\par}
2228 
\bigskip{}
2229 
 
2230 
\vspace{10mm}
2231 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
2232 
\hline
2233 
31&
2234 
&
2235 
&
2236 
&
2237 
&
2238 
&
2239 
&
2240 
24&
2241 
23&
2242 
&
2243 
&
2244 
20&
2245 
19&
2246 
&
2247 
&
2248 
16&
2249 
15&
2250 
&
2251 
&
2252 
&
2253 
&
2254 
&
2255 
&
2256 
&
2257 
&
2258 
&
2259 
&
2260 
&
2261 
&
2262 
&
2263 
&
2264 
0\\
2265 
\hline
2266 
\multicolumn{8}{|c|}{opcode 0x2b}&
2267 
\multicolumn{4}{c|}{A}&
2268 
\multicolumn{4}{c|}{reserved}&
2269 
\multicolumn{16}{c|}{I}\\
2270 
 
2271 
\hline
2272 
\multicolumn{8}{|c|}{8 bits}&
2273 
\multicolumn{4}{c|}{4 bits}&
2274 
\multicolumn{4}{c|}{4 bits}&
2275 
\multicolumn{16}{c|}{16 bits}\\
2276 
 
2277 
\hline
2278 
\end{tabular}\par}
2279 
\vspace{15mm}
2280 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2281 
\vspace{5mm}
2282 
\begin{quotation}
2283 
\texttt{\large l.immhi16u\ rA,hi(I)}{\large \par}
2284 
\end{quotation}
2285 
\vspace{10mm}
2286 
\textbf{\LARGE Description:}{\LARGE \par}
2287 
\vspace{5mm}
2288 
\begin{quotation}
2289 
\texttt{\large 16 bit immediate is placed into high-order 16 bits of general register rA.}{\large \par}
2290 
\end{quotation}
2291 
\vspace{10mm}
2292 
\textbf{\LARGE Operation:}{\LARGE \par}
2293 
\vspace{5mm}
2294 
\begin{quotation}
2295 
rA{[}31:16{]} <- Immediate
2296 
\end{quotation}
2297 
\vspace{10mm}
2298 
\textbf{\LARGE Notes:}{\LARGE \par}
2299 
\vspace{5mm}
2300 
\begin{quotation}
2301 
 
2302 
\end{quotation}
2303 
\vspace{10mm}
2304 
\vfill
2305 
Class 1:
2306 
{\centering \begin{tabular}{|c|c|c|}
2307 
\hline
2308 
Architecture Level&
2309 
Execution Mode&
2310 
Implementation\\
2311 
\hline
2312 
Core CPU&User and Supervisor&Mandatory always\\
2313 
\hline
2314 
\end{tabular}\par}
2315 
 
2316 
 
2317 
 
2318 
\newpage
2319 
\vspace{10mm}
2320 
\lyxline{\small}\vspace{-1\parskip}
2321 
\vspace{10mm}
2322 
{\raggedright \begin{tabular}{ccc}
2323 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2324 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2325 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2326 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2327 
\textbf{\huge l.sub32s}&
2328 
\multicolumn{1}{c}{\textbf{\huge Subtract Signed}}&
2329 
\textbf{\huge l.sub32s}\\
2330 
\end{tabular}\par}
2331 
\bigskip{}
2332 
 
2333 
\vspace{10mm}
2334 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2335 
\hline
2336 
31&
2337 
&
2338 
&
2339 
&
2340 
&
2341 
&
2342 
&
2343 
24&
2344 
23&
2345 
&
2346 
&
2347 
20&
2348 
19&
2349 
&
2350 
&
2351 
16&
2352 
15&
2353 
&
2354 
&
2355 
12&
2356 
11&
2357 
&
2358 
&
2359 
8&
2360 
7&
2361 
&
2362 
&
2363 
&
2364 
&
2365 
&
2366 
&
2367 
0\\
2368 
\hline
2369 
\multicolumn{8}{|c|}{opcode 0x2c}&
2370 
\multicolumn{4}{c|}{A}&
2371 
\multicolumn{4}{c|}{B}&
2372 
\multicolumn{4}{c|}{C}&
2373 
\multicolumn{4}{c|}{opcode 0x0}&
2374 
\multicolumn{8}{c|}{reserved}\\
2375 
 
2376 
\hline
2377 
\multicolumn{8}{|c|}{8 bits}&
2378 
\multicolumn{4}{c|}{4 bits}&
2379 
\multicolumn{4}{c|}{4 bits}&
2380 
\multicolumn{4}{c|}{4 bits}&
2381 
\multicolumn{4}{c|}{4 bits}&
2382 
\multicolumn{8}{c|}{8 bits}\\
2383 
 
2384 
\hline
2385 
\end{tabular}\par}
2386 
\vspace{15mm}
2387 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2388 
\vspace{5mm}
2389 
\begin{quotation}
2390 
\texttt{\large l.sub32s\ rA,rB,rC}{\large \par}
2391 
\end{quotation}
2392 
\vspace{10mm}
2393 
\textbf{\LARGE Description:}{\LARGE \par}
2394 
\vspace{5mm}
2395 
\begin{quotation}
2396 
\texttt{\large The contents of general register rC is subtracted from the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
2397 
\end{quotation}
2398 
\vspace{10mm}
2399 
\textbf{\LARGE Operation:}{\LARGE \par}
2400 
\vspace{5mm}
2401 
\begin{quotation}
2402 
rA <- rB - rC
2403 
\end{quotation}
2404 
\vspace{10mm}
2405 
\textbf{\LARGE Notes:}{\LARGE \par}
2406 
\vspace{5mm}
2407 
\begin{quotation}
2408 
 
2409 
\end{quotation}
2410 
\vspace{10mm}
2411 
\vfill
2412 
Class 1:
2413 
{\centering \begin{tabular}{|c|c|c|}
2414 
\hline
2415 
Architecture Level&
2416 
Execution Mode&
2417 
Implementation\\
2418 
\hline
2419 
Core CPU&User and Supervisor&Mandatory always\\
2420 
\hline
2421 
\end{tabular}\par}
2422 
 
2423 
 
2424 
 
2425 
\newpage
2426 
\vspace{10mm}
2427 
\lyxline{\small}\vspace{-1\parskip}
2428 
\vspace{10mm}
2429 
{\raggedright \begin{tabular}{ccc}
2430 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2431 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2432 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2433 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2434 
\textbf{\huge l.shla32}&
2435 
\multicolumn{1}{c}{\textbf{\huge Shift Left Arithmetic}}&
2436 
\textbf{\huge l.shla32}\\
2437 
\end{tabular}\par}
2438 
\bigskip{}
2439 
 
2440 
\vspace{10mm}
2441 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
2442 
\hline
2443 
31&
2444 
&
2445 
&
2446 
&
2447 
&
2448 
&
2449 
&
2450 
24&
2451 
23&
2452 
&
2453 
&
2454 
20&
2455 
19&
2456 
&
2457 
&
2458 
16&
2459 
15&
2460 
&
2461 
&
2462 
12&
2463 
11&
2464 
&
2465 
&
2466 
8&
2467 
7&
2468 
&
2469 
&
2470 
&
2471 
3&
2472 
2&
2473 
&
2474 
0\\
2475 
\hline
2476 
\multicolumn{8}{|c|}{opcode 0x2c}&
2477 
\multicolumn{4}{c|}{A}&
2478 
\multicolumn{4}{c|}{B}&
2479 
\multicolumn{4}{c|}{C}&
2480 
\multicolumn{4}{c|}{opcode 0x1}&
2481 
\multicolumn{5}{c|}{L}&
2482 
\multicolumn{3}{c|}{reserved}\\
2483 
 
2484 
\hline
2485 
\multicolumn{8}{|c|}{8 bits}&
2486 
\multicolumn{4}{c|}{4 bits}&
2487 
\multicolumn{4}{c|}{4 bits}&
2488 
\multicolumn{4}{c|}{4 bits}&
2489 
\multicolumn{4}{c|}{4 bits}&
2490 
\multicolumn{5}{c|}{5 bits}&
2491 
\multicolumn{3}{c|}{3 bits}\\
2492 
 
2493 
\hline
2494 
\end{tabular}\par}
2495 
\vspace{15mm}
2496 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2497 
\vspace{5mm}
2498 
\begin{quotation}
2499 
\texttt{\large l.shla32\ rA,rB,rC,L}{\large \par}
2500 
\end{quotation}
2501 
\vspace{10mm}
2502 
\textbf{\LARGE Description:}{\LARGE \par}
2503 
\vspace{5mm}
2504 
\begin{quotation}
2505 
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted left, inserting zeros into the low-order bits.}{\large \par}
2506 
\end{quotation}
2507 
\vspace{10mm}
2508 
\textbf{\LARGE Operation:}{\LARGE \par}
2509 
\vspace{5mm}
2510 
\begin{quotation}
2511 
b <- Immediate | rC\\rA{[}31:b{]} <- rB{[}31-b:0{]}\\rA{[}b:0{]} <- 0
2512 
\end{quotation}
2513 
\vspace{10mm}
2514 
\textbf{\LARGE Notes:}{\LARGE \par}
2515 
\vspace{5mm}
2516 
\begin{quotation}
2517 
 
2518 
\end{quotation}
2519 
\vspace{10mm}
2520 
\vfill
2521 
Class 1:
2522 
{\centering \begin{tabular}{|c|c|c|}
2523 
\hline
2524 
Architecture Level&
2525 
Execution Mode&
2526 
Implementation\\
2527 
\hline
2528 
Core CPU&User and Supervisor&Mandatory always\\
2529 
\hline
2530 
\end{tabular}\par}
2531 
 
2532 
 
2533 
 
2534 
\newpage
2535 
\vspace{10mm}
2536 
\lyxline{\small}\vspace{-1\parskip}
2537 
\vspace{10mm}
2538 
{\raggedright \begin{tabular}{ccc}
2539 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2540 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2541 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2542 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2543 
\textbf{\huge l.shra32}&
2544 
\multicolumn{1}{c}{\textbf{\huge Shift Right Arithmetic}}&
2545 
\textbf{\huge l.shra32}\\
2546 
\end{tabular}\par}
2547 
\bigskip{}
2548 
 
2549 
\vspace{10mm}
2550 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
2551 
\hline
2552 
31&
2553 
&
2554 
&
2555 
&
2556 
&
2557 
&
2558 
&
2559 
24&
2560 
23&
2561 
&
2562 
&
2563 
20&
2564 
19&
2565 
&
2566 
&
2567 
16&
2568 
15&
2569 
&
2570 
&
2571 
12&
2572 
11&
2573 
&
2574 
&
2575 
8&
2576 
7&
2577 
&
2578 
&
2579 
&
2580 
3&
2581 
2&
2582 
&
2583 
0\\
2584 
\hline
2585 
\multicolumn{8}{|c|}{opcode 0x2c}&
2586 
\multicolumn{4}{c|}{A}&
2587 
\multicolumn{4}{c|}{B}&
2588 
\multicolumn{4}{c|}{C}&
2589 
\multicolumn{4}{c|}{opcode 0x2}&
2590 
\multicolumn{5}{c|}{L}&
2591 
\multicolumn{3}{c|}{reserved}\\
2592 
 
2593 
\hline
2594 
\multicolumn{8}{|c|}{8 bits}&
2595 
\multicolumn{4}{c|}{4 bits}&
2596 
\multicolumn{4}{c|}{4 bits}&
2597 
\multicolumn{4}{c|}{4 bits}&
2598 
\multicolumn{4}{c|}{4 bits}&
2599 
\multicolumn{5}{c|}{5 bits}&
2600 
\multicolumn{3}{c|}{3 bits}\\
2601 
 
2602 
\hline
2603 
\end{tabular}\par}
2604 
\vspace{15mm}
2605 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2606 
\vspace{5mm}
2607 
\begin{quotation}
2608 
\texttt{\large l.shra32\ rA,rB,rC,L}{\large \par}
2609 
\end{quotation}
2610 
\vspace{10mm}
2611 
\textbf{\LARGE Description:}{\LARGE \par}
2612 
\vspace{5mm}
2613 
\begin{quotation}
2614 
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted right, sign-extending the high-order bits.}{\large \par}
2615 
\end{quotation}
2616 
\vspace{10mm}
2617 
\textbf{\LARGE Operation:}{\LARGE \par}
2618 
\vspace{5mm}
2619 
\begin{quotation}
2620 
b <- Immediate | rC\\rA{[}31-b:0{]} <- rB{[}31:b{]}\\rA{[}31-b:31{]} <- rB{[}31{]}
2621 
\end{quotation}
2622 
\vspace{10mm}
2623 
\textbf{\LARGE Notes:}{\LARGE \par}
2624 
\vspace{5mm}
2625 
\begin{quotation}
2626 
 
2627 
\end{quotation}
2628 
\vspace{10mm}
2629 
\vfill
2630 
Class 1:
2631 
{\centering \begin{tabular}{|c|c|c|}
2632 
\hline
2633 
Architecture Level&
2634 
Execution Mode&
2635 
Implementation\\
2636 
\hline
2637 
Core CPU&User and Supervisor&Mandatory always\\
2638 
\hline
2639 
\end{tabular}\par}
2640 
 
2641 
 
2642 
 
2643 
\newpage
2644 
\vspace{10mm}
2645 
\lyxline{\small}\vspace{-1\parskip}
2646 
\vspace{10mm}
2647 
{\raggedright \begin{tabular}{ccc}
2648 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2649 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2650 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2651 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2652 
\textbf{\huge l.shrl32}&
2653 
\multicolumn{1}{c}{\textbf{\huge Shift Right Logical}}&
2654 
\textbf{\huge l.shrl32}\\
2655 
\end{tabular}\par}
2656 
\bigskip{}
2657 
 
2658 
\vspace{10mm}
2659 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
2660 
\hline
2661 
31&
2662 
&
2663 
&
2664 
&
2665 
&
2666 
&
2667 
&
2668 
24&
2669 
23&
2670 
&
2671 
&
2672 
20&
2673 
19&
2674 
&
2675 
&
2676 
16&
2677 
15&
2678 
&
2679 
&
2680 
12&
2681 
11&
2682 
&
2683 
&
2684 
8&
2685 
7&
2686 
&
2687 
&
2688 
&
2689 
3&
2690 
2&
2691 
&
2692 
0\\
2693 
\hline
2694 
\multicolumn{8}{|c|}{opcode 0x2c}&
2695 
\multicolumn{4}{c|}{A}&
2696 
\multicolumn{4}{c|}{B}&
2697 
\multicolumn{4}{c|}{C}&
2698 
\multicolumn{4}{c|}{opcode 0x3}&
2699 
\multicolumn{5}{c|}{L}&
2700 
\multicolumn{3}{c|}{reserved}\\
2701 
 
2702 
\hline
2703 
\multicolumn{8}{|c|}{8 bits}&
2704 
\multicolumn{4}{c|}{4 bits}&
2705 
\multicolumn{4}{c|}{4 bits}&
2706 
\multicolumn{4}{c|}{4 bits}&
2707 
\multicolumn{4}{c|}{4 bits}&
2708 
\multicolumn{5}{c|}{5 bits}&
2709 
\multicolumn{3}{c|}{3 bits}\\
2710 
 
2711 
\hline
2712 
\end{tabular}\par}
2713 
\vspace{15mm}
2714 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2715 
\vspace{5mm}
2716 
\begin{quotation}
2717 
\texttt{\large l.shrl32\ rA,rB,rC,L}{\large \par}
2718 
\end{quotation}
2719 
\vspace{10mm}
2720 
\textbf{\LARGE Description:}{\LARGE \par}
2721 
\vspace{5mm}
2722 
\begin{quotation}
2723 
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted right, inserting zeros into the high-order bits.}{\large \par}
2724 
\end{quotation}
2725 
\vspace{10mm}
2726 
\textbf{\LARGE Operation:}{\LARGE \par}
2727 
\vspace{5mm}
2728 
\begin{quotation}
2729 
b <- Immediate | rC\\rA{[}31-b:0{]} <- rB{[}31:b{]}\\rA{[}31-b:31{]} <- 0
2730 
\end{quotation}
2731 
\vspace{10mm}
2732 
\textbf{\LARGE Notes:}{\LARGE \par}
2733 
\vspace{5mm}
2734 
\begin{quotation}
2735 
 
2736 
\end{quotation}
2737 
\vspace{10mm}
2738 
\vfill
2739 
Class 1:
2740 
{\centering \begin{tabular}{|c|c|c|}
2741 
\hline
2742 
Architecture Level&
2743 
Execution Mode&
2744 
Implementation\\
2745 
\hline
2746 
Core CPU&User and Supervisor&Mandatory always\\
2747 
\hline
2748 
\end{tabular}\par}
2749 
 
2750 
 
2751 
 
2752 
\newpage
2753 
\vspace{10mm}
2754 
\lyxline{\small}\vspace{-1\parskip}
2755 
\vspace{10mm}
2756 
{\raggedright \begin{tabular}{ccc}
2757 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2758 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2759 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2760 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2761 
\textbf{\huge l.and32}&
2762 
\multicolumn{1}{c}{\textbf{\huge And}}&
2763 
\textbf{\huge l.and32}\\
2764 
\end{tabular}\par}
2765 
\bigskip{}
2766 
 
2767 
\vspace{10mm}
2768 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2769 
\hline
2770 
31&
2771 
&
2772 
&
2773 
&
2774 
&
2775 
&
2776 
&
2777 
24&
2778 
23&
2779 
&
2780 
&
2781 
20&
2782 
19&
2783 
&
2784 
&
2785 
16&
2786 
15&
2787 
&
2788 
&
2789 
12&
2790 
11&
2791 
&
2792 
&
2793 
8&
2794 
7&
2795 
&
2796 
&
2797 
&
2798 
&
2799 
&
2800 
&
2801 
0\\
2802 
\hline
2803 
\multicolumn{8}{|c|}{opcode 0x2c}&
2804 
\multicolumn{4}{c|}{A}&
2805 
\multicolumn{4}{c|}{B}&
2806 
\multicolumn{4}{c|}{C}&
2807 
\multicolumn{4}{c|}{opcode 0x4}&
2808 
\multicolumn{8}{c|}{reserved}\\
2809 
 
2810 
\hline
2811 
\multicolumn{8}{|c|}{8 bits}&
2812 
\multicolumn{4}{c|}{4 bits}&
2813 
\multicolumn{4}{c|}{4 bits}&
2814 
\multicolumn{4}{c|}{4 bits}&
2815 
\multicolumn{4}{c|}{4 bits}&
2816 
\multicolumn{8}{c|}{8 bits}\\
2817 
 
2818 
\hline
2819 
\end{tabular}\par}
2820 
\vspace{15mm}
2821 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2822 
\vspace{5mm}
2823 
\begin{quotation}
2824 
\texttt{\large l.and32\ rA,rB,rC}{\large \par}
2825 
\end{quotation}
2826 
\vspace{10mm}
2827 
\textbf{\LARGE Description:}{\LARGE \par}
2828 
\vspace{5mm}
2829 
\begin{quotation}
2830 
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical AND operation. The result is placed into general register rA.}{\large \par}
2831 
\end{quotation}
2832 
\vspace{10mm}
2833 
\textbf{\LARGE Operation:}{\LARGE \par}
2834 
\vspace{5mm}
2835 
\begin{quotation}
2836 
rA <- rB AND rC
2837 
\end{quotation}
2838 
\vspace{10mm}
2839 
\textbf{\LARGE Notes:}{\LARGE \par}
2840 
\vspace{5mm}
2841 
\begin{quotation}
2842 
 
2843 
\end{quotation}
2844 
\vspace{10mm}
2845 
\vfill
2846 
Class 1:
2847 
{\centering \begin{tabular}{|c|c|c|}
2848 
\hline
2849 
Architecture Level&
2850 
Execution Mode&
2851 
Implementation\\
2852 
\hline
2853 
Core CPU&User and Supervisor&Mandatory always\\
2854 
\hline
2855 
\end{tabular}\par}
2856 
 
2857 
 
2858 
 
2859 
\newpage
2860 
\vspace{10mm}
2861 
\lyxline{\small}\vspace{-1\parskip}
2862 
\vspace{10mm}
2863 
{\raggedright \begin{tabular}{ccc}
2864 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2865 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2866 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2867 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2868 
\textbf{\huge l.or32}&
2869 
\multicolumn{1}{c}{\textbf{\huge Or}}&
2870 
\textbf{\huge l.or32}\\
2871 
\end{tabular}\par}
2872 
\bigskip{}
2873 
 
2874 
\vspace{10mm}
2875 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2876 
\hline
2877 
31&
2878 
&
2879 
&
2880 
&
2881 
&
2882 
&
2883 
&
2884 
24&
2885 
23&
2886 
&
2887 
&
2888 
20&
2889 
19&
2890 
&
2891 
&
2892 
16&
2893 
15&
2894 
&
2895 
&
2896 
12&
2897 
11&
2898 
&
2899 
&
2900 
8&
2901 
7&
2902 
&
2903 
&
2904 
&
2905 
&
2906 
&
2907 
&
2908 
0\\
2909 
\hline
2910 
\multicolumn{8}{|c|}{opcode 0x2c}&
2911 
\multicolumn{4}{c|}{A}&
2912 
\multicolumn{4}{c|}{B}&
2913 
\multicolumn{4}{c|}{C}&
2914 
\multicolumn{4}{c|}{opcode 0x5}&
2915 
\multicolumn{8}{c|}{reserved}\\
2916 
 
2917 
\hline
2918 
\multicolumn{8}{|c|}{8 bits}&
2919 
\multicolumn{4}{c|}{4 bits}&
2920 
\multicolumn{4}{c|}{4 bits}&
2921 
\multicolumn{4}{c|}{4 bits}&
2922 
\multicolumn{4}{c|}{4 bits}&
2923 
\multicolumn{8}{c|}{8 bits}\\
2924 
 
2925 
\hline
2926 
\end{tabular}\par}
2927 
\vspace{15mm}
2928 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
2929 
\vspace{5mm}
2930 
\begin{quotation}
2931 
\texttt{\large l.or32\ rA,rB,rC}{\large \par}
2932 
\end{quotation}
2933 
\vspace{10mm}
2934 
\textbf{\LARGE Description:}{\LARGE \par}
2935 
\vspace{5mm}
2936 
\begin{quotation}
2937 
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical OR operation. The result is placed into general register rA.}{\large \par}
2938 
\end{quotation}
2939 
\vspace{10mm}
2940 
\textbf{\LARGE Operation:}{\LARGE \par}
2941 
\vspace{5mm}
2942 
\begin{quotation}
2943 
rA <- rB OR rC
2944 
\end{quotation}
2945 
\vspace{10mm}
2946 
\textbf{\LARGE Notes:}{\LARGE \par}
2947 
\vspace{5mm}
2948 
\begin{quotation}
2949 
 
2950 
\end{quotation}
2951 
\vspace{10mm}
2952 
\vfill
2953 
Class 1:
2954 
{\centering \begin{tabular}{|c|c|c|}
2955 
\hline
2956 
Architecture Level&
2957 
Execution Mode&
2958 
Implementation\\
2959 
\hline
2960 
Core CPU&User and Supervisor&Mandatory always\\
2961 
\hline
2962 
\end{tabular}\par}
2963 
 
2964 
 
2965 
 
2966 
\newpage
2967 
\vspace{10mm}
2968 
\lyxline{\small}\vspace{-1\parskip}
2969 
\vspace{10mm}
2970 
{\raggedright \begin{tabular}{ccc}
2971 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
2972 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
2973 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
2974 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
2975 
\textbf{\huge l.xor32}&
2976 
\multicolumn{1}{c}{\textbf{\huge Exclusive Or}}&
2977 
\textbf{\huge l.xor32}\\
2978 
\end{tabular}\par}
2979 
\bigskip{}
2980 
 
2981 
\vspace{10mm}
2982 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
2983 
\hline
2984 
31&
2985 
&
2986 
&
2987 
&
2988 
&
2989 
&
2990 
&
2991 
24&
2992 
23&
2993 
&
2994 
&
2995 
20&
2996 
19&
2997 
&
2998 
&
2999 
16&
3000 
15&
3001 
&
3002 
&
3003 
12&
3004 
11&
3005 
&
3006 
&
3007 
8&
3008 
7&
3009 
&
3010 
&
3011 
&
3012 
&
3013 
&
3014 
&
3015 
0\\
3016 
\hline
3017 
\multicolumn{8}{|c|}{opcode 0x2c}&
3018 
\multicolumn{4}{c|}{A}&
3019 
\multicolumn{4}{c|}{B}&
3020 
\multicolumn{4}{c|}{C}&
3021 
\multicolumn{4}{c|}{opcode 0x6}&
3022 
\multicolumn{8}{c|}{reserved}\\
3023 
 
3024 
\hline
3025 
\multicolumn{8}{|c|}{8 bits}&
3026 
\multicolumn{4}{c|}{4 bits}&
3027 
\multicolumn{4}{c|}{4 bits}&
3028 
\multicolumn{4}{c|}{4 bits}&
3029 
\multicolumn{4}{c|}{4 bits}&
3030 
\multicolumn{8}{c|}{8 bits}\\
3031 
 
3032 
\hline
3033 
\end{tabular}\par}
3034 
\vspace{15mm}
3035 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3036 
\vspace{5mm}
3037 
\begin{quotation}
3038 
\texttt{\large l.xor32\ rA,rB,rC}{\large \par}
3039 
\end{quotation}
3040 
\vspace{10mm}
3041 
\textbf{\LARGE Description:}{\LARGE \par}
3042 
\vspace{5mm}
3043 
\begin{quotation}
3044 
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical XOR operation. The result is placed into general register rA.}{\large \par}
3045 
\end{quotation}
3046 
\vspace{10mm}
3047 
\textbf{\LARGE Operation:}{\LARGE \par}
3048 
\vspace{5mm}
3049 
\begin{quotation}
3050 
rA <- rB XOR rC
3051 
\end{quotation}
3052 
\vspace{10mm}
3053 
\textbf{\LARGE Notes:}{\LARGE \par}
3054 
\vspace{5mm}
3055 
\begin{quotation}
3056 
 
3057 
\end{quotation}
3058 
\vspace{10mm}
3059 
\vfill
3060 
Class 1:
3061 
{\centering \begin{tabular}{|c|c|c|}
3062 
\hline
3063 
Architecture Level&
3064 
Execution Mode&
3065 
Implementation\\
3066 
\hline
3067 
Core CPU&User and Supervisor&Mandatory always\\
3068 
\hline
3069 
\end{tabular}\par}
3070 
 
3071 
 
3072 
 
3073 
\newpage
3074 
\vspace{10mm}
3075 
\lyxline{\small}\vspace{-1\parskip}
3076 
\vspace{10mm}
3077 
{\raggedright \begin{tabular}{ccc}
3078 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3079 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3080 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3081 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3082 
\textbf{\huge l.mul32s}&
3083 
\multicolumn{1}{c}{\textbf{\huge Multiply Signed}}&
3084 
\textbf{\huge l.mul32s}\\
3085 
\end{tabular}\par}
3086 
\bigskip{}
3087 
 
3088 
\vspace{10mm}
3089 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
3090 
\hline
3091 
31&
3092 
&
3093 
&
3094 
&
3095 
&
3096 
&
3097 
&
3098 
24&
3099 
23&
3100 
&
3101 
&
3102 
20&
3103 
19&
3104 
&
3105 
&
3106 
16&
3107 
15&
3108 
&
3109 
&
3110 
12&
3111 
11&
3112 
&
3113 
&
3114 
8&
3115 
7&
3116 
&
3117 
&
3118 
&
3119 
&
3120 
&
3121 
&
3122 
0\\
3123 
\hline
3124 
\multicolumn{8}{|c|}{opcode 0x2c}&
3125 
\multicolumn{4}{c|}{A}&
3126 
\multicolumn{4}{c|}{B}&
3127 
\multicolumn{4}{c|}{C}&
3128 
\multicolumn{4}{c|}{opcode 0x7}&
3129 
\multicolumn{8}{c|}{reserved}\\
3130 
 
3131 
\hline
3132 
\multicolumn{8}{|c|}{8 bits}&
3133 
\multicolumn{4}{c|}{4 bits}&
3134 
\multicolumn{4}{c|}{4 bits}&
3135 
\multicolumn{4}{c|}{4 bits}&
3136 
\multicolumn{4}{c|}{4 bits}&
3137 
\multicolumn{8}{c|}{8 bits}\\
3138 
 
3139 
\hline
3140 
\end{tabular}\par}
3141 
\vspace{15mm}
3142 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3143 
\vspace{5mm}
3144 
\begin{quotation}
3145 
\texttt{\large l.mul32s\ rA,rB,rC}{\large \par}
3146 
\end{quotation}
3147 
\vspace{10mm}
3148 
\textbf{\LARGE Description:}{\LARGE \par}
3149 
\vspace{5mm}
3150 
\begin{quotation}
3151 
\texttt{\large The contents of general register rB and the contents of general register rC are multiplied and the result is truncated to 32 bits and placed into general register rA. Both operands are treated as unsigned integers.}{\large \par}
3152 
\end{quotation}
3153 
\vspace{10mm}
3154 
\textbf{\LARGE Operation:}{\LARGE \par}
3155 
\vspace{5mm}
3156 
\begin{quotation}
3157 
rA <- rB * rC
3158 
\end{quotation}
3159 
\vspace{10mm}
3160 
\textbf{\LARGE Notes:}{\LARGE \par}
3161 
\vspace{5mm}
3162 
\begin{quotation}
3163 
 
3164 
\end{quotation}
3165 
\vspace{10mm}
3166 
\vfill
3167 
Class 2:
3168 
{\centering \begin{tabular}{|c|c|c|}
3169 
\hline
3170 
Architecture Level&
3171 
Execution Mode&
3172 
Implementation\\
3173 
\hline
3174 
Core CPU&User and Supervisor&Recommended\\
3175 
\hline
3176 
\end{tabular}\par}
3177 
 
3178 
 
3179 
 
3180 
\newpage
3181 
\vspace{10mm}
3182 
\lyxline{\small}\vspace{-1\parskip}
3183 
\vspace{10mm}
3184 
{\raggedright \begin{tabular}{ccc}
3185 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3186 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3187 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3188 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3189 
\textbf{\huge l.mul32u}&
3190 
\multicolumn{1}{c}{\textbf{\huge Multiply Unsigned}}&
3191 
\textbf{\huge l.mul32u}\\
3192 
\end{tabular}\par}
3193 
\bigskip{}
3194 
 
3195 
\vspace{10mm}
3196 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
3197 
\hline
3198 
31&
3199 
&
3200 
&
3201 
&
3202 
&
3203 
&
3204 
&
3205 
24&
3206 
23&
3207 
&
3208 
&
3209 
20&
3210 
19&
3211 
&
3212 
&
3213 
16&
3214 
15&
3215 
&
3216 
&
3217 
12&
3218 
11&
3219 
&
3220 
&
3221 
8&
3222 
7&
3223 
&
3224 
&
3225 
&
3226 
&
3227 
&
3228 
&
3229 
0\\
3230 
\hline
3231 
\multicolumn{8}{|c|}{opcode 0x2c}&
3232 
\multicolumn{4}{c|}{A}&
3233 
\multicolumn{4}{c|}{B}&
3234 
\multicolumn{4}{c|}{C}&
3235 
\multicolumn{4}{c|}{opcode 0x8}&
3236 
\multicolumn{8}{c|}{reserved}\\
3237 
 
3238 
\hline
3239 
\multicolumn{8}{|c|}{8 bits}&
3240 
\multicolumn{4}{c|}{4 bits}&
3241 
\multicolumn{4}{c|}{4 bits}&
3242 
\multicolumn{4}{c|}{4 bits}&
3243 
\multicolumn{4}{c|}{4 bits}&
3244 
\multicolumn{8}{c|}{8 bits}\\
3245 
 
3246 
\hline
3247 
\end{tabular}\par}
3248 
\vspace{15mm}
3249 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3250 
\vspace{5mm}
3251 
\begin{quotation}
3252 
\texttt{\large l.mul32u\ rA,rB,rC}{\large \par}
3253 
\end{quotation}
3254 
\vspace{10mm}
3255 
\textbf{\LARGE Description:}{\LARGE \par}
3256 
\vspace{5mm}
3257 
\begin{quotation}
3258 
\texttt{\large The contents of general register rB and the contents of general register rC are multiplied and the result is truncated to 32 bits and placed into general register rA. Both operands are treated as unsigned integers.}{\large \par}
3259 
\end{quotation}
3260 
\vspace{10mm}
3261 
\textbf{\LARGE Operation:}{\LARGE \par}
3262 
\vspace{5mm}
3263 
\begin{quotation}
3264 
rA <- rB * rC
3265 
\end{quotation}
3266 
\vspace{10mm}
3267 
\textbf{\LARGE Notes:}{\LARGE \par}
3268 
\vspace{5mm}
3269 
\begin{quotation}
3270 
 
3271 
\end{quotation}
3272 
\vspace{10mm}
3273 
\vfill
3274 
Class 2:
3275 
{\centering \begin{tabular}{|c|c|c|}
3276 
\hline
3277 
Architecture Level&
3278 
Execution Mode&
3279 
Implementation\\
3280 
\hline
3281 
Core CPU&User and Supervisor&Recommended\\
3282 
\hline
3283 
\end{tabular}\par}
3284 
 
3285 
 
3286 
 
3287 
\newpage
3288 
\vspace{10mm}
3289 
\lyxline{\small}\vspace{-1\parskip}
3290 
\vspace{10mm}
3291 
{\raggedright \begin{tabular}{ccc}
3292 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3293 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3294 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3295 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3296 
\textbf{\huge l.div32s}&
3297 
\multicolumn{1}{c}{\textbf{\huge Divide Signed}}&
3298 
\textbf{\huge l.div32s}\\
3299 
\end{tabular}\par}
3300 
\bigskip{}
3301 
 
3302 
\vspace{10mm}
3303 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
3304 
\hline
3305 
31&
3306 
&
3307 
&
3308 
&
3309 
&
3310 
&
3311 
&
3312 
24&
3313 
23&
3314 
&
3315 
&
3316 
20&
3317 
19&
3318 
&
3319 
&
3320 
16&
3321 
15&
3322 
&
3323 
&
3324 
12&
3325 
11&
3326 
&
3327 
&
3328 
8&
3329 
7&
3330 
&
3331 
&
3332 
&
3333 
&
3334 
&
3335 
&
3336 
0\\
3337 
\hline
3338 
\multicolumn{8}{|c|}{opcode 0x2c}&
3339 
\multicolumn{4}{c|}{A}&
3340 
\multicolumn{4}{c|}{B}&
3341 
\multicolumn{4}{c|}{C}&
3342 
\multicolumn{4}{c|}{opcode 0x9}&
3343 
\multicolumn{8}{c|}{reserved}\\
3344 
 
3345 
\hline
3346 
\multicolumn{8}{|c|}{8 bits}&
3347 
\multicolumn{4}{c|}{4 bits}&
3348 
\multicolumn{4}{c|}{4 bits}&
3349 
\multicolumn{4}{c|}{4 bits}&
3350 
\multicolumn{4}{c|}{4 bits}&
3351 
\multicolumn{8}{c|}{8 bits}\\
3352 
 
3353 
\hline
3354 
\end{tabular}\par}
3355 
\vspace{15mm}
3356 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3357 
\vspace{5mm}
3358 
\begin{quotation}
3359 
\texttt{\large l.div32s\ rA,rB,rC}{\large \par}
3360 
\end{quotation}
3361 
\vspace{10mm}
3362 
\textbf{\LARGE Description:}{\LARGE \par}
3363 
\vspace{5mm}
3364 
\begin{quotation}
3365 
\texttt{\large The contents of general register rB are divided by the contents of general register rC and the result is placed into general register rA. Both operands are treated as signed integers. A divisor flag is set when the divisor is zero.}{\large \par}
3366 
\end{quotation}
3367 
\vspace{10mm}
3368 
\textbf{\LARGE Operation:}{\LARGE \par}
3369 
\vspace{5mm}
3370 
\begin{quotation}
3371 
rA <- rB / rC
3372 
\end{quotation}
3373 
\vspace{10mm}
3374 
\textbf{\LARGE Notes:}{\LARGE \par}
3375 
\vspace{5mm}
3376 
\begin{quotation}
3377 
 
3378 
\end{quotation}
3379 
\vspace{10mm}
3380 
\vfill
3381 
Class 3:
3382 
{\centering \begin{tabular}{|c|c|c|}
3383 
\hline
3384 
Architecture Level&
3385 
Execution Mode&
3386 
Implementation\\
3387 
\hline
3388 
Core CPU&User and Supervisor&Optional\\
3389 
\hline
3390 
\end{tabular}\par}
3391 
 
3392 
 
3393 
 
3394 
\newpage
3395 
\vspace{10mm}
3396 
\lyxline{\small}\vspace{-1\parskip}
3397 
\vspace{10mm}
3398 
{\raggedright \begin{tabular}{ccc}
3399 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3400 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3401 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3402 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3403 
\textbf{\huge l.div32u}&
3404 
\multicolumn{1}{c}{\textbf{\huge Divide Unsigned}}&
3405 
\textbf{\huge l.div32u}\\
3406 
\end{tabular}\par}
3407 
\bigskip{}
3408 
 
3409 
\vspace{10mm}
3410 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
3411 
\hline
3412 
31&
3413 
&
3414 
&
3415 
&
3416 
&
3417 
&
3418 
&
3419 
24&
3420 
23&
3421 
&
3422 
&
3423 
20&
3424 
19&
3425 
&
3426 
&
3427 
16&
3428 
15&
3429 
&
3430 
&
3431 
12&
3432 
11&
3433 
&
3434 
&
3435 
8&
3436 
7&
3437 
&
3438 
&
3439 
&
3440 
&
3441 
&
3442 
&
3443 
0\\
3444 
\hline
3445 
\multicolumn{8}{|c|}{opcode 0x2c}&
3446 
\multicolumn{4}{c|}{A}&
3447 
\multicolumn{4}{c|}{B}&
3448 
\multicolumn{4}{c|}{C}&
3449 
\multicolumn{4}{c|}{opcode 0xa}&
3450 
\multicolumn{8}{c|}{reserved}\\
3451 
 
3452 
\hline
3453 
\multicolumn{8}{|c|}{8 bits}&
3454 
\multicolumn{4}{c|}{4 bits}&
3455 
\multicolumn{4}{c|}{4 bits}&
3456 
\multicolumn{4}{c|}{4 bits}&
3457 
\multicolumn{4}{c|}{4 bits}&
3458 
\multicolumn{8}{c|}{8 bits}\\
3459 
 
3460 
\hline
3461 
\end{tabular}\par}
3462 
\vspace{15mm}
3463 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3464 
\vspace{5mm}
3465 
\begin{quotation}
3466 
\texttt{\large l.div32u\ rA,rB,rC}{\large \par}
3467 
\end{quotation}
3468 
\vspace{10mm}
3469 
\textbf{\LARGE Description:}{\LARGE \par}
3470 
\vspace{5mm}
3471 
\begin{quotation}
3472 
\texttt{\large The contents of general register rB are divided by the contents of general register rC and the result is placed into general register rA. Both operands are treated as unsigned integers. A divisor flag is set when the divisor is zero.}{\large \par}
3473 
\end{quotation}
3474 
\vspace{10mm}
3475 
\textbf{\LARGE Operation:}{\LARGE \par}
3476 
\vspace{5mm}
3477 
\begin{quotation}
3478 
rA <- rB / rC
3479 
\end{quotation}
3480 
\vspace{10mm}
3481 
\textbf{\LARGE Notes:}{\LARGE \par}
3482 
\vspace{5mm}
3483 
\begin{quotation}
3484 
 
3485 
\end{quotation}
3486 
\vspace{10mm}
3487 
\vfill
3488 
Class 3:
3489 
{\centering \begin{tabular}{|c|c|c|}
3490 
\hline
3491 
Architecture Level&
3492 
Execution Mode&
3493 
Implementation\\
3494 
\hline
3495 
Core CPU&User and Supervisor&Optional\\
3496 
\hline
3497 
\end{tabular}\par}
3498 
 
3499 
 
3500 
 
3501 
\newpage
3502 
\vspace{10mm}
3503 
\lyxline{\small}\vspace{-1\parskip}
3504 
\vspace{10mm}
3505 
{\raggedright \begin{tabular}{ccc}
3506 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3507 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3508 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3509 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3510 
\textbf{\huge l.dcbf}&
3511 
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Flush}}&
3512 
\textbf{\huge l.dcbf}\\
3513 
\end{tabular}\par}
3514 
\bigskip{}
3515 
 
3516 
\vspace{10mm}
3517 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3518 
\hline
3519 
31&
3520 
&
3521 
&
3522 
&
3523 
&
3524 
&
3525 
&
3526 
24&
3527 
23&
3528 
&
3529 
&
3530 
20&
3531 
19&
3532 
&
3533 
&
3534 
&
3535 
&
3536 
&
3537 
&
3538 
12&
3539 
11&
3540 
&
3541 
&
3542 
8&
3543 
7&
3544 
&
3545 
&
3546 
&
3547 
&
3548 
&
3549 
&
3550 
0\\
3551 
\hline
3552 
\multicolumn{8}{|c|}{opcode 0x30}&
3553 
\multicolumn{4}{c|}{A}&
3554 
\multicolumn{8}{c|}{I}&
3555 
\multicolumn{4}{c|}{opcode 0x0}&
3556 
\multicolumn{8}{c|}{I}\\
3557 
 
3558 
\hline
3559 
\multicolumn{8}{|c|}{8 bits}&
3560 
\multicolumn{4}{c|}{4 bits}&
3561 
\multicolumn{8}{c|}{8 bits}&
3562 
\multicolumn{4}{c|}{4 bits}&
3563 
\multicolumn{8}{c|}{8 bits}\\
3564 
 
3565 
\hline
3566 
\end{tabular}\par}
3567 
\vspace{15mm}
3568 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3569 
\vspace{5mm}
3570 
\begin{quotation}
3571 
\texttt{\large l.dcbf\ J(rA)}{\large \par}
3572 
\end{quotation}
3573 
\vspace{10mm}
3574 
\textbf{\LARGE Description:}{\LARGE \par}
3575 
\vspace{5mm}
3576 
\begin{quotation}
3577 
\texttt{\large TBD}{\large \par}
3578 
\end{quotation}
3579 
\vspace{10mm}
3580 
\textbf{\LARGE Operation:}{\LARGE \par}
3581 
\vspace{5mm}
3582 
\begin{quotation}
3583 
 
3584 
\end{quotation}
3585 
\vspace{10mm}
3586 
\textbf{\LARGE Notes:}{\LARGE \par}
3587 
\vspace{5mm}
3588 
\begin{quotation}
3589 
 
3590 
\end{quotation}
3591 
\vspace{10mm}
3592 
\vfill
3593 
Class 5:
3594 
{\centering \begin{tabular}{|c|c|c|}
3595 
\hline
3596 
Architecture Level&
3597 
Execution Mode&
3598 
Implementation\\
3599 
\hline
3600 
Cache Management&Supervisor only&Mandatory if cache supported\\
3601 
\hline
3602 
\end{tabular}\par}
3603 
 
3604 
 
3605 
 
3606 
\newpage
3607 
\vspace{10mm}
3608 
\lyxline{\small}\vspace{-1\parskip}
3609 
\vspace{10mm}
3610 
{\raggedright \begin{tabular}{ccc}
3611 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3612 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3613 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3614 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3615 
\textbf{\huge l.dcbt}&
3616 
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Touch}}&
3617 
\textbf{\huge l.dcbt}\\
3618 
\end{tabular}\par}
3619 
\bigskip{}
3620 
 
3621 
\vspace{10mm}
3622 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3623 
\hline
3624 
31&
3625 
&
3626 
&
3627 
&
3628 
&
3629 
&
3630 
&
3631 
24&
3632 
23&
3633 
&
3634 
&
3635 
20&
3636 
19&
3637 
&
3638 
&
3639 
&
3640 
&
3641 
&
3642 
&
3643 
12&
3644 
11&
3645 
&
3646 
&
3647 
8&
3648 
7&
3649 
&
3650 
&
3651 
&
3652 
&
3653 
&
3654 
&
3655 
0\\
3656 
\hline
3657 
\multicolumn{8}{|c|}{opcode 0x30}&
3658 
\multicolumn{4}{c|}{A}&
3659 
\multicolumn{8}{c|}{I}&
3660 
\multicolumn{4}{c|}{opcode 0x1}&
3661 
\multicolumn{8}{c|}{I}\\
3662 
 
3663 
\hline
3664 
\multicolumn{8}{|c|}{8 bits}&
3665 
\multicolumn{4}{c|}{4 bits}&
3666 
\multicolumn{8}{c|}{8 bits}&
3667 
\multicolumn{4}{c|}{4 bits}&
3668 
\multicolumn{8}{c|}{8 bits}\\
3669 
 
3670 
\hline
3671 
\end{tabular}\par}
3672 
\vspace{15mm}
3673 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3674 
\vspace{5mm}
3675 
\begin{quotation}
3676 
\texttt{\large l.dcbt\ J(rA)}{\large \par}
3677 
\end{quotation}
3678 
\vspace{10mm}
3679 
\textbf{\LARGE Description:}{\LARGE \par}
3680 
\vspace{5mm}
3681 
\begin{quotation}
3682 
\texttt{\large TBD}{\large \par}
3683 
\end{quotation}
3684 
\vspace{10mm}
3685 
\textbf{\LARGE Operation:}{\LARGE \par}
3686 
\vspace{5mm}
3687 
\begin{quotation}
3688 
 
3689 
\end{quotation}
3690 
\vspace{10mm}
3691 
\textbf{\LARGE Notes:}{\LARGE \par}
3692 
\vspace{5mm}
3693 
\begin{quotation}
3694 
 
3695 
\end{quotation}
3696 
\vspace{10mm}
3697 
\vfill
3698 
Class 5:
3699 
{\centering \begin{tabular}{|c|c|c|}
3700 
\hline
3701 
Architecture Level&
3702 
Execution Mode&
3703 
Implementation\\
3704 
\hline
3705 
Cache Management&Supervisor only&Mandatory if cache supported\\
3706 
\hline
3707 
\end{tabular}\par}
3708 
 
3709 
 
3710 
 
3711 
\newpage
3712 
\vspace{10mm}
3713 
\lyxline{\small}\vspace{-1\parskip}
3714 
\vspace{10mm}
3715 
{\raggedright \begin{tabular}{ccc}
3716 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3717 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3718 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3719 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3720 
\textbf{\huge l.dcbi}&
3721 
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Invalidate}}&
3722 
\textbf{\huge l.dcbi}\\
3723 
\end{tabular}\par}
3724 
\bigskip{}
3725 
 
3726 
\vspace{10mm}
3727 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3728 
\hline
3729 
31&
3730 
&
3731 
&
3732 
&
3733 
&
3734 
&
3735 
&
3736 
24&
3737 
23&
3738 
&
3739 
&
3740 
20&
3741 
19&
3742 
&
3743 
&
3744 
&
3745 
&
3746 
&
3747 
&
3748 
12&
3749 
11&
3750 
&
3751 
&
3752 
8&
3753 
7&
3754 
&
3755 
&
3756 
&
3757 
&
3758 
&
3759 
&
3760 
0\\
3761 
\hline
3762 
\multicolumn{8}{|c|}{opcode 0x30}&
3763 
\multicolumn{4}{c|}{A}&
3764 
\multicolumn{8}{c|}{I}&
3765 
\multicolumn{4}{c|}{opcode 0x2}&
3766 
\multicolumn{8}{c|}{I}\\
3767 
 
3768 
\hline
3769 
\multicolumn{8}{|c|}{8 bits}&
3770 
\multicolumn{4}{c|}{4 bits}&
3771 
\multicolumn{8}{c|}{8 bits}&
3772 
\multicolumn{4}{c|}{4 bits}&
3773 
\multicolumn{8}{c|}{8 bits}\\
3774 
 
3775 
\hline
3776 
\end{tabular}\par}
3777 
\vspace{15mm}
3778 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3779 
\vspace{5mm}
3780 
\begin{quotation}
3781 
\texttt{\large l.dcbi\ J(rA)}{\large \par}
3782 
\end{quotation}
3783 
\vspace{10mm}
3784 
\textbf{\LARGE Description:}{\LARGE \par}
3785 
\vspace{5mm}
3786 
\begin{quotation}
3787 
\texttt{\large TBD}{\large \par}
3788 
\end{quotation}
3789 
\vspace{10mm}
3790 
\textbf{\LARGE Operation:}{\LARGE \par}
3791 
\vspace{5mm}
3792 
\begin{quotation}
3793 
 
3794 
\end{quotation}
3795 
\vspace{10mm}
3796 
\textbf{\LARGE Notes:}{\LARGE \par}
3797 
\vspace{5mm}
3798 
\begin{quotation}
3799 
 
3800 
\end{quotation}
3801 
\vspace{10mm}
3802 
\vfill
3803 
Class 5:
3804 
{\centering \begin{tabular}{|c|c|c|}
3805 
\hline
3806 
Architecture Level&
3807 
Execution Mode&
3808 
Implementation\\
3809 
\hline
3810 
Cache Management&Supervisor only&Mandatory if cache supported\\
3811 
\hline
3812 
\end{tabular}\par}
3813 
 
3814 
 
3815 
 
3816 
\newpage
3817 
\vspace{10mm}
3818 
\lyxline{\small}\vspace{-1\parskip}
3819 
\vspace{10mm}
3820 
{\raggedright \begin{tabular}{ccc}
3821 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3822 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3823 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3824 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3825 
\textbf{\huge l.dcia}&
3826 
\multicolumn{1}{c}{\textbf{\huge Data Cache Invalidate All}}&
3827 
\textbf{\huge l.dcia}\\
3828 
\end{tabular}\par}
3829 
\bigskip{}
3830 
 
3831 
\vspace{10mm}
3832 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3833 
\hline
3834 
31&
3835 
&
3836 
&
3837 
&
3838 
&
3839 
&
3840 
&
3841 
24&
3842 
23&
3843 
&
3844 
&
3845 
20&
3846 
19&
3847 
&
3848 
&
3849 
&
3850 
&
3851 
&
3852 
&
3853 
12&
3854 
11&
3855 
&
3856 
&
3857 
8&
3858 
7&
3859 
&
3860 
&
3861 
&
3862 
&
3863 
&
3864 
&
3865 
0\\
3866 
\hline
3867 
\multicolumn{8}{|c|}{opcode 0x30}&
3868 
\multicolumn{4}{c|}{A}&
3869 
\multicolumn{8}{c|}{reserved}&
3870 
\multicolumn{4}{c|}{opcode 0x3}&
3871 
\multicolumn{8}{c|}{reserved}\\
3872 
 
3873 
\hline
3874 
\multicolumn{8}{|c|}{8 bits}&
3875 
\multicolumn{4}{c|}{4 bits}&
3876 
\multicolumn{8}{c|}{8 bits}&
3877 
\multicolumn{4}{c|}{4 bits}&
3878 
\multicolumn{8}{c|}{8 bits}\\
3879 
 
3880 
\hline
3881 
\end{tabular}\par}
3882 
\vspace{15mm}
3883 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3884 
\vspace{5mm}
3885 
\begin{quotation}
3886 
\texttt{\large l.dcia\ }{\large \par}
3887 
\end{quotation}
3888 
\vspace{10mm}
3889 
\textbf{\LARGE Description:}{\LARGE \par}
3890 
\vspace{5mm}
3891 
\begin{quotation}
3892 
\texttt{\large TBD}{\large \par}
3893 
\end{quotation}
3894 
\vspace{10mm}
3895 
\textbf{\LARGE Operation:}{\LARGE \par}
3896 
\vspace{5mm}
3897 
\begin{quotation}
3898 
 
3899 
\end{quotation}
3900 
\vspace{10mm}
3901 
\textbf{\LARGE Notes:}{\LARGE \par}
3902 
\vspace{5mm}
3903 
\begin{quotation}
3904 
 
3905 
\end{quotation}
3906 
\vspace{10mm}
3907 
\vfill
3908 
Class 5:
3909 
{\centering \begin{tabular}{|c|c|c|}
3910 
\hline
3911 
Architecture Level&
3912 
Execution Mode&
3913 
Implementation\\
3914 
\hline
3915 
Cache Management&Supervisor only&Mandatory if cache supported\\
3916 
\hline
3917 
\end{tabular}\par}
3918 
 
3919 
 
3920 
 
3921 
\newpage
3922 
\vspace{10mm}
3923 
\lyxline{\small}\vspace{-1\parskip}
3924 
\vspace{10mm}
3925 
{\raggedright \begin{tabular}{ccc}
3926 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
3927 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
3928 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
3929 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
3930 
\textbf{\huge l.dcfa}&
3931 
\multicolumn{1}{c}{\textbf{\huge Data Cache Flush All}}&
3932 
\textbf{\huge l.dcfa}\\
3933 
\end{tabular}\par}
3934 
\bigskip{}
3935 
 
3936 
\vspace{10mm}
3937 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
3938 
\hline
3939 
31&
3940 
&
3941 
&
3942 
&
3943 
&
3944 
&
3945 
&
3946 
24&
3947 
23&
3948 
&
3949 
&
3950 
20&
3951 
19&
3952 
&
3953 
&
3954 
&
3955 
&
3956 
&
3957 
&
3958 
12&
3959 
11&
3960 
&
3961 
&
3962 
8&
3963 
7&
3964 
&
3965 
&
3966 
&
3967 
&
3968 
&
3969 
&
3970 
0\\
3971 
\hline
3972 
\multicolumn{8}{|c|}{opcode 0x30}&
3973 
\multicolumn{4}{c|}{A}&
3974 
\multicolumn{8}{c|}{reserved}&
3975 
\multicolumn{4}{c|}{opcode 0x4}&
3976 
\multicolumn{8}{c|}{reserved}\\
3977 
 
3978 
\hline
3979 
\multicolumn{8}{|c|}{8 bits}&
3980 
\multicolumn{4}{c|}{4 bits}&
3981 
\multicolumn{8}{c|}{8 bits}&
3982 
\multicolumn{4}{c|}{4 bits}&
3983 
\multicolumn{8}{c|}{8 bits}\\
3984 
 
3985 
\hline
3986 
\end{tabular}\par}
3987 
\vspace{15mm}
3988 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
3989 
\vspace{5mm}
3990 
\begin{quotation}
3991 
\texttt{\large l.dcfa\ }{\large \par}
3992 
\end{quotation}
3993 
\vspace{10mm}
3994 
\textbf{\LARGE Description:}{\LARGE \par}
3995 
\vspace{5mm}
3996 
\begin{quotation}
3997 
\texttt{\large TBD}{\large \par}
3998 
\end{quotation}
3999 
\vspace{10mm}
4000 
\textbf{\LARGE Operation:}{\LARGE \par}
4001 
\vspace{5mm}
4002 
\begin{quotation}
4003 
 
4004 
\end{quotation}
4005 
\vspace{10mm}
4006 
\textbf{\LARGE Notes:}{\LARGE \par}
4007 
\vspace{5mm}
4008 
\begin{quotation}
4009 
 
4010 
\end{quotation}
4011 
\vspace{10mm}
4012 
\vfill
4013 
Class 5:
4014 
{\centering \begin{tabular}{|c|c|c|}
4015 
\hline
4016 
Architecture Level&
4017 
Execution Mode&
4018 
Implementation\\
4019 
\hline
4020 
Cache Management&Supervisor only&Mandatory if cache supported\\
4021 
\hline
4022 
\end{tabular}\par}
4023 
 
4024 
 
4025 
 
4026 
\newpage
4027 
\vspace{10mm}
4028 
\lyxline{\small}\vspace{-1\parskip}
4029 
\vspace{10mm}
4030 
{\raggedright \begin{tabular}{ccc}
4031 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4032 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4033 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4034 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4035 
\textbf{\huge l.tlbia}&
4036 
\multicolumn{1}{c}{\textbf{\huge TLB Invalidate All}}&
4037 
\textbf{\huge l.tlbia}\\
4038 
\end{tabular}\par}
4039 
\bigskip{}
4040 
 
4041 
\vspace{10mm}
4042 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
4043 
\hline
4044 
31&
4045 
&
4046 
&
4047 
&
4048 
&
4049 
&
4050 
&
4051 
24&
4052 
23&
4053 
&
4054 
&
4055 
20&
4056 
19&
4057 
&
4058 
&
4059 
&
4060 
&
4061 
&
4062 
&
4063 
12&
4064 
11&
4065 
&
4066 
&
4067 
8&
4068 
7&
4069 
&
4070 
&
4071 
&
4072 
&
4073 
&
4074 
&
4075 
0\\
4076 
\hline
4077 
\multicolumn{8}{|c|}{opcode 0x30}&
4078 
\multicolumn{4}{c|}{A}&
4079 
\multicolumn{8}{c|}{reserved}&
4080 
\multicolumn{4}{c|}{opcode 0x5}&
4081 
\multicolumn{8}{c|}{reserved}\\
4082 
 
4083 
\hline
4084 
\multicolumn{8}{|c|}{8 bits}&
4085 
\multicolumn{4}{c|}{4 bits}&
4086 
\multicolumn{8}{c|}{8 bits}&
4087 
\multicolumn{4}{c|}{4 bits}&
4088 
\multicolumn{8}{c|}{8 bits}\\
4089 
 
4090 
\hline
4091 
\end{tabular}\par}
4092 
\vspace{15mm}
4093 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4094 
\vspace{5mm}
4095 
\begin{quotation}
4096 
\texttt{\large l.tlbia\ }{\large \par}
4097 
\end{quotation}
4098 
\vspace{10mm}
4099 
\textbf{\LARGE Description:}{\LARGE \par}
4100 
\vspace{5mm}
4101 
\begin{quotation}
4102 
\texttt{\large TBD}{\large \par}
4103 
\end{quotation}
4104 
\vspace{10mm}
4105 
\textbf{\LARGE Operation:}{\LARGE \par}
4106 
\vspace{5mm}
4107 
\begin{quotation}
4108 
 
4109 
\end{quotation}
4110 
\vspace{10mm}
4111 
\textbf{\LARGE Notes:}{\LARGE \par}
4112 
\vspace{5mm}
4113 
\begin{quotation}
4114 
 
4115 
\end{quotation}
4116 
\vspace{10mm}
4117 
\vfill
4118 
Class 6:
4119 
{\centering \begin{tabular}{|c|c|c|}
4120 
\hline
4121 
Architecture Level&
4122 
Execution Mode&
4123 
Implementation\\
4124 
\hline
4125 
Virtual Memory&Supervisor only&Mandatory if MMU supported\\
4126 
\hline
4127 
\end{tabular}\par}
4128 
 
4129 
 
4130 
 
4131 
\newpage
4132 
\vspace{10mm}
4133 
\lyxline{\small}\vspace{-1\parskip}
4134 
\vspace{10mm}
4135 
{\raggedright \begin{tabular}{ccc}
4136 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4137 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4138 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4139 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4140 
\textbf{\huge l.mtsr}&
4141 
\multicolumn{1}{c}{\textbf{\huge Move To Special Register}}&
4142 
\textbf{\huge l.mtsr}\\
4143 
\end{tabular}\par}
4144 
\bigskip{}
4145 
 
4146 
\vspace{10mm}
4147 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
4148 
\hline
4149 
31&
4150 
&
4151 
&
4152 
&
4153 
&
4154 
&
4155 
&
4156 
24&
4157 
23&
4158 
&
4159 
&
4160 
20&
4161 
19&
4162 
&
4163 
&
4164 
&
4165 
&
4166 
&
4167 
&
4168 
12&
4169 
11&
4170 
&
4171 
&
4172 
8&
4173 
7&
4174 
&
4175 
&
4176 
&
4177 
&
4178 
&
4179 
&
4180 
0\\
4181 
\hline
4182 
\multicolumn{8}{|c|}{opcode 0x30}&
4183 
\multicolumn{4}{c|}{A}&
4184 
\multicolumn{8}{c|}{S}&
4185 
\multicolumn{4}{c|}{opcode 0x6}&
4186 
\multicolumn{8}{c|}{S}\\
4187 
 
4188 
\hline
4189 
\multicolumn{8}{|c|}{8 bits}&
4190 
\multicolumn{4}{c|}{4 bits}&
4191 
\multicolumn{8}{c|}{8 bits}&
4192 
\multicolumn{4}{c|}{4 bits}&
4193 
\multicolumn{8}{c|}{8 bits}\\
4194 
 
4195 
\hline
4196 
\end{tabular}\par}
4197 
\vspace{15mm}
4198 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4199 
\vspace{5mm}
4200 
\begin{quotation}
4201 
\texttt{\large l.mtsr\ rS,rA}{\large \par}
4202 
\end{quotation}
4203 
\vspace{10mm}
4204 
\textbf{\LARGE Description:}{\LARGE \par}
4205 
\vspace{5mm}
4206 
\begin{quotation}
4207 
\texttt{\large The contents of general register rA are moved into special register rS.}{\large \par}
4208 
\end{quotation}
4209 
\vspace{10mm}
4210 
\textbf{\LARGE Operation:}{\LARGE \par}
4211 
\vspace{5mm}
4212 
\begin{quotation}
4213 
rS <- rA
4214 
\end{quotation}
4215 
\vspace{10mm}
4216 
\textbf{\LARGE Notes:}{\LARGE \par}
4217 
\vspace{5mm}
4218 
\begin{quotation}
4219 
 
4220 
\end{quotation}
4221 
\vspace{10mm}
4222 
\vfill
4223 
Class 4:
4224 
{\centering \begin{tabular}{|c|c|c|}
4225 
\hline
4226 
Architecture Level&
4227 
Execution Mode&
4228 
Implementation\\
4229 
\hline
4230 
System Management&Supervisor only&Mandatory always\\
4231 
\hline
4232 
\end{tabular}\par}
4233 
 
4234 
 
4235 
 
4236 
\newpage
4237 
\vspace{10mm}
4238 
\lyxline{\small}\vspace{-1\parskip}
4239 
\vspace{10mm}
4240 
{\raggedright \begin{tabular}{ccc}
4241 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4242 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4243 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4244 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4245 
\textbf{\huge l.mfsr}&
4246 
\multicolumn{1}{c}{\textbf{\huge Move From Special Register}}&
4247 
\textbf{\huge l.mfsr}\\
4248 
\end{tabular}\par}
4249 
\bigskip{}
4250 
 
4251 
\vspace{10mm}
4252 
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
4253 
\hline
4254 
31&
4255 
&
4256 
&
4257 
&
4258 
&
4259 
&
4260 
&
4261 
24&
4262 
23&
4263 
&
4264 
&
4265 
20&
4266 
19&
4267 
&
4268 
&
4269 
&
4270 
&
4271 
&
4272 
&
4273 
12&
4274 
11&
4275 
&
4276 
&
4277 
8&
4278 
7&
4279 
&
4280 
&
4281 
&
4282 
&
4283 
&
4284 
&
4285 
0\\
4286 
\hline
4287 
\multicolumn{8}{|c|}{opcode 0x30}&
4288 
\multicolumn{4}{c|}{A}&
4289 
\multicolumn{8}{c|}{S}&
4290 
\multicolumn{4}{c|}{opcode 0x7}&
4291 
\multicolumn{8}{c|}{S}\\
4292 
 
4293 
\hline
4294 
\multicolumn{8}{|c|}{8 bits}&
4295 
\multicolumn{4}{c|}{4 bits}&
4296 
\multicolumn{8}{c|}{8 bits}&
4297 
\multicolumn{4}{c|}{4 bits}&
4298 
\multicolumn{8}{c|}{8 bits}\\
4299 
 
4300 
\hline
4301 
\end{tabular}\par}
4302 
\vspace{15mm}
4303 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4304 
\vspace{5mm}
4305 
\begin{quotation}
4306 
\texttt{\large l.mfsr\ rA,rS}{\large \par}
4307 
\end{quotation}
4308 
\vspace{10mm}
4309 
\textbf{\LARGE Description:}{\LARGE \par}
4310 
\vspace{5mm}
4311 
\begin{quotation}
4312 
\texttt{\large The contents of special register rS are moved into general register rA.}{\large \par}
4313 
\end{quotation}
4314 
\vspace{10mm}
4315 
\textbf{\LARGE Operation:}{\LARGE \par}
4316 
\vspace{5mm}
4317 
\begin{quotation}
4318 
rA <- rS
4319 
\end{quotation}
4320 
\vspace{10mm}
4321 
\textbf{\LARGE Notes:}{\LARGE \par}
4322 
\vspace{5mm}
4323 
\begin{quotation}
4324 
 
4325 
\end{quotation}
4326 
\vspace{10mm}
4327 
\vfill
4328 
Class 4:
4329 
{\centering \begin{tabular}{|c|c|c|}
4330 
\hline
4331 
Architecture Level&
4332 
Execution Mode&
4333 
Implementation\\
4334 
\hline
4335 
System Management&Supervisor only&Mandatory always\\
4336 
\hline
4337 
\end{tabular}\par}
4338 
 
4339 
 
4340 
 
4341 
\newpage
4342 
\vspace{10mm}
4343 
\lyxline{\small}\vspace{-1\parskip}
4344 
\vspace{10mm}
4345 
{\raggedright \begin{tabular}{ccc}
4346 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4347 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4348 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4349 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4350 
\textbf{\huge h.sfeq32}&
4351 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Equal}}&
4352 
\textbf{\huge h.sfeq32}\\
4353 
\end{tabular}\par}
4354 
\bigskip{}
4355 
 
4356 
\vspace{10mm}
4357 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4358 
\hline
4359 
15&
4360 
&
4361 
&
4362 
&
4363 
&
4364 
&
4365 
&
4366 
8&
4367 
7&
4368 
&
4369 
&
4370 
4&
4371 
3&
4372 
&
4373 
&
4374 
0\\
4375 
\hline
4376 
\multicolumn{8}{|c|}{opcode 0x40}&
4377 
\multicolumn{4}{c|}{A}&
4378 
\multicolumn{4}{c|}{B}\\
4379 
 
4380 
\hline
4381 
\multicolumn{8}{|c|}{8 bits}&
4382 
\multicolumn{4}{c|}{4 bits}&
4383 
\multicolumn{4}{c|}{4 bits}\\
4384 
 
4385 
\hline
4386 
\end{tabular}\par}
4387 
\vspace{15mm}
4388 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4389 
\vspace{5mm}
4390 
\begin{quotation}
4391 
\texttt{\large h.sfeq32\ rA,rB}{\large \par}
4392 
\end{quotation}
4393 
\vspace{10mm}
4394 
\textbf{\LARGE Description:}{\LARGE \par}
4395 
\vspace{5mm}
4396 
\begin{quotation}
4397 
\texttt{\large The contents of general register rA and the contents of general register rB are compared. If the two registers are equal, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4398 
\end{quotation}
4399 
\vspace{10mm}
4400 
\textbf{\LARGE Operation:}{\LARGE \par}
4401 
\vspace{5mm}
4402 
\begin{quotation}
4403 
flag <- rA == rB
4404 
\end{quotation}
4405 
\vspace{10mm}
4406 
\textbf{\LARGE Notes:}{\LARGE \par}
4407 
\vspace{5mm}
4408 
\begin{quotation}
4409 
 
4410 
\end{quotation}
4411 
\vspace{10mm}
4412 
\vfill
4413 
Class 1:
4414 
{\centering \begin{tabular}{|c|c|c|}
4415 
\hline
4416 
Architecture Level&
4417 
Execution Mode&
4418 
Implementation\\
4419 
\hline
4420 
Core CPU&User and Supervisor&Mandatory always\\
4421 
\hline
4422 
\end{tabular}\par}
4423 
 
4424 
 
4425 
 
4426 
\newpage
4427 
\vspace{10mm}
4428 
\lyxline{\small}\vspace{-1\parskip}
4429 
\vspace{10mm}
4430 
{\raggedright \begin{tabular}{ccc}
4431 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4432 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4433 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4434 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4435 
\textbf{\huge h.sfne32}&
4436 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Not Equal}}&
4437 
\textbf{\huge h.sfne32}\\
4438 
\end{tabular}\par}
4439 
\bigskip{}
4440 
 
4441 
\vspace{10mm}
4442 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4443 
\hline
4444 
15&
4445 
&
4446 
&
4447 
&
4448 
&
4449 
&
4450 
&
4451 
8&
4452 
7&
4453 
&
4454 
&
4455 
4&
4456 
3&
4457 
&
4458 
&
4459 
0\\
4460 
\hline
4461 
\multicolumn{8}{|c|}{opcode 0x41}&
4462 
\multicolumn{4}{c|}{A}&
4463 
\multicolumn{4}{c|}{B}\\
4464 
 
4465 
\hline
4466 
\multicolumn{8}{|c|}{8 bits}&
4467 
\multicolumn{4}{c|}{4 bits}&
4468 
\multicolumn{4}{c|}{4 bits}\\
4469 
 
4470 
\hline
4471 
\end{tabular}\par}
4472 
\vspace{15mm}
4473 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4474 
\vspace{5mm}
4475 
\begin{quotation}
4476 
\texttt{\large h.sfne32\ rA,rB}{\large \par}
4477 
\end{quotation}
4478 
\vspace{10mm}
4479 
\textbf{\LARGE Description:}{\LARGE \par}
4480 
\vspace{5mm}
4481 
\begin{quotation}
4482 
\texttt{\large The contents of general register rA and the contents of general register rB are compared. If the two registers are not equal, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4483 
\end{quotation}
4484 
\vspace{10mm}
4485 
\textbf{\LARGE Operation:}{\LARGE \par}
4486 
\vspace{5mm}
4487 
\begin{quotation}
4488 
flag <- rA != rB
4489 
\end{quotation}
4490 
\vspace{10mm}
4491 
\textbf{\LARGE Notes:}{\LARGE \par}
4492 
\vspace{5mm}
4493 
\begin{quotation}
4494 
 
4495 
\end{quotation}
4496 
\vspace{10mm}
4497 
\vfill
4498 
Class 1:
4499 
{\centering \begin{tabular}{|c|c|c|}
4500 
\hline
4501 
Architecture Level&
4502 
Execution Mode&
4503 
Implementation\\
4504 
\hline
4505 
Core CPU&User and Supervisor&Mandatory always\\
4506 
\hline
4507 
\end{tabular}\par}
4508 
 
4509 
 
4510 
 
4511 
\newpage
4512 
\vspace{10mm}
4513 
\lyxline{\small}\vspace{-1\parskip}
4514 
\vspace{10mm}
4515 
{\raggedright \begin{tabular}{ccc}
4516 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4517 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4518 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4519 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4520 
\textbf{\huge h.sfgt32s}&
4521 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater Than Signed}}&
4522 
\textbf{\huge h.sfgt32s}\\
4523 
\end{tabular}\par}
4524 
\bigskip{}
4525 
 
4526 
\vspace{10mm}
4527 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4528 
\hline
4529 
15&
4530 
&
4531 
&
4532 
&
4533 
&
4534 
&
4535 
&
4536 
8&
4537 
7&
4538 
&
4539 
&
4540 
4&
4541 
3&
4542 
&
4543 
&
4544 
0\\
4545 
\hline
4546 
\multicolumn{8}{|c|}{opcode 0x42}&
4547 
\multicolumn{4}{c|}{A}&
4548 
\multicolumn{4}{c|}{B}\\
4549 
 
4550 
\hline
4551 
\multicolumn{8}{|c|}{8 bits}&
4552 
\multicolumn{4}{c|}{4 bits}&
4553 
\multicolumn{4}{c|}{4 bits}\\
4554 
 
4555 
\hline
4556 
\end{tabular}\par}
4557 
\vspace{15mm}
4558 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4559 
\vspace{5mm}
4560 
\begin{quotation}
4561 
\texttt{\large h.sfgt32s\ rA,rB}{\large \par}
4562 
\end{quotation}
4563 
\vspace{10mm}
4564 
\textbf{\LARGE Description:}{\LARGE \par}
4565 
\vspace{5mm}
4566 
\begin{quotation}
4567 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are greater than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4568 
\end{quotation}
4569 
\vspace{10mm}
4570 
\textbf{\LARGE Operation:}{\LARGE \par}
4571 
\vspace{5mm}
4572 
\begin{quotation}
4573 
flag <- rA > rB
4574 
\end{quotation}
4575 
\vspace{10mm}
4576 
\textbf{\LARGE Notes:}{\LARGE \par}
4577 
\vspace{5mm}
4578 
\begin{quotation}
4579 
 
4580 
\end{quotation}
4581 
\vspace{10mm}
4582 
\vfill
4583 
Class 1:
4584 
{\centering \begin{tabular}{|c|c|c|}
4585 
\hline
4586 
Architecture Level&
4587 
Execution Mode&
4588 
Implementation\\
4589 
\hline
4590 
Core CPU&User and Supervisor&Mandatory always\\
4591 
\hline
4592 
\end{tabular}\par}
4593 
 
4594 
 
4595 
 
4596 
\newpage
4597 
\vspace{10mm}
4598 
\lyxline{\small}\vspace{-1\parskip}
4599 
\vspace{10mm}
4600 
{\raggedright \begin{tabular}{ccc}
4601 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4602 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4603 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4604 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4605 
\textbf{\huge h.sfge32s}&
4606 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater or Equal Than Signed}}&
4607 
\textbf{\huge h.sfge32s}\\
4608 
\end{tabular}\par}
4609 
\bigskip{}
4610 
 
4611 
\vspace{10mm}
4612 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4613 
\hline
4614 
15&
4615 
&
4616 
&
4617 
&
4618 
&
4619 
&
4620 
&
4621 
8&
4622 
7&
4623 
&
4624 
&
4625 
4&
4626 
3&
4627 
&
4628 
&
4629 
0\\
4630 
\hline
4631 
\multicolumn{8}{|c|}{opcode 0x43}&
4632 
\multicolumn{4}{c|}{A}&
4633 
\multicolumn{4}{c|}{B}\\
4634 
 
4635 
\hline
4636 
\multicolumn{8}{|c|}{8 bits}&
4637 
\multicolumn{4}{c|}{4 bits}&
4638 
\multicolumn{4}{c|}{4 bits}\\
4639 
 
4640 
\hline
4641 
\end{tabular}\par}
4642 
\vspace{15mm}
4643 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4644 
\vspace{5mm}
4645 
\begin{quotation}
4646 
\texttt{\large h.sfge32s\ rA,rB}{\large \par}
4647 
\end{quotation}
4648 
\vspace{10mm}
4649 
\textbf{\LARGE Description:}{\LARGE \par}
4650 
\vspace{5mm}
4651 
\begin{quotation}
4652 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are greater or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4653 
\end{quotation}
4654 
\vspace{10mm}
4655 
\textbf{\LARGE Operation:}{\LARGE \par}
4656 
\vspace{5mm}
4657 
\begin{quotation}
4658 
flag <- rA >= rB
4659 
\end{quotation}
4660 
\vspace{10mm}
4661 
\textbf{\LARGE Notes:}{\LARGE \par}
4662 
\vspace{5mm}
4663 
\begin{quotation}
4664 
 
4665 
\end{quotation}
4666 
\vspace{10mm}
4667 
\vfill
4668 
Class 1:
4669 
{\centering \begin{tabular}{|c|c|c|}
4670 
\hline
4671 
Architecture Level&
4672 
Execution Mode&
4673 
Implementation\\
4674 
\hline
4675 
Core CPU&User and Supervisor&Mandatory always\\
4676 
\hline
4677 
\end{tabular}\par}
4678 
 
4679 
 
4680 
 
4681 
\newpage
4682 
\vspace{10mm}
4683 
\lyxline{\small}\vspace{-1\parskip}
4684 
\vspace{10mm}
4685 
{\raggedright \begin{tabular}{ccc}
4686 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4687 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4688 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4689 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4690 
\textbf{\huge h.sflt32s}&
4691 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less Than Signed}}&
4692 
\textbf{\huge h.sflt32s}\\
4693 
\end{tabular}\par}
4694 
\bigskip{}
4695 
 
4696 
\vspace{10mm}
4697 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4698 
\hline
4699 
15&
4700 
&
4701 
&
4702 
&
4703 
&
4704 
&
4705 
&
4706 
8&
4707 
7&
4708 
&
4709 
&
4710 
4&
4711 
3&
4712 
&
4713 
&
4714 
0\\
4715 
\hline
4716 
\multicolumn{8}{|c|}{opcode 0x44}&
4717 
\multicolumn{4}{c|}{A}&
4718 
\multicolumn{4}{c|}{B}\\
4719 
 
4720 
\hline
4721 
\multicolumn{8}{|c|}{8 bits}&
4722 
\multicolumn{4}{c|}{4 bits}&
4723 
\multicolumn{4}{c|}{4 bits}\\
4724 
 
4725 
\hline
4726 
\end{tabular}\par}
4727 
\vspace{15mm}
4728 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4729 
\vspace{5mm}
4730 
\begin{quotation}
4731 
\texttt{\large h.sflt32s\ rA,rB}{\large \par}
4732 
\end{quotation}
4733 
\vspace{10mm}
4734 
\textbf{\LARGE Description:}{\LARGE \par}
4735 
\vspace{5mm}
4736 
\begin{quotation}
4737 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are less than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4738 
\end{quotation}
4739 
\vspace{10mm}
4740 
\textbf{\LARGE Operation:}{\LARGE \par}
4741 
\vspace{5mm}
4742 
\begin{quotation}
4743 
flag <- rA < rB
4744 
\end{quotation}
4745 
\vspace{10mm}
4746 
\textbf{\LARGE Notes:}{\LARGE \par}
4747 
\vspace{5mm}
4748 
\begin{quotation}
4749 
 
4750 
\end{quotation}
4751 
\vspace{10mm}
4752 
\vfill
4753 
Class 1:
4754 
{\centering \begin{tabular}{|c|c|c|}
4755 
\hline
4756 
Architecture Level&
4757 
Execution Mode&
4758 
Implementation\\
4759 
\hline
4760 
Core CPU&User and Supervisor&Mandatory always\\
4761 
\hline
4762 
\end{tabular}\par}
4763 
 
4764 
 
4765 
 
4766 
\newpage
4767 
\vspace{10mm}
4768 
\lyxline{\small}\vspace{-1\parskip}
4769 
\vspace{10mm}
4770 
{\raggedright \begin{tabular}{ccc}
4771 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4772 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4773 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4774 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4775 
\textbf{\huge h.sfle32s}&
4776 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less or Equal Than Signed}}&
4777 
\textbf{\huge h.sfle32s}\\
4778 
\end{tabular}\par}
4779 
\bigskip{}
4780 
 
4781 
\vspace{10mm}
4782 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4783 
\hline
4784 
15&
4785 
&
4786 
&
4787 
&
4788 
&
4789 
&
4790 
&
4791 
8&
4792 
7&
4793 
&
4794 
&
4795 
4&
4796 
3&
4797 
&
4798 
&
4799 
0\\
4800 
\hline
4801 
\multicolumn{8}{|c|}{opcode 0x45}&
4802 
\multicolumn{4}{c|}{A}&
4803 
\multicolumn{4}{c|}{B}\\
4804 
 
4805 
\hline
4806 
\multicolumn{8}{|c|}{8 bits}&
4807 
\multicolumn{4}{c|}{4 bits}&
4808 
\multicolumn{4}{c|}{4 bits}\\
4809 
 
4810 
\hline
4811 
\end{tabular}\par}
4812 
\vspace{15mm}
4813 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4814 
\vspace{5mm}
4815 
\begin{quotation}
4816 
\texttt{\large h.sfle32s\ rA,rB}{\large \par}
4817 
\end{quotation}
4818 
\vspace{10mm}
4819 
\textbf{\LARGE Description:}{\LARGE \par}
4820 
\vspace{5mm}
4821 
\begin{quotation}
4822 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are less or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4823 
\end{quotation}
4824 
\vspace{10mm}
4825 
\textbf{\LARGE Operation:}{\LARGE \par}
4826 
\vspace{5mm}
4827 
\begin{quotation}
4828 
flag <- rA <= rB
4829 
\end{quotation}
4830 
\vspace{10mm}
4831 
\textbf{\LARGE Notes:}{\LARGE \par}
4832 
\vspace{5mm}
4833 
\begin{quotation}
4834 
 
4835 
\end{quotation}
4836 
\vspace{10mm}
4837 
\vfill
4838 
Class 1:
4839 
{\centering \begin{tabular}{|c|c|c|}
4840 
\hline
4841 
Architecture Level&
4842 
Execution Mode&
4843 
Implementation\\
4844 
\hline
4845 
Core CPU&User and Supervisor&Mandatory always\\
4846 
\hline
4847 
\end{tabular}\par}
4848 
 
4849 
 
4850 
 
4851 
\newpage
4852 
\vspace{10mm}
4853 
\lyxline{\small}\vspace{-1\parskip}
4854 
\vspace{10mm}
4855 
{\raggedright \begin{tabular}{ccc}
4856 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4857 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4858 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4859 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4860 
\textbf{\huge h.sfgt32u}&
4861 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater Than Unsigned}}&
4862 
\textbf{\huge h.sfgt32u}\\
4863 
\end{tabular}\par}
4864 
\bigskip{}
4865 
 
4866 
\vspace{10mm}
4867 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4868 
\hline
4869 
15&
4870 
&
4871 
&
4872 
&
4873 
&
4874 
&
4875 
&
4876 
8&
4877 
7&
4878 
&
4879 
&
4880 
4&
4881 
3&
4882 
&
4883 
&
4884 
0\\
4885 
\hline
4886 
\multicolumn{8}{|c|}{opcode 0x46}&
4887 
\multicolumn{4}{c|}{A}&
4888 
\multicolumn{4}{c|}{B}\\
4889 
 
4890 
\hline
4891 
\multicolumn{8}{|c|}{8 bits}&
4892 
\multicolumn{4}{c|}{4 bits}&
4893 
\multicolumn{4}{c|}{4 bits}\\
4894 
 
4895 
\hline
4896 
\end{tabular}\par}
4897 
\vspace{15mm}
4898 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4899 
\vspace{5mm}
4900 
\begin{quotation}
4901 
\texttt{\large h.sfgt32u\ rA,rB}{\large \par}
4902 
\end{quotation}
4903 
\vspace{10mm}
4904 
\textbf{\LARGE Description:}{\LARGE \par}
4905 
\vspace{5mm}
4906 
\begin{quotation}
4907 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are greater than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4908 
\end{quotation}
4909 
\vspace{10mm}
4910 
\textbf{\LARGE Operation:}{\LARGE \par}
4911 
\vspace{5mm}
4912 
\begin{quotation}
4913 
flag <- rA > rB
4914 
\end{quotation}
4915 
\vspace{10mm}
4916 
\textbf{\LARGE Notes:}{\LARGE \par}
4917 
\vspace{5mm}
4918 
\begin{quotation}
4919 
 
4920 
\end{quotation}
4921 
\vspace{10mm}
4922 
\vfill
4923 
Class 1:
4924 
{\centering \begin{tabular}{|c|c|c|}
4925 
\hline
4926 
Architecture Level&
4927 
Execution Mode&
4928 
Implementation\\
4929 
\hline
4930 
Core CPU&User and Supervisor&Mandatory always\\
4931 
\hline
4932 
\end{tabular}\par}
4933 
 
4934 
 
4935 
 
4936 
\newpage
4937 
\vspace{10mm}
4938 
\lyxline{\small}\vspace{-1\parskip}
4939 
\vspace{10mm}
4940 
{\raggedright \begin{tabular}{ccc}
4941 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
4942 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
4943 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
4944 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
4945 
\textbf{\huge h.sfge32u}&
4946 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater or Equal Than Unsigned}}&
4947 
\textbf{\huge h.sfge32u}\\
4948 
\end{tabular}\par}
4949 
\bigskip{}
4950 
 
4951 
\vspace{10mm}
4952 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
4953 
\hline
4954 
15&
4955 
&
4956 
&
4957 
&
4958 
&
4959 
&
4960 
&
4961 
8&
4962 
7&
4963 
&
4964 
&
4965 
4&
4966 
3&
4967 
&
4968 
&
4969 
0\\
4970 
\hline
4971 
\multicolumn{8}{|c|}{opcode 0x47}&
4972 
\multicolumn{4}{c|}{A}&
4973 
\multicolumn{4}{c|}{B}\\
4974 
 
4975 
\hline
4976 
\multicolumn{8}{|c|}{8 bits}&
4977 
\multicolumn{4}{c|}{4 bits}&
4978 
\multicolumn{4}{c|}{4 bits}\\
4979 
 
4980 
\hline
4981 
\end{tabular}\par}
4982 
\vspace{15mm}
4983 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
4984 
\vspace{5mm}
4985 
\begin{quotation}
4986 
\texttt{\large h.sfge32u\ rA,rB}{\large \par}
4987 
\end{quotation}
4988 
\vspace{10mm}
4989 
\textbf{\LARGE Description:}{\LARGE \par}
4990 
\vspace{5mm}
4991 
\begin{quotation}
4992 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are greater or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
4993 
\end{quotation}
4994 
\vspace{10mm}
4995 
\textbf{\LARGE Operation:}{\LARGE \par}
4996 
\vspace{5mm}
4997 
\begin{quotation}
4998 
flag <- rA >= rB
4999 
\end{quotation}
5000 
\vspace{10mm}
5001 
\textbf{\LARGE Notes:}{\LARGE \par}
5002 
\vspace{5mm}
5003 
\begin{quotation}
5004 
 
5005 
\end{quotation}
5006 
\vspace{10mm}
5007 
\vfill
5008 
Class 1:
5009 
{\centering \begin{tabular}{|c|c|c|}
5010 
\hline
5011 
Architecture Level&
5012 
Execution Mode&
5013 
Implementation\\
5014 
\hline
5015 
Core CPU&User and Supervisor&Mandatory always\\
5016 
\hline
5017 
\end{tabular}\par}
5018 
 
5019 
 
5020 
 
5021 
\newpage
5022 
\vspace{10mm}
5023 
\lyxline{\small}\vspace{-1\parskip}
5024 
\vspace{10mm}
5025 
{\raggedright \begin{tabular}{ccc}
5026 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5027 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5028 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5029 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5030 
\textbf{\huge h.sflt32u}&
5031 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less Than Unsigned}}&
5032 
\textbf{\huge h.sflt32u}\\
5033 
\end{tabular}\par}
5034 
\bigskip{}
5035 
 
5036 
\vspace{10mm}
5037 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
5038 
\hline
5039 
15&
5040 
&
5041 
&
5042 
&
5043 
&
5044 
&
5045 
&
5046 
8&
5047 
7&
5048 
&
5049 
&
5050 
4&
5051 
3&
5052 
&
5053 
&
5054 
0\\
5055 
\hline
5056 
\multicolumn{8}{|c|}{opcode 0x48}&
5057 
\multicolumn{4}{c|}{A}&
5058 
\multicolumn{4}{c|}{B}\\
5059 
 
5060 
\hline
5061 
\multicolumn{8}{|c|}{8 bits}&
5062 
\multicolumn{4}{c|}{4 bits}&
5063 
\multicolumn{4}{c|}{4 bits}\\
5064 
 
5065 
\hline
5066 
\end{tabular}\par}
5067 
\vspace{15mm}
5068 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5069 
\vspace{5mm}
5070 
\begin{quotation}
5071 
\texttt{\large h.sflt32u\ rA,rB}{\large \par}
5072 
\end{quotation}
5073 
\vspace{10mm}
5074 
\textbf{\LARGE Description:}{\LARGE \par}
5075 
\vspace{5mm}
5076 
\begin{quotation}
5077 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are less than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
5078 
\end{quotation}
5079 
\vspace{10mm}
5080 
\textbf{\LARGE Operation:}{\LARGE \par}
5081 
\vspace{5mm}
5082 
\begin{quotation}
5083 
flag <- rA < rB
5084 
\end{quotation}
5085 
\vspace{10mm}
5086 
\textbf{\LARGE Notes:}{\LARGE \par}
5087 
\vspace{5mm}
5088 
\begin{quotation}
5089 
 
5090 
\end{quotation}
5091 
\vspace{10mm}
5092 
\vfill
5093 
Class 1:
5094 
{\centering \begin{tabular}{|c|c|c|}
5095 
\hline
5096 
Architecture Level&
5097 
Execution Mode&
5098 
Implementation\\
5099 
\hline
5100 
Core CPU&User and Supervisor&Mandatory always\\
5101 
\hline
5102 
\end{tabular}\par}
5103 
 
5104 
 
5105 
 
5106 
\newpage
5107 
\vspace{10mm}
5108 
\lyxline{\small}\vspace{-1\parskip}
5109 
\vspace{10mm}
5110 
{\raggedright \begin{tabular}{ccc}
5111 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5112 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5113 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5114 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5115 
\textbf{\huge h.sfle32u}&
5116 
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less or Equal Than Unsigned}}&
5117 
\textbf{\huge h.sfle32u}\\
5118 
\end{tabular}\par}
5119 
\bigskip{}
5120 
 
5121 
\vspace{10mm}
5122 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
5123 
\hline
5124 
15&
5125 
&
5126 
&
5127 
&
5128 
&
5129 
&
5130 
&
5131 
8&
5132 
7&
5133 
&
5134 
&
5135 
4&
5136 
3&
5137 
&
5138 
&
5139 
0\\
5140 
\hline
5141 
\multicolumn{8}{|c|}{opcode 0x49}&
5142 
\multicolumn{4}{c|}{A}&
5143 
\multicolumn{4}{c|}{B}\\
5144 
 
5145 
\hline
5146 
\multicolumn{8}{|c|}{8 bits}&
5147 
\multicolumn{4}{c|}{4 bits}&
5148 
\multicolumn{4}{c|}{4 bits}\\
5149 
 
5150 
\hline
5151 
\end{tabular}\par}
5152 
\vspace{15mm}
5153 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5154 
\vspace{5mm}
5155 
\begin{quotation}
5156 
\texttt{\large h.sfle32u\ rA,rB}{\large \par}
5157 
\end{quotation}
5158 
\vspace{10mm}
5159 
\textbf{\LARGE Description:}{\LARGE \par}
5160 
\vspace{5mm}
5161 
\begin{quotation}
5162 
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are less or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
5163 
\end{quotation}
5164 
\vspace{10mm}
5165 
\textbf{\LARGE Operation:}{\LARGE \par}
5166 
\vspace{5mm}
5167 
\begin{quotation}
5168 
flag <- rA <= rB
5169 
\end{quotation}
5170 
\vspace{10mm}
5171 
\textbf{\LARGE Notes:}{\LARGE \par}
5172 
\vspace{5mm}
5173 
\begin{quotation}
5174 
 
5175 
\end{quotation}
5176 
\vspace{10mm}
5177 
\vfill
5178 
Class 1:
5179 
{\centering \begin{tabular}{|c|c|c|}
5180 
\hline
5181 
Architecture Level&
5182 
Execution Mode&
5183 
Implementation\\
5184 
\hline
5185 
Core CPU&User and Supervisor&Mandatory always\\
5186 
\hline
5187 
\end{tabular}\par}
5188 
 
5189 
 
5190 
 
5191 
\newpage
5192 
\vspace{10mm}
5193 
\lyxline{\small}\vspace{-1\parskip}
5194 
\vspace{10mm}
5195 
{\raggedright \begin{tabular}{ccc}
5196 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5197 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5198 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5199 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5200 
\textbf{\huge h.mov32}&
5201 
\multicolumn{1}{c}{\textbf{\huge Move}}&
5202 
\textbf{\huge h.mov32}\\
5203 
\end{tabular}\par}
5204 
\bigskip{}
5205 
 
5206 
\vspace{10mm}
5207 
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
5208 
\hline
5209 
15&
5210 
&
5211 
&
5212 
&
5213 
&
5214 
&
5215 
&
5216 
8&
5217 
7&
5218 
&
5219 
&
5220 
4&
5221 
3&
5222 
&
5223 
&
5224 
0\\
5225 
\hline
5226 
\multicolumn{8}{|c|}{opcode 0x4a}&
5227 
\multicolumn{4}{c|}{A}&
5228 
\multicolumn{4}{c|}{B}\\
5229 
 
5230 
\hline
5231 
\multicolumn{8}{|c|}{8 bits}&
5232 
\multicolumn{4}{c|}{4 bits}&
5233 
\multicolumn{4}{c|}{4 bits}\\
5234 
 
5235 
\hline
5236 
\end{tabular}\par}
5237 
\vspace{15mm}
5238 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5239 
\vspace{5mm}
5240 
\begin{quotation}
5241 
\texttt{\large h.mov32\ rA,rB}{\large \par}
5242 
\end{quotation}
5243 
\vspace{10mm}
5244 
\textbf{\LARGE Description:}{\LARGE \par}
5245 
\vspace{5mm}
5246 
\begin{quotation}
5247 
\texttt{\large The contents of general register rB are moved into general register rA.}{\large \par}
5248 
\end{quotation}
5249 
\vspace{10mm}
5250 
\textbf{\LARGE Operation:}{\LARGE \par}
5251 
\vspace{5mm}
5252 
\begin{quotation}
5253 
rA <- rB
5254 
\end{quotation}
5255 
\vspace{10mm}
5256 
\textbf{\LARGE Notes:}{\LARGE \par}
5257 
\vspace{5mm}
5258 
\begin{quotation}
5259 
 
5260 
\end{quotation}
5261 
\vspace{10mm}
5262 
\vfill
5263 
Class 2:
5264 
{\centering \begin{tabular}{|c|c|c|}
5265 
\hline
5266 
Architecture Level&
5267 
Execution Mode&
5268 
Implementation\\
5269 
\hline
5270 
Core CPU&User and Supervisor&Recommended\\
5271 
\hline
5272 
\end{tabular}\par}
5273 
 
5274 
 
5275 
 
5276 
\newpage
5277 
\vspace{10mm}
5278 
\lyxline{\small}\vspace{-1\parskip}
5279 
\vspace{10mm}
5280 
{\raggedright \begin{tabular}{ccc}
5281 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5282 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5283 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5284 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5285 
\textbf{\huge h.ext16s}&
5286 
\multicolumn{1}{c}{\textbf{\huge Extend Half Word with Sign}}&
5287 
\textbf{\huge h.ext16s}\\
5288 
\end{tabular}\par}
5289 
\bigskip{}
5290 
 
5291 
\vspace{10mm}
5292 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5293 
\hline
5294 
15&
5295 
&
5296 
&
5297 
&
5298 
&
5299 
&
5300 
&
5301 
8&
5302 
7&
5303 
&
5304 
&
5305 
4&
5306 
3&
5307 
2&
5308 
&
5309 
0\\
5310 
\hline
5311 
\multicolumn{8}{|c|}{opcode 0x4b}&
5312 
\multicolumn{4}{c|}{A}&
5313 
\multicolumn{1}{c|}{reserved}&
5314 
\multicolumn{3}{c|}{opcode 0x0}\\
5315 
 
5316 
\hline
5317 
\multicolumn{8}{|c|}{8 bits}&
5318 
\multicolumn{4}{c|}{4 bits}&
5319 
\multicolumn{1}{c|}{1 bits}&
5320 
\multicolumn{3}{c|}{3 bits}\\
5321 
 
5322 
\hline
5323 
\end{tabular}\par}
5324 
\vspace{15mm}
5325 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5326 
\vspace{5mm}
5327 
\begin{quotation}
5328 
\texttt{\large h.ext16s\ rA}{\large \par}
5329 
\end{quotation}
5330 
\vspace{10mm}
5331 
\textbf{\LARGE Description:}{\LARGE \par}
5332 
\vspace{5mm}
5333 
\begin{quotation}
5334 
\texttt{\large Bit 15 of general register rA is placed in high-order 16 bits of general register rA. The low-order 16 bits of general register rA are left unchanged.}{\large \par}
5335 
\end{quotation}
5336 
\vspace{10mm}
5337 
\textbf{\LARGE Operation:}{\LARGE \par}
5338 
\vspace{5mm}
5339 
\begin{quotation}
5340 
rA{[}31:16{]} <- rA{[}15{]}
5341 
\end{quotation}
5342 
\vspace{10mm}
5343 
\textbf{\LARGE Notes:}{\LARGE \par}
5344 
\vspace{5mm}
5345 
\begin{quotation}
5346 
 
5347 
\end{quotation}
5348 
\vspace{10mm}
5349 
\vfill
5350 
Class 2:
5351 
{\centering \begin{tabular}{|c|c|c|}
5352 
\hline
5353 
Architecture Level&
5354 
Execution Mode&
5355 
Implementation\\
5356 
\hline
5357 
Core CPU&User and Supervisor&Recommended\\
5358 
\hline
5359 
\end{tabular}\par}
5360 
 
5361 
 
5362 
 
5363 
\newpage
5364 
\vspace{10mm}
5365 
\lyxline{\small}\vspace{-1\parskip}
5366 
\vspace{10mm}
5367 
{\raggedright \begin{tabular}{ccc}
5368 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5369 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5370 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5371 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5372 
\textbf{\huge h.ext16z}&
5373 
\multicolumn{1}{c}{\textbf{\huge Extend Half Word with Zero}}&
5374 
\textbf{\huge h.ext16z}\\
5375 
\end{tabular}\par}
5376 
\bigskip{}
5377 
 
5378 
\vspace{10mm}
5379 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5380 
\hline
5381 
15&
5382 
&
5383 
&
5384 
&
5385 
&
5386 
&
5387 
&
5388 
8&
5389 
7&
5390 
&
5391 
&
5392 
4&
5393 
3&
5394 
2&
5395 
&
5396 
0\\
5397 
\hline
5398 
\multicolumn{8}{|c|}{opcode 0x4b}&
5399 
\multicolumn{4}{c|}{A}&
5400 
\multicolumn{1}{c|}{reserved}&
5401 
\multicolumn{3}{c|}{opcode 0x1}\\
5402 
 
5403 
\hline
5404 
\multicolumn{8}{|c|}{8 bits}&
5405 
\multicolumn{4}{c|}{4 bits}&
5406 
\multicolumn{1}{c|}{1 bits}&
5407 
\multicolumn{3}{c|}{3 bits}\\
5408 
 
5409 
\hline
5410 
\end{tabular}\par}
5411 
\vspace{15mm}
5412 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5413 
\vspace{5mm}
5414 
\begin{quotation}
5415 
\texttt{\large h.ext16z\ rA}{\large \par}
5416 
\end{quotation}
5417 
\vspace{10mm}
5418 
\textbf{\LARGE Description:}{\LARGE \par}
5419 
\vspace{5mm}
5420 
\begin{quotation}
5421 
\texttt{\large Zero is placed in high-order 16 bits of general register rA. The low-order 16 bits of general register rA are left unchanged.}{\large \par}
5422 
\end{quotation}
5423 
\vspace{10mm}
5424 
\textbf{\LARGE Operation:}{\LARGE \par}
5425 
\vspace{5mm}
5426 
\begin{quotation}
5427 
rA{[}31:16{]} <- 0
5428 
\end{quotation}
5429 
\vspace{10mm}
5430 
\textbf{\LARGE Notes:}{\LARGE \par}
5431 
\vspace{5mm}
5432 
\begin{quotation}
5433 
 
5434 
\end{quotation}
5435 
\vspace{10mm}
5436 
\vfill
5437 
Class 2:
5438 
{\centering \begin{tabular}{|c|c|c|}
5439 
\hline
5440 
Architecture Level&
5441 
Execution Mode&
5442 
Implementation\\
5443 
\hline
5444 
Core CPU&User and Supervisor&Recommended\\
5445 
\hline
5446 
\end{tabular}\par}
5447 
 
5448 
 
5449 
 
5450 
\newpage
5451 
\vspace{10mm}
5452 
\lyxline{\small}\vspace{-1\parskip}
5453 
\vspace{10mm}
5454 
{\raggedright \begin{tabular}{ccc}
5455 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5456 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5457 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5458 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5459 
\textbf{\huge h.ext8s}&
5460 
\multicolumn{1}{c}{\textbf{\huge Extend Byte with Sign}}&
5461 
\textbf{\huge h.ext8s}\\
5462 
\end{tabular}\par}
5463 
\bigskip{}
5464 
 
5465 
\vspace{10mm}
5466 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5467 
\hline
5468 
15&
5469 
&
5470 
&
5471 
&
5472 
&
5473 
&
5474 
&
5475 
8&
5476 
7&
5477 
&
5478 
&
5479 
4&
5480 
3&
5481 
2&
5482 
&
5483 
0\\
5484 
\hline
5485 
\multicolumn{8}{|c|}{opcode 0x4b}&
5486 
\multicolumn{4}{c|}{A}&
5487 
\multicolumn{1}{c|}{reserved}&
5488 
\multicolumn{3}{c|}{opcode 0x2}\\
5489 
 
5490 
\hline
5491 
\multicolumn{8}{|c|}{8 bits}&
5492 
\multicolumn{4}{c|}{4 bits}&
5493 
\multicolumn{1}{c|}{1 bits}&
5494 
\multicolumn{3}{c|}{3 bits}\\
5495 
 
5496 
\hline
5497 
\end{tabular}\par}
5498 
\vspace{15mm}
5499 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5500 
\vspace{5mm}
5501 
\begin{quotation}
5502 
\texttt{\large h.ext8s\ rA}{\large \par}
5503 
\end{quotation}
5504 
\vspace{10mm}
5505 
\textbf{\LARGE Description:}{\LARGE \par}
5506 
\vspace{5mm}
5507 
\begin{quotation}
5508 
\texttt{\large Bit 7 of general register rA is placed in high-order 24 bits of general register rA. The low-order eight bits of general register rA are left unchanged.}{\large \par}
5509 
\end{quotation}
5510 
\vspace{10mm}
5511 
\textbf{\LARGE Operation:}{\LARGE \par}
5512 
\vspace{5mm}
5513 
\begin{quotation}
5514 
rA{[}31:8{]} <- rA{[}7{]}
5515 
\end{quotation}
5516 
\vspace{10mm}
5517 
\textbf{\LARGE Notes:}{\LARGE \par}
5518 
\vspace{5mm}
5519 
\begin{quotation}
5520 
 
5521 
\end{quotation}
5522 
\vspace{10mm}
5523 
\vfill
5524 
Class 2:
5525 
{\centering \begin{tabular}{|c|c|c|}
5526 
\hline
5527 
Architecture Level&
5528 
Execution Mode&
5529 
Implementation\\
5530 
\hline
5531 
Core CPU&User and Supervisor&Recommended\\
5532 
\hline
5533 
\end{tabular}\par}
5534 
 
5535 
 
5536 
 
5537 
\newpage
5538 
\vspace{10mm}
5539 
\lyxline{\small}\vspace{-1\parskip}
5540 
\vspace{10mm}
5541 
{\raggedright \begin{tabular}{ccc}
5542 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5543 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5544 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5545 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5546 
\textbf{\huge h.ext8z}&
5547 
\multicolumn{1}{c}{\textbf{\huge Extend Byte with Zero}}&
5548 
\textbf{\huge h.ext8z}\\
5549 
\end{tabular}\par}
5550 
\bigskip{}
5551 
 
5552 
\vspace{10mm}
5553 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5554 
\hline
5555 
15&
5556 
&
5557 
&
5558 
&
5559 
&
5560 
&
5561 
&
5562 
8&
5563 
7&
5564 
&
5565 
&
5566 
4&
5567 
3&
5568 
2&
5569 
&
5570 
0\\
5571 
\hline
5572 
\multicolumn{8}{|c|}{opcode 0x4b}&
5573 
\multicolumn{4}{c|}{A}&
5574 
\multicolumn{1}{c|}{reserved}&
5575 
\multicolumn{3}{c|}{opcode 0x3}\\
5576 
 
5577 
\hline
5578 
\multicolumn{8}{|c|}{8 bits}&
5579 
\multicolumn{4}{c|}{4 bits}&
5580 
\multicolumn{1}{c|}{1 bits}&
5581 
\multicolumn{3}{c|}{3 bits}\\
5582 
 
5583 
\hline
5584 
\end{tabular}\par}
5585 
\vspace{15mm}
5586 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5587 
\vspace{5mm}
5588 
\begin{quotation}
5589 
\texttt{\large h.ext8z\ rA}{\large \par}
5590 
\end{quotation}
5591 
\vspace{10mm}
5592 
\textbf{\LARGE Description:}{\LARGE \par}
5593 
\vspace{5mm}
5594 
\begin{quotation}
5595 
\texttt{\large Zero is placed in high-order 24 bits of general register rA. The low-order eight bits of general register rA are left unchanged.}{\large \par}
5596 
\end{quotation}
5597 
\vspace{10mm}
5598 
\textbf{\LARGE Operation:}{\LARGE \par}
5599 
\vspace{5mm}
5600 
\begin{quotation}
5601 
rA{[}31:8{]} <- 0
5602 
\end{quotation}
5603 
\vspace{10mm}
5604 
\textbf{\LARGE Notes:}{\LARGE \par}
5605 
\vspace{5mm}
5606 
\begin{quotation}
5607 
 
5608 
\end{quotation}
5609 
\vspace{10mm}
5610 
\vfill
5611 
Class 2:
5612 
{\centering \begin{tabular}{|c|c|c|}
5613 
\hline
5614 
Architecture Level&
5615 
Execution Mode&
5616 
Implementation\\
5617 
\hline
5618 
Core CPU&User and Supervisor&Recommended\\
5619 
\hline
5620 
\end{tabular}\par}
5621 
 
5622 
 
5623 
 
5624 
\newpage
5625 
\vspace{10mm}
5626 
\lyxline{\small}\vspace{-1\parskip}
5627 
\vspace{10mm}
5628 
{\raggedright \begin{tabular}{ccc}
5629 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5630 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5631 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5632 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5633 
\textbf{\huge h.nop}&
5634 
\multicolumn{1}{c}{\textbf{\huge No Operation}}&
5635 
\textbf{\huge h.nop}\\
5636 
\end{tabular}\par}
5637 
\bigskip{}
5638 
 
5639 
\vspace{10mm}
5640 
{\centering \begin{tabular}{|cccccccc|ccccc|ccc|}
5641 
\hline
5642 
15&
5643 
&
5644 
&
5645 
&
5646 
&
5647 
&
5648 
&
5649 
8&
5650 
7&
5651 
&
5652 
&
5653 
&
5654 
3&
5655 
2&
5656 
&
5657 
0\\
5658 
\hline
5659 
\multicolumn{8}{|c|}{opcode 0x4b}&
5660 
\multicolumn{5}{c|}{reserved}&
5661 
\multicolumn{3}{c|}{opcode 0x4}\\
5662 
 
5663 
\hline
5664 
\multicolumn{8}{|c|}{8 bits}&
5665 
\multicolumn{5}{c|}{5 bits}&
5666 
\multicolumn{3}{c|}{3 bits}\\
5667 
 
5668 
\hline
5669 
\end{tabular}\par}
5670 
\vspace{15mm}
5671 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5672 
\vspace{5mm}
5673 
\begin{quotation}
5674 
\texttt{\large h.nop\ }{\large \par}
5675 
\end{quotation}
5676 
\vspace{10mm}
5677 
\textbf{\LARGE Description:}{\LARGE \par}
5678 
\vspace{5mm}
5679 
\begin{quotation}
5680 
\texttt{\large This instruction does not do anything except it takes at least one clock cycle to complete. It is usually used to fill gaps between 16 bit and 32 bit instructions.}{\large \par}
5681 
\end{quotation}
5682 
\vspace{10mm}
5683 
\textbf{\LARGE Operation:}{\LARGE \par}
5684 
\vspace{5mm}
5685 
\begin{quotation}
5686 
 
5687 
\end{quotation}
5688 
\vspace{10mm}
5689 
\textbf{\LARGE Notes:}{\LARGE \par}
5690 
\vspace{5mm}
5691 
\begin{quotation}
5692 
 
5693 
\end{quotation}
5694 
\vspace{10mm}
5695 
\vfill
5696 
Class 1:
5697 
{\centering \begin{tabular}{|c|c|c|}
5698 
\hline
5699 
Architecture Level&
5700 
Execution Mode&
5701 
Implementation\\
5702 
\hline
5703 
Core CPU&User and Supervisor&Mandatory always\\
5704 
\hline
5705 
\end{tabular}\par}
5706 
 
5707 
 
5708 
 
5709 
\newpage
5710 
\vspace{10mm}
5711 
\lyxline{\small}\vspace{-1\parskip}
5712 
\vspace{10mm}
5713 
{\raggedright \begin{tabular}{ccc}
5714 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5715 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5716 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5717 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5718 
\textbf{\huge h.jalr}&
5719 
\multicolumn{1}{c}{\textbf{\huge Jump and Link Register}}&
5720 
\textbf{\huge h.jalr}\\
5721 
\end{tabular}\par}
5722 
\bigskip{}
5723 
 
5724 
\vspace{10mm}
5725 
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
5726 
\hline
5727 
15&
5728 
&
5729 
&
5730 
&
5731 
&
5732 
&
5733 
&
5734 
8&
5735 
7&
5736 
&
5737 
&
5738 
4&
5739 
3&
5740 
2&
5741 
&
5742 
0\\
5743 
\hline
5744 
\multicolumn{8}{|c|}{opcode 0x4b}&
5745 
\multicolumn{4}{c|}{A}&
5746 
\multicolumn{1}{c|}{reserved}&
5747 
\multicolumn{3}{c|}{opcode 0x5}\\
5748 
 
5749 
\hline
5750 
\multicolumn{8}{|c|}{8 bits}&
5751 
\multicolumn{4}{c|}{4 bits}&
5752 
\multicolumn{1}{c|}{1 bits}&
5753 
\multicolumn{3}{c|}{3 bits}\\
5754 
 
5755 
\hline
5756 
\end{tabular}\par}
5757 
\vspace{15mm}
5758 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5759 
\vspace{5mm}
5760 
\begin{quotation}
5761 
\texttt{\large h.jalr\ rA}{\large \par}
5762 
\end{quotation}
5763 
\vspace{10mm}
5764 
\textbf{\LARGE Description:}{\LARGE \par}
5765 
\vspace{5mm}
5766 
\begin{quotation}
5767 
\texttt{\large The contents of general register rA is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
5768 
\end{quotation}
5769 
\vspace{10mm}
5770 
\textbf{\LARGE Operation:}{\LARGE \par}
5771 
\vspace{5mm}
5772 
\begin{quotation}
5773 
PC <- rA\\LR <- DelayInsnAddr + 4
5774 
\end{quotation}
5775 
\vspace{10mm}
5776 
\textbf{\LARGE Notes:}{\LARGE \par}
5777 
\vspace{5mm}
5778 
\begin{quotation}
5779 
 
5780 
\end{quotation}
5781 
\vspace{10mm}
5782 
\vfill
5783 
Class 1:
5784 
{\centering \begin{tabular}{|c|c|c|}
5785 
\hline
5786 
Architecture Level&
5787 
Execution Mode&
5788 
Implementation\\
5789 
\hline
5790 
Core CPU&User and Supervisor&Mandatory always\\
5791 
\hline
5792 
\end{tabular}\par}
5793 
 
5794 
 
5795 
 
5796 
\newpage
5797 
\vspace{10mm}
5798 
\lyxline{\small}\vspace{-1\parskip}
5799 
\vspace{10mm}
5800 
{\raggedright \begin{tabular}{ccc}
5801 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5802 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5803 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5804 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5805 
\textbf{\huge h.load32u}&
5806 
\multicolumn{1}{c}{\textbf{\huge Load Word and Extend with Zero}}&
5807 
\textbf{\huge h.load32u}\\
5808 
\end{tabular}\par}
5809 
\bigskip{}
5810 
 
5811 
\vspace{10mm}
5812 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
5813 
\hline
5814 
15&
5815 
&
5816 
&
5817 
12&
5818 
11&
5819 
&
5820 
&
5821 
8&
5822 
7&
5823 
&
5824 
&
5825 
4&
5826 
3&
5827 
&
5828 
&
5829 
0\\
5830 
\hline
5831 
\multicolumn{4}{|c|}{opcode 0x5}&
5832 
\multicolumn{4}{c|}{N}&
5833 
\multicolumn{4}{c|}{A}&
5834 
\multicolumn{4}{c|}{B}\\
5835 
 
5836 
\hline
5837 
\multicolumn{4}{|c|}{4 bits}&
5838 
\multicolumn{4}{c|}{4 bits}&
5839 
\multicolumn{4}{c|}{4 bits}&
5840 
\multicolumn{4}{c|}{4 bits}\\
5841 
 
5842 
\hline
5843 
\end{tabular}\par}
5844 
\vspace{15mm}
5845 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5846 
\vspace{5mm}
5847 
\begin{quotation}
5848 
\texttt{\large h.load32u\ rA,N(rB)}{\large \par}
5849 
\end{quotation}
5850 
\vspace{10mm}
5851 
\textbf{\LARGE Description:}{\LARGE \par}
5852 
\vspace{5mm}
5853 
\begin{quotation}
5854 
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The word in memory addressed by EA is loaded into general register rA. }{\large \par}
5855 
\end{quotation}
5856 
\vspace{10mm}
5857 
\textbf{\LARGE Operation:}{\LARGE \par}
5858 
\vspace{5mm}
5859 
\begin{quotation}
5860 
EA <- exts(Immediate) + rB\\rA <- (EA){[}31:0{]}
5861 
\end{quotation}
5862 
\vspace{10mm}
5863 
\textbf{\LARGE Notes:}{\LARGE \par}
5864 
\vspace{5mm}
5865 
\begin{quotation}
5866 
 
5867 
\end{quotation}
5868 
\vspace{10mm}
5869 
\vfill
5870 
Class 2:
5871 
{\centering \begin{tabular}{|c|c|c|}
5872 
\hline
5873 
Architecture Level&
5874 
Execution Mode&
5875 
Implementation\\
5876 
\hline
5877 
Core CPU&User and Supervisor&Recommended\\
5878 
\hline
5879 
\end{tabular}\par}
5880 
 
5881 
 
5882 
 
5883 
\newpage
5884 
\vspace{10mm}
5885 
\lyxline{\small}\vspace{-1\parskip}
5886 
\vspace{10mm}
5887 
{\raggedright \begin{tabular}{ccc}
5888 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5889 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5890 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5891 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5892 
\textbf{\huge h.stor32}&
5893 
\multicolumn{1}{c}{\textbf{\huge Store Word}}&
5894 
\textbf{\huge h.stor32}\\
5895 
\end{tabular}\par}
5896 
\bigskip{}
5897 
 
5898 
\vspace{10mm}
5899 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
5900 
\hline
5901 
15&
5902 
&
5903 
&
5904 
12&
5905 
11&
5906 
&
5907 
&
5908 
8&
5909 
7&
5910 
&
5911 
&
5912 
4&
5913 
3&
5914 
&
5915 
&
5916 
0\\
5917 
\hline
5918 
\multicolumn{4}{|c|}{opcode 0x6}&
5919 
\multicolumn{4}{c|}{N}&
5920 
\multicolumn{4}{c|}{A}&
5921 
\multicolumn{4}{c|}{B}\\
5922 
 
5923 
\hline
5924 
\multicolumn{4}{|c|}{4 bits}&
5925 
\multicolumn{4}{c|}{4 bits}&
5926 
\multicolumn{4}{c|}{4 bits}&
5927 
\multicolumn{4}{c|}{4 bits}\\
5928 
 
5929 
\hline
5930 
\end{tabular}\par}
5931 
\vspace{15mm}
5932 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
5933 
\vspace{5mm}
5934 
\begin{quotation}
5935 
\texttt{\large h.stor32\ N(rA),rB}{\large \par}
5936 
\end{quotation}
5937 
\vspace{10mm}
5938 
\textbf{\LARGE Description:}{\LARGE \par}
5939 
\vspace{5mm}
5940 
\begin{quotation}
5941 
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The word in general register rB is stored to memory addressed by EA. }{\large \par}
5942 
\end{quotation}
5943 
\vspace{10mm}
5944 
\textbf{\LARGE Operation:}{\LARGE \par}
5945 
\vspace{5mm}
5946 
\begin{quotation}
5947 
EA <- exts(Immediate) + rA\\(EA){[}31:0{]} <- rB
5948 
\end{quotation}
5949 
\vspace{10mm}
5950 
\textbf{\LARGE Notes:}{\LARGE \par}
5951 
\vspace{5mm}
5952 
\begin{quotation}
5953 
 
5954 
\end{quotation}
5955 
\vspace{10mm}
5956 
\vfill
5957 
Class 2:
5958 
{\centering \begin{tabular}{|c|c|c|}
5959 
\hline
5960 
Architecture Level&
5961 
Execution Mode&
5962 
Implementation\\
5963 
\hline
5964 
Core CPU&User and Supervisor&Recommended\\
5965 
\hline
5966 
\end{tabular}\par}
5967 
 
5968 
 
5969 
 
5970 
\newpage
5971 
\vspace{10mm}
5972 
\lyxline{\small}\vspace{-1\parskip}
5973 
\vspace{10mm}
5974 
{\raggedright \begin{tabular}{ccc}
5975 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
5976 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
5977 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
5978 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
5979 
\textbf{\huge h.add32s}&
5980 
\multicolumn{1}{c}{\textbf{\huge Add Signed}}&
5981 
\textbf{\huge h.add32s}\\
5982 
\end{tabular}\par}
5983 
\bigskip{}
5984 
 
5985 
\vspace{10mm}
5986 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
5987 
\hline
5988 
15&
5989 
&
5990 
&
5991 
12&
5992 
11&
5993 
&
5994 
&
5995 
8&
5996 
7&
5997 
&
5998 
&
5999 
4&
6000 
3&
6001 
&
6002 
&
6003 
0\\
6004 
\hline
6005 
\multicolumn{4}{|c|}{opcode 0x7}&
6006 
\multicolumn{4}{c|}{D}&
6007 
\multicolumn{4}{c|}{A}&
6008 
\multicolumn{4}{c|}{B}\\
6009 
 
6010 
\hline
6011 
\multicolumn{4}{|c|}{4 bits}&
6012 
\multicolumn{4}{c|}{4 bits}&
6013 
\multicolumn{4}{c|}{4 bits}&
6014 
\multicolumn{4}{c|}{4 bits}\\
6015 
 
6016 
\hline
6017 
\end{tabular}\par}
6018 
\vspace{15mm}
6019 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6020 
\vspace{5mm}
6021 
\begin{quotation}
6022 
\texttt{\large h.add32s\ rA,rB,rD}{\large \par}
6023 
\end{quotation}
6024 
\vspace{10mm}
6025 
\textbf{\LARGE Description:}{\LARGE \par}
6026 
\vspace{5mm}
6027 
\begin{quotation}
6028 
\texttt{\large The contents of general register rC is added to the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
6029 
\end{quotation}
6030 
\vspace{10mm}
6031 
\textbf{\LARGE Operation:}{\LARGE \par}
6032 
\vspace{5mm}
6033 
\begin{quotation}
6034 
rA <- rB + rC
6035 
\end{quotation}
6036 
\vspace{10mm}
6037 
\textbf{\LARGE Notes:}{\LARGE \par}
6038 
\vspace{5mm}
6039 
\begin{quotation}
6040 
 
6041 
\end{quotation}
6042 
\vspace{10mm}
6043 
\vfill
6044 
Class 1:
6045 
{\centering \begin{tabular}{|c|c|c|}
6046 
\hline
6047 
Architecture Level&
6048 
Execution Mode&
6049 
Implementation\\
6050 
\hline
6051 
Core CPU&User and Supervisor&Mandatory always\\
6052 
\hline
6053 
\end{tabular}\par}
6054 
 
6055 
 
6056 
 
6057 
\newpage
6058 
\vspace{10mm}
6059 
\lyxline{\small}\vspace{-1\parskip}
6060 
\vspace{10mm}
6061 
{\raggedright \begin{tabular}{ccc}
6062 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6063 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6064 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6065 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6066 
\textbf{\huge h.immch32s}&
6067 
\multicolumn{1}{c}{\textbf{\huge Immediate Byte Signed}}&
6068 
\textbf{\huge h.immch32s}\\
6069 
\end{tabular}\par}
6070 
\bigskip{}
6071 
 
6072 
\vspace{10mm}
6073 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
6074 
\hline
6075 
15&
6076 
&
6077 
&
6078 
12&
6079 
11&
6080 
&
6081 
&
6082 
8&
6083 
7&
6084 
&
6085 
&
6086 
4&
6087 
3&
6088 
&
6089 
&
6090 
0\\
6091 
\hline
6092 
\multicolumn{4}{|c|}{opcode 0x8}&
6093 
\multicolumn{4}{c|}{M}&
6094 
\multicolumn{4}{c|}{A}&
6095 
\multicolumn{4}{c|}{M}\\
6096 
 
6097 
\hline
6098 
\multicolumn{4}{|c|}{4 bits}&
6099 
\multicolumn{4}{c|}{4 bits}&
6100 
\multicolumn{4}{c|}{4 bits}&
6101 
\multicolumn{4}{c|}{4 bits}\\
6102 
 
6103 
\hline
6104 
\end{tabular}\par}
6105 
\vspace{15mm}
6106 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6107 
\vspace{5mm}
6108 
\begin{quotation}
6109 
\texttt{\large h.immch32s\ rA,M}{\large \par}
6110 
\end{quotation}
6111 
\vspace{10mm}
6112 
\textbf{\LARGE Description:}{\LARGE \par}
6113 
\vspace{5mm}
6114 
\begin{quotation}
6115 
\texttt{\large 8 bit immediate is sign-extended to 32 bits and placed into general register rA.}{\large \par}
6116 
\end{quotation}
6117 
\vspace{10mm}
6118 
\textbf{\LARGE Operation:}{\LARGE \par}
6119 
\vspace{5mm}
6120 
\begin{quotation}
6121 
rA <- exts(Immediate)
6122 
\end{quotation}
6123 
\vspace{10mm}
6124 
\textbf{\LARGE Notes:}{\LARGE \par}
6125 
\vspace{5mm}
6126 
\begin{quotation}
6127 
 
6128 
\end{quotation}
6129 
\vspace{10mm}
6130 
\vfill
6131 
Class 2:
6132 
{\centering \begin{tabular}{|c|c|c|}
6133 
\hline
6134 
Architecture Level&
6135 
Execution Mode&
6136 
Implementation\\
6137 
\hline
6138 
Core CPU&User and Supervisor&Recommended\\
6139 
\hline
6140 
\end{tabular}\par}
6141 
 
6142 
 
6143 
 
6144 
\newpage
6145 
\vspace{10mm}
6146 
\lyxline{\small}\vspace{-1\parskip}
6147 
\vspace{10mm}
6148 
{\raggedright \begin{tabular}{ccc}
6149 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6150 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6151 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6152 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6153 
\textbf{\huge h.jal}&
6154 
\multicolumn{1}{c}{\textbf{\huge Jump and Link}}&
6155 
\textbf{\huge h.jal}\\
6156 
\end{tabular}\par}
6157 
\bigskip{}
6158 
 
6159 
\vspace{10mm}
6160 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
6161 
\hline
6162 
15&
6163 
&
6164 
&
6165 
12&
6166 
11&
6167 
&
6168 
&
6169 
&
6170 
&
6171 
&
6172 
&
6173 
&
6174 
&
6175 
&
6176 
&
6177 
0\\
6178 
\hline
6179 
\multicolumn{4}{|c|}{opcode 0x9}&
6180 
\multicolumn{12}{c|}{X}\\
6181 
 
6182 
\hline
6183 
\multicolumn{4}{|c|}{4 bits}&
6184 
\multicolumn{12}{c|}{12 bits}\\
6185 
 
6186 
\hline
6187 
\end{tabular}\par}
6188 
\vspace{15mm}
6189 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6190 
\vspace{5mm}
6191 
\begin{quotation}
6192 
\texttt{\large h.jal\ X}{\large \par}
6193 
\end{quotation}
6194 
\vspace{10mm}
6195 
\textbf{\LARGE Description:}{\LARGE \par}
6196 
\vspace{5mm}
6197 
\begin{quotation}
6198 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
6199 
\end{quotation}
6200 
\vspace{10mm}
6201 
\textbf{\LARGE Operation:}{\LARGE \par}
6202 
\vspace{5mm}
6203 
\begin{quotation}
6204 
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
6205 
\end{quotation}
6206 
\vspace{10mm}
6207 
\textbf{\LARGE Notes:}{\LARGE \par}
6208 
\vspace{5mm}
6209 
\begin{quotation}
6210 
 
6211 
\end{quotation}
6212 
\vspace{10mm}
6213 
\vfill
6214 
Class 2:
6215 
{\centering \begin{tabular}{|c|c|c|}
6216 
\hline
6217 
Architecture Level&
6218 
Execution Mode&
6219 
Implementation\\
6220 
\hline
6221 
Core CPU&User and Supervisor&Recommended\\
6222 
\hline
6223 
\end{tabular}\par}
6224 
 
6225 
 
6226 
 
6227 
\newpage
6228 
\vspace{10mm}
6229 
\lyxline{\small}\vspace{-1\parskip}
6230 
\vspace{10mm}
6231 
{\raggedright \begin{tabular}{ccc}
6232 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6233 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6234 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6235 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6236 
\textbf{\huge h.bnf}&
6237 
\multicolumn{1}{c}{\textbf{\huge Branch if No Flag}}&
6238 
\textbf{\huge h.bnf}\\
6239 
\end{tabular}\par}
6240 
\bigskip{}
6241 
 
6242 
\vspace{10mm}
6243 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
6244 
\hline
6245 
15&
6246 
&
6247 
&
6248 
12&
6249 
11&
6250 
&
6251 
&
6252 
&
6253 
&
6254 
&
6255 
&
6256 
&
6257 
&
6258 
&
6259 
&
6260 
0\\
6261 
\hline
6262 
\multicolumn{4}{|c|}{opcode 0xa}&
6263 
\multicolumn{12}{c|}{X}\\
6264 
 
6265 
\hline
6266 
\multicolumn{4}{|c|}{4 bits}&
6267 
\multicolumn{12}{c|}{12 bits}\\
6268 
 
6269 
\hline
6270 
\end{tabular}\par}
6271 
\vspace{15mm}
6272 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6273 
\vspace{5mm}
6274 
\begin{quotation}
6275 
\texttt{\large h.bnf\ X}{\large \par}
6276 
\end{quotation}
6277 
\vspace{10mm}
6278 
\textbf{\LARGE Description:}{\LARGE \par}
6279 
\vspace{5mm}
6280 
\begin{quotation}
6281 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is cleared, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
6282 
\end{quotation}
6283 
\vspace{10mm}
6284 
\textbf{\LARGE Operation:}{\LARGE \par}
6285 
\vspace{5mm}
6286 
\begin{quotation}
6287 
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared
6288 
\end{quotation}
6289 
\vspace{10mm}
6290 
\textbf{\LARGE Notes:}{\LARGE \par}
6291 
\vspace{5mm}
6292 
\begin{quotation}
6293 
 
6294 
\end{quotation}
6295 
\vspace{10mm}
6296 
\vfill
6297 
Class 2:
6298 
{\centering \begin{tabular}{|c|c|c|}
6299 
\hline
6300 
Architecture Level&
6301 
Execution Mode&
6302 
Implementation\\
6303 
\hline
6304 
Core CPU&User and Supervisor&Recommended\\
6305 
\hline
6306 
\end{tabular}\par}
6307 
 
6308 
 
6309 
 
6310 
\newpage
6311 
\vspace{10mm}
6312 
\lyxline{\small}\vspace{-1\parskip}
6313 
\vspace{10mm}
6314 
{\raggedright \begin{tabular}{ccc}
6315 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6316 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6317 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6318 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6319 
\textbf{\huge h.bf}&
6320 
\multicolumn{1}{c}{\textbf{\huge Branch if Flag}}&
6321 
\textbf{\huge h.bf}\\
6322 
\end{tabular}\par}
6323 
\bigskip{}
6324 
 
6325 
\vspace{10mm}
6326 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
6327 
\hline
6328 
15&
6329 
&
6330 
&
6331 
12&
6332 
11&
6333 
&
6334 
&
6335 
&
6336 
&
6337 
&
6338 
&
6339 
&
6340 
&
6341 
&
6342 
&
6343 
0\\
6344 
\hline
6345 
\multicolumn{4}{|c|}{opcode 0xb}&
6346 
\multicolumn{12}{c|}{X}\\
6347 
 
6348 
\hline
6349 
\multicolumn{4}{|c|}{4 bits}&
6350 
\multicolumn{12}{c|}{12 bits}\\
6351 
 
6352 
\hline
6353 
\end{tabular}\par}
6354 
\vspace{15mm}
6355 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6356 
\vspace{5mm}
6357 
\begin{quotation}
6358 
\texttt{\large h.bf\ X}{\large \par}
6359 
\end{quotation}
6360 
\vspace{10mm}
6361 
\textbf{\LARGE Description:}{\LARGE \par}
6362 
\vspace{5mm}
6363 
\begin{quotation}
6364 
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is set, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
6365 
\end{quotation}
6366 
\vspace{10mm}
6367 
\textbf{\LARGE Operation:}{\LARGE \par}
6368 
\vspace{5mm}
6369 
\begin{quotation}
6370 
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set
6371 
\end{quotation}
6372 
\vspace{10mm}
6373 
\textbf{\LARGE Notes:}{\LARGE \par}
6374 
\vspace{5mm}
6375 
\begin{quotation}
6376 
 
6377 
\end{quotation}
6378 
\vspace{10mm}
6379 
\vfill
6380 
Class 2:
6381 
{\centering \begin{tabular}{|c|c|c|}
6382 
\hline
6383 
Architecture Level&
6384 
Execution Mode&
6385 
Implementation\\
6386 
\hline
6387 
Core CPU&User and Supervisor&Recommended\\
6388 
\hline
6389 
\end{tabular}\par}
6390 
 
6391 
 
6392 
 
6393 
\newpage
6394 
\vspace{10mm}
6395 
\lyxline{\small}\vspace{-1\parskip}
6396 
\vspace{10mm}
6397 
{\raggedright \begin{tabular}{ccc}
6398 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6399 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6400 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6401 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6402 
\textbf{\huge h.movi32}&
6403 
\multicolumn{1}{c}{\textbf{\huge Move 32 bit Immediate}}&
6404 
\textbf{\huge h.movi32}\\
6405 
\end{tabular}\par}
6406 
\bigskip{}
6407 
 
6408 
\vspace{10mm}
6409 
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
6410 
\hline
6411 
15&
6412 
&
6413 
&
6414 
12&
6415 
11&
6416 
&
6417 
&
6418 
8&
6419 
7&
6420 
&
6421 
&
6422 
4&
6423 
3&
6424 
&
6425 
&
6426 
0\\
6427 
\hline
6428 
\multicolumn{4}{|c|}{opcode 0xc}&
6429 
\multicolumn{4}{c|}{M}&
6430 
\multicolumn{4}{c|}{A}&
6431 
\multicolumn{4}{c|}{M}\\
6432 
 
6433 
\hline
6434 
\multicolumn{4}{|c|}{4 bits}&
6435 
\multicolumn{4}{c|}{4 bits}&
6436 
\multicolumn{4}{c|}{4 bits}&
6437 
\multicolumn{4}{c|}{4 bits}\\
6438 
 
6439 
\hline
6440 
\end{tabular}\par}
6441 
\vspace{15mm}
6442 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6443 
\vspace{5mm}
6444 
\begin{quotation}
6445 
\texttt{\large h.movi32\ rA,M}{\large \par}
6446 
\end{quotation}
6447 
\vspace{10mm}
6448 
\textbf{\LARGE Description:}{\LARGE \par}
6449 
\vspace{5mm}
6450 
\begin{quotation}
6451 
\texttt{\large For simulator. Obsolete}{\large \par}
6452 
\end{quotation}
6453 
\vspace{10mm}
6454 
\textbf{\LARGE Operation:}{\LARGE \par}
6455 
\vspace{5mm}
6456 
\begin{quotation}
6457 
N/A
6458 
\end{quotation}
6459 
\vspace{10mm}
6460 
\textbf{\LARGE Notes:}{\LARGE \par}
6461 
\vspace{5mm}
6462 
\begin{quotation}
6463 
 
6464 
\end{quotation}
6465 
\vspace{10mm}
6466 
\vfill
6467 
Class 0:
6468 
{\centering \begin{tabular}{|c|c|c|}
6469 
\hline
6470 
Architecture Level&
6471 
Execution Mode&
6472 
Implementation\\
6473 
\hline
6474 
&&\\
6475 
\hline
6476 
\end{tabular}\par}
6477 
 
6478 
 
6479 
 
6480 
\newpage
6481 
\vspace{10mm}
6482 
\lyxline{\small}\vspace{-1\parskip}
6483 
\vspace{10mm}
6484 
{\raggedright \begin{tabular}{ccc}
6485 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6486 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6487 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6488 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6489 
\textbf{\huge simprintf}&
6490 
\multicolumn{1}{c}{\textbf{\huge Simulate printf}}&
6491 
\textbf{\huge simprintf}\\
6492 
\end{tabular}\par}
6493 
\bigskip{}
6494 
 
6495 
\vspace{10mm}
6496 
{\centering \begin{tabular}{|cccccccccccccccc|}
6497 
\hline
6498 
31&
6499 
&
6500 
&
6501 
&
6502 
&
6503 
&
6504 
&
6505 
&
6506 
&
6507 
&
6508 
&
6509 
&
6510 
&
6511 
&
6512 
&
6513 
&
6514 
&
6515 
&
6516 
&
6517 
&
6518 
&
6519 
&
6520 
&
6521 
&
6522 
&
6523 
&
6524 
&
6525 
&
6526 
&
6527 
&
6528 
&
6529 
0\\
6530 
\hline
6531 
\multicolumn{16}{|c|}{opcode 0xe001}\\
6532 
 
6533 
\hline
6534 
\multicolumn{16}{|c|}{16 bits}\\
6535 
 
6536 
\hline
6537 
\end{tabular}\par}
6538 
\vspace{15mm}
6539 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6540 
\vspace{5mm}
6541 
\begin{quotation}
6542 
\texttt{\large simprintf\ }{\large \par}
6543 
\end{quotation}
6544 
\vspace{10mm}
6545 
\textbf{\LARGE Description:}{\LARGE \par}
6546 
\vspace{5mm}
6547 
\begin{quotation}
6548 
\texttt{\large For simulator. Obsolete.}{\large \par}
6549 
\end{quotation}
6550 
\vspace{10mm}
6551 
\textbf{\LARGE Operation:}{\LARGE \par}
6552 
\vspace{5mm}
6553 
\begin{quotation}
6554 
N/A
6555 
\end{quotation}
6556 
\vspace{10mm}
6557 
\textbf{\LARGE Notes:}{\LARGE \par}
6558 
\vspace{5mm}
6559 
\begin{quotation}
6560 
 
6561 
\end{quotation}
6562 
\vspace{10mm}
6563 
\vfill
6564 
Class 0:
6565 
{\centering \begin{tabular}{|c|c|c|}
6566 
\hline
6567 
Architecture Level&
6568 
Execution Mode&
6569 
Implementation\\
6570 
\hline
6571 
&&\\
6572 
\hline
6573 
\end{tabular}\par}
6574 
 
6575 
 
6576 
 
6577 
\newpage
6578 
\vspace{10mm}
6579 
\lyxline{\small}\vspace{-1\parskip}
6580 
\vspace{10mm}
6581 
{\raggedright \begin{tabular}{ccc}
6582 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6583 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6584 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6585 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6586 
\textbf{\huge simrdtsc}&
6587 
\multicolumn{1}{c}{\textbf{\huge Simulate Read Timer}}&
6588 
\textbf{\huge simrdtsc}\\
6589 
\end{tabular}\par}
6590 
\bigskip{}
6591 
 
6592 
\vspace{10mm}
6593 
{\centering \begin{tabular}{|cccccccc|cccc|ccc|}
6594 
\hline
6595 
31&
6596 
&
6597 
&
6598 
&
6599 
&
6600 
&
6601 
&
6602 
24&
6603 
23&
6604 
&
6605 
&
6606 
20&
6607 
19&
6608 
&
6609 
&
6610 
&
6611 
&
6612 
&
6613 
&
6614 
&
6615 
&
6616 
&
6617 
&
6618 
&
6619 
&
6620 
&
6621 
&
6622 
&
6623 
&
6624 
&
6625 
&
6626 
0\\
6627 
\hline
6628 
\multicolumn{8}{|c|}{opcode 0xe0}&
6629 
\multicolumn{4}{c|}{A}&
6630 
\multicolumn{3}{c|}{opcode 0x0}\\
6631 
 
6632 
\hline
6633 
\multicolumn{8}{|c|}{8 bits}&
6634 
\multicolumn{4}{c|}{4 bits}&
6635 
\multicolumn{3}{c|}{3 bits}\\
6636 
 
6637 
\hline
6638 
\end{tabular}\par}
6639 
\vspace{15mm}
6640 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6641 
\vspace{5mm}
6642 
\begin{quotation}
6643 
\texttt{\large simrdtsc\ rA}{\large \par}
6644 
\end{quotation}
6645 
\vspace{10mm}
6646 
\textbf{\LARGE Description:}{\LARGE \par}
6647 
\vspace{5mm}
6648 
\begin{quotation}
6649 
\texttt{\large For simulator. Obsolete.}{\large \par}
6650 
\end{quotation}
6651 
\vspace{10mm}
6652 
\textbf{\LARGE Operation:}{\LARGE \par}
6653 
\vspace{5mm}
6654 
\begin{quotation}
6655 
N/A
6656 
\end{quotation}
6657 
\vspace{10mm}
6658 
\textbf{\LARGE Notes:}{\LARGE \par}
6659 
\vspace{5mm}
6660 
\begin{quotation}
6661 
 
6662 
\end{quotation}
6663 
\vspace{10mm}
6664 
\vfill
6665 
Class 0:
6666 
{\centering \begin{tabular}{|c|c|c|}
6667 
\hline
6668 
Architecture Level&
6669 
Execution Mode&
6670 
Implementation\\
6671 
\hline
6672 
&&\\
6673 
\hline
6674 
\end{tabular}\par}
6675 
 
6676 
 
6677 
 
6678 
\newpage
6679 
\vspace{10mm}
6680 
\lyxline{\small}\vspace{-1\parskip}
6681 
\vspace{10mm}
6682 
{\raggedright \begin{tabular}{ccc}
6683 
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
6684 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
6685 
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
6686 
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
6687 
\textbf{\huge h.sched}&
6688 
\multicolumn{1}{c}{\textbf{\huge Schedule}}&
6689 
\textbf{\huge h.sched}\\
6690 
\end{tabular}\par}
6691 
\bigskip{}
6692 
 
6693 
\vspace{10mm}
6694 
{\centering \begin{tabular}{|cccc|cccccccccccc|}
6695 
\hline
6696 
15&
6697 
&
6698 
&
6699 
12&
6700 
11&
6701 
&
6702 
&
6703 
&
6704 
&
6705 
&
6706 
&
6707 
&
6708 
&
6709 
&
6710 
&
6711 
0\\
6712 
\hline
6713 
\multicolumn{4}{|c|}{opcode 0xf}&
6714 
\multicolumn{12}{c|}{Z}\\
6715 
 
6716 
\hline
6717 
\multicolumn{4}{|c|}{4 bits}&
6718 
\multicolumn{12}{c|}{12 bits}\\
6719 
 
6720 
\hline
6721 
\end{tabular}\par}
6722 
\vspace{15mm}
6723 
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
6724 
\vspace{5mm}
6725 
\begin{quotation}
6726 
\texttt{\large h.sched\ Z}{\large \par}
6727 
\end{quotation}
6728 
\vspace{10mm}
6729 
\textbf{\LARGE Description:}{\LARGE \par}
6730 
\vspace{5mm}
6731 
\begin{quotation}
6732 
\texttt{\large Immediate carries static scheduling information about instruction scheduling. This information is generated by an optimizing compiler.}{\large \par}
6733 
\end{quotation}
6734 
\vspace{10mm}
6735 
\textbf{\LARGE Operation:}{\LARGE \par}
6736 
\vspace{5mm}
6737 
\begin{quotation}
6738 
 
6739 
\end{quotation}
6740 
\vspace{10mm}
6741 
\textbf{\LARGE Notes:}{\LARGE \par}
6742 
\vspace{5mm}
6743 
\begin{quotation}
6744 
 
6745 
\end{quotation}
6746 
\vspace{10mm}
6747 
\vfill
6748 
Class 3:
6749 
{\centering \begin{tabular}{|c|c|c|}
6750 
\hline
6751 
Architecture Level&
6752 
Execution Mode&
6753 
Implementation\\
6754 
\hline
6755 
Core CPU&User and Supervisor&Optional\\
6756 
\hline
6757 
\end{tabular}\par}
6758 
 
6759 
 
6760 
\end{document}

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