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//

// Black boxes for 4kB caches

//

// This are black boxes to synthesize caches memories using

// distributed memories. 

// To reduce area and improve timing it is strongly recommend to 

// use block RAM generated using Coregen

//

module RAMB4_S16_S16(

         CLKA,

         RSTA,

         ADDRA,

         DIA,

         ENA,

         WEA,

         DOA,

         CLKB,

         RSTB,

         ADDRB,

         DIB,

         ENB,

         WEB,

         DOB

         );  //synthesis syn_black_box

input CLKA;

input RSTA;

input [7:0] ADDRA;

input [15:0] DIA;

input ENA;

input WEA;

output [15:0] DOA;

input CLKB;

input RSTB;

input [7:0] ADDRB;

input [15:0] DIB;

input ENB;

input WEB;

output [15:0] DOB;

endmodule