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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,
        icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
 
        // Internal i/f
        branch_op, except_type,
        branch_addrofs, lr_restor, flag, taken, except_start,
        binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cyc_o;
output                          icpu_stb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_ack_i;
input                           icpu_rty_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input   [31:2]                  branch_addrofs;
input   [31:0]                   lr_restor;
input                           flag;
output                          taken;
input                           except_start;
input   [31:2]                  binsn_addr;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           genpc_refetch;
 
//
// Internal wires and regs
//
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg                             taken;  /* Set to in case of jump or taken branch */
reg                             dslot;  /* set when fetching delay slot insn */
reg                             btarget; /* set when fetching branch target insns */
 
//
// Address of insn to be fecthed
//
assign icpu_adr_o = icpu_rty_i | genpc_refetch ? icpu_adr_i : pc;
 
//
// Control access to IC subsystem
//
assign icpu_cyc_o = 1'b1;
assign icpu_stb_o = 1'b1;
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 'd1, 2'b0};
                        taken = 1'b0;
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
                        pc = lr_restor;
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {binsn_addr + branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 'd1, 2'b0};
                                taken = 1'b0;
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                                pc = {pcreg + 'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
                                taken = 1'b0;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
                        pc = epcr;
                        taken = 1'b1;
                end
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
                        pc = { 20'h0_0000, except_type, 8'h00};
                        taken = 1'b1;
                end
                default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
                        pc = spr_dat_i;
                        taken = 1'b0;
                end
        endcase
end
 
//
// PC register
//
always @(posedge clk or posedge rst)
        if (rst)
                pcreg <= #1 30'd63;
        else if (spr_pc_we)
                pcreg <= #1 spr_dat_i[31:2];
        else if (!icpu_rty_i & !genpc_refetch)
                pcreg <= #1 pc[31:2];
 
//
// dslot
//
always @(posedge clk or posedge rst)
        if (rst)
                dslot <= #1 1'b0;
        else if (spr_pc_we)
                dslot <= #1 1'b0;
        else if (!icpu_rty_i)
                dslot <= #1 |branch_op;
 
//
// btarget
//
always @(posedge clk or posedge rst)
        if (rst)
                btarget <= #1 1'b0;
        else if (spr_pc_we)
                btarget <= #1 1'b0;
        else if (!icpu_rty_i)
                btarget <= #1 dslot;
 
endmodule

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[/] [or1k/] [tags/] [asyst_2/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Blame information for rev 504

Line No.	Rev	Author	Line
1	504	lampret
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's generate PC ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// PC, interface to IC. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.10 2001/11/20 18:46:15 simons`
49			`// Break point bug fixed`
50			`//`
51			`// Revision 1.9 2001/11/18 09:58:28 lampret`
52			`// Fixed some l.trap typos.`
53			`//`
54			`// Revision 1.8 2001/11/18 08:36:28 lampret`
55			`// For GDB changed single stepping and disabled trap exception.`
56			`//`
57			`// Revision 1.7 2001/10/21 17:57:16 lampret`
58			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
59			`//`
60			`// Revision 1.6 2001/10/14 13:12:09 lampret`
61			`// MP3 version.`
62			`//`
63			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
64			`// no message`
65			`//`
66			`// Revision 1.1 2001/08/09 13:39:33 lampret`
67			`// Major clean-up.`
68			`//`
69			`//`
70
71			`// synopsys translate_off`
72			`include "timescale.v"
73			`// synopsys translate_on`
74			`include "or1200_defines.v"
75
76			`module or1200_genpc(`
77			`// Clock and reset`
78			`clk, rst,`
79
80			`// External i/f to IC`
81			`icpu_adr_o, icpu_cyc_o, icpu_stb_o, icpu_sel_o, icpu_tag_o,`
82			`icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,`
83
84			`// Internal i/f`
85			`branch_op, except_type,`
86			`branch_addrofs, lr_restor, flag, taken, except_start,`
87			`binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch`
88			`);`
89
90			`//`
91			`// I/O`
92			`//`
93
94			`//`
95			`// Clock and reset`
96			`//`
97			`input clk;`
98			`input rst;`
99
100			`//`
101			`// External i/f to IC`
102			`//`
103			`output [31:0] icpu_adr_o;`
104			`output icpu_cyc_o;`
105			`output icpu_stb_o;`
106			`output [3:0] icpu_sel_o;`
107			`output [3:0] icpu_tag_o;`
108			`input icpu_ack_i;`
109			`input icpu_rty_i;`
110			`input icpu_err_i;`
111			`input [31:0] icpu_adr_i;`
112
113			`//`
114			`// Internal i/f`
115			`//`
116			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
117			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
118			`input [31:2] branch_addrofs;`
119			`input [31:0] lr_restor;`
120			`input flag;`
121			`output taken;`
122			`input except_start;`
123			`input [31:2] binsn_addr;`
124			`input [31:0] epcr;`
125			`input [31:0] spr_dat_i;`
126			`input spr_pc_we;`
127			`input genpc_refetch;`
128
129			`//`
130			`// Internal wires and regs`
131			`//`
132			`reg [31:2] pcreg;`
133			`reg [31:0] pc;`
134			`reg taken; /* Set to in case of jump or taken branch */`
135			`reg dslot; /* set when fetching delay slot insn */`
136			`reg btarget; /* set when fetching branch target insns */`
137
138			`//`
139			`// Address of insn to be fecthed`
140			`//`
141			`assign icpu_adr_o = icpu_rty_i \| genpc_refetch ? icpu_adr_i : pc;`
142
143			`//`
144			`// Control access to IC subsystem`
145			`//`
146			`assign icpu_cyc_o = 1'b1;`
147			`assign icpu_stb_o = 1'b1;`
148			`assign icpu_sel_o = 4'b1111;`
149			assign icpu_tag_o = `OR1200_ITAG_NI;
150
151			`//`
152			`// Async calculation of new PC value. This value is used for addressing the IC.`
153			`//`
154			`always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type`
155			`or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i) begin`
156			`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
157			{2'b00, `OR1200_BRANCHOP_NOP}: begin
158			`pc = {pcreg + 'd1, 2'b0};`
159			`taken = 1'b0;`
160			`end`
161			{2'b00, `OR1200_BRANCHOP_J}: begin
162			`ifdef OR1200_VERBOSE
163			`// synopsys translate_off`
164			`$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);`
165			`// synopsys translate_on`
166			`endif
167			`pc = {branch_addrofs, 2'b0};`
168			`taken = 1'b1;`
169			`end`
170			{2'b00, `OR1200_BRANCHOP_JR}: begin
171			`ifdef OR1200_VERBOSE
172			`// synopsys translate_off`
173			`$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);`
174			`// synopsys translate_on`
175			`endif
176			`pc = lr_restor;`
177			`taken = 1'b1;`
178			`end`
179			{2'b00, `OR1200_BRANCHOP_BAL}: begin
180			`ifdef OR1200_VERBOSE
181			`// synopsys translate_off`
182			`$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
183			`// synopsys translate_on`
184			`endif
185			`pc = {binsn_addr + branch_addrofs, 2'b0};`
186			`taken = 1'b1;`
187			`end`
188			{2'b00, `OR1200_BRANCHOP_BF}:
189			`if (flag) begin`
190			`ifdef OR1200_VERBOSE
191			`// synopsys translate_off`
192			`$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
193			`// synopsys translate_on`
194			`endif
195			`pc = {binsn_addr + branch_addrofs, 2'b0};`
196			`taken = 1'b1;`
197			`end`
198			`else begin`
199			`ifdef OR1200_VERBOSE
200			`// synopsys translate_off`
201			`$display("%t: BRANCHOP_BF: not taken", $time);`
202			`// synopsys translate_on`
203			`endif
204			`pc = {pcreg + 'd1, 2'b0};`
205			`taken = 1'b0;`
206			`end`
207			{2'b00, `OR1200_BRANCHOP_BNF}:
208			`if (flag) begin`
209			`pc = {pcreg + 'd1, 2'b0};`
210			`ifdef OR1200_VERBOSE
211			`// synopsys translate_off`
212			`$display("%t: BRANCHOP_BNF: not taken", $time);`
213			`// synopsys translate_on`
214			`endif
215			`taken = 1'b0;`
216			`end`
217			`else begin`
218			`ifdef OR1200_VERBOSE
219			`// synopsys translate_off`
220			`$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
221			`// synopsys translate_on`
222			`endif
223			`pc = {binsn_addr + branch_addrofs, 2'b0};`
224			`taken = 1'b1;`
225			`end`
226			{2'b00, `OR1200_BRANCHOP_RFE}: begin
227			`ifdef OR1200_VERBOSE
228			`// synopsys translate_off`
229			`$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);`
230			`// synopsys translate_on`
231			`endif
232			`pc = epcr;`
233			`taken = 1'b1;`
234			`end`
235			`{2'b01, 3'bxxx}: begin`
236			`ifdef OR1200_VERBOSE
237			`// synopsys translate_off`
238			`$display("Starting exception: %h.", except_type);`
239			`// synopsys translate_on`
240			`endif
241			`pc = { 20'h0_0000, except_type, 8'h00};`
242			`taken = 1'b1;`
243			`end`
244			`default: begin`
245			`ifdef OR1200_VERBOSE
246			`// synopsys translate_off`
247			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
248			`// synopsys translate_on`
249			`endif
250			`pc = spr_dat_i;`
251			`taken = 1'b0;`
252			`end`
253			`endcase`
254			`end`
255
256			`//`
257			`// PC register`
258			`//`
259			`always @(posedge clk or posedge rst)`
260			`if (rst)`
261			`pcreg <= #1 30'd63;`
262			`else if (spr_pc_we)`
263			`pcreg <= #1 spr_dat_i[31:2];`
264			`else if (!icpu_rty_i & !genpc_refetch)`
265			`pcreg <= #1 pc[31:2];`
266
267			`//`
268			`// dslot`
269			`//`
270			`always @(posedge clk or posedge rst)`
271			`if (rst)`
272			`dslot <= #1 1'b0;`
273			`else if (spr_pc_we)`
274			`dslot <= #1 1'b0;`
275			`else if (!icpu_rty_i)`
276			`dslot <= #1 \|branch_op;`
277
278			`//`
279			`// btarget`
280			`//`
281			`always @(posedge clk or posedge rst)`
282			`if (rst)`
283			`btarget <= #1 1'b0;`
284			`else if (spr_pc_we)`
285			`btarget <= #1 1'b0;`
286			`else if (!icpu_rty_i)`
287			`btarget <= #1 dslot;`
288
289			`endmodule`