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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        result, flagforw, flag_we
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg                             flagforw;
reg                             flag_we;
integer                         d1;
integer                         d2;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin
        casex (alu_op)          // synopsys parallel_case full_case
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                                flag_we = 1'b0;
                end
                `OR1200_ALUOP_ADD : begin
                                result = a + b;
                                flag_we = 1'b0;
                end
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                                flag_we = 1'b0;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                                flag_we = 1'b0;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                                flag_we = 1'b0;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b;
                                flag_we = 1'b0;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                        flag_we = 1'b0;
                                end
                                else begin
                                        result = b << 16;
                                        flag_we = 1'b0;
                                end
                end
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
// synopsys translate_on
`endif
                                flag_we = 1'b0;
                end
// synopsys translate_off
`ifdef OR1200_SIM_ALU_DIV
                `OR1200_ALUOP_DIV : begin
                                d1 = a;
                                d2 = b;
                                $display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
                                if (d2)
                                        result = d1 / d2;
                                else
                                        result = 32'h00000000;
                                flag_we = 1'b0;
                end
`endif
`ifdef OR1200_SIM_ALU_DIVU
                `OR1200_ALUOP_DIVU : begin
                                if (b)
                                        result = a / b;
                                else
                                        result = 32'h00000000;
                                flag_we = 1'b0;
                end
`endif
// synopsys translate_on
                `OR1200_ALUOP_COMP: begin
                                flag_we = 1'b1;
                                result = 32'd0;
                end
                default : begin // `OR1200_ALUOP_AND
                                result = a & b;
                                flag_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
                `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagforw = a_eq_b;
                `OR1200_COP_SFNE:
                        flagforw = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagforw = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagforw = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagforw = a_lt_b;
                `OR1200_COP_SFLE:
                        flagforw = a_eq_b | a_lt_b;
// synopsys translate_off
                default:
                        flagforw = 1'bx;
// synopsys translate_on
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagforw = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagforw = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagforw = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagforw = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagforw = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagforw = (comp_a <= comp_b);
// synopsys translate_off
                default:
                        flagforw = 1'bx;
// synopsys translate_on
        endcase
end
`endif
 
endmodule

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[/] [or1k/] [tags/] [asyst_3/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Blame information for rev 504

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.10 2001/11/12 01:45:40 lampret`
48			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
49			`//`
50			`// Revision 1.9 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.8 2001/10/19 23:28:45 lampret`
54			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
55			`//`
56			`// Revision 1.7 2001/10/14 13:12:09 lampret`
57			`// MP3 version.`
58			`//`
59			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
60			`// no message`
61			`//`
62			`// Revision 1.2 2001/08/09 13:39:33 lampret`
63			`// Major clean-up.`
64			`//`
65			`// Revision 1.1 2001/07/20 00:46:03 lampret`
66			`// Development version of RTL. Libraries are missing.`
67			`//`
68			`//`
69
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "or1200_defines.v"
74
75			`module or1200_alu(`
76			`a, b, mult_mac_result, macrc_op,`
77			`alu_op, shrot_op, comp_op,`
78			`result, flagforw, flag_we`
79			`);`
80
81			parameter width = `OR1200_OPERAND_WIDTH;
82
83			`//`
84			`// I/O`
85			`//`
86			`input [width-1:0] a;`
87			`input [width-1:0] b;`
88			`input [width-1:0] mult_mac_result;`
89			`input macrc_op;`
90			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
91			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
92			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
93			`output [width-1:0] result;`
94			`output flagforw;`
95			`output flag_we;`
96
97			`//`
98			`// Internal wires and regs`
99			`//`
100			`reg [width-1:0] result;`
101			`reg [width-1:0] shifted_rotated;`
102			`reg flagforw;`
103			`reg flag_we;`
104			`integer d1;`
105			`integer d2;`
106			`wire [width-1:0] comp_a;`
107			`wire [width-1:0] comp_b;`
108			`ifdef OR1200_IMPL_ALU_COMP1
109			`wire a_eq_b;`
110			`wire a_lt_b;`
111			`endif
112
113			`//`
114			`// Combinatorial logic`
115			`//`
116			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
117			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
118			`ifdef OR1200_IMPL_ALU_COMP1
119			`assign a_eq_b = (comp_a == comp_b);`
120			`assign a_lt_b = (comp_a < comp_b);`
121			`endif
122
123			`//`
124			`// Simulation check for bad ALU behavior`
125			`//`
126			`ifdef OR1200_WARNINGS
127			`// synopsys translate_off`
128			`always @(result) begin`
129			`if (result === 32'bx)`
130			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
131			`end`
132			`// synopsys translate_on`
133			`endif
134
135			`//`
136			`// Central part of the ALU`
137			`//`
138			`always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin`
139			`casex (alu_op) // synopsys parallel_case full_case`
140			`OR1200_ALUOP_SHROT : begin
141			`result = shifted_rotated;`
142			`flag_we = 1'b0;`
143			`end`
144			`OR1200_ALUOP_ADD : begin
145			`result = a + b;`
146			`flag_we = 1'b0;`
147			`end`
148			`OR1200_ALUOP_SUB : begin
149			`result = a - b;`
150			`flag_we = 1'b0;`
151			`end`
152			`OR1200_ALUOP_XOR : begin
153			`result = a ^ b;`
154			`flag_we = 1'b0;`
155			`end`
156			`OR1200_ALUOP_OR : begin
157			`result = a \| b;`
158			`flag_we = 1'b0;`
159			`end`
160			`OR1200_ALUOP_IMM : begin
161			`result = b;`
162			`flag_we = 1'b0;`
163			`end`
164			`OR1200_ALUOP_MOVHI : begin
165			`if (macrc_op) begin`
166			`result = mult_mac_result;`
167			`flag_we = 1'b0;`
168			`end`
169			`else begin`
170			`result = b << 16;`
171			`flag_we = 1'b0;`
172			`end`
173			`end`
174			`OR1200_ALUOP_MUL : begin
175			`result = mult_mac_result;`
176			`ifdef OR1200_VERBOSE
177			`// synopsys translate_off`
178			`$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);`
179			`// synopsys translate_on`
180			`endif
181			`flag_we = 1'b0;`
182			`end`
183			`// synopsys translate_off`
184			`ifdef OR1200_SIM_ALU_DIV
185			`OR1200_ALUOP_DIV : begin
186			`d1 = a;`
187			`d2 = b;`
188			`$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);`
189			`if (d2)`
190			`result = d1 / d2;`
191			`else`
192			`result = 32'h00000000;`
193			`flag_we = 1'b0;`
194			`end`
195			`endif
196			`ifdef OR1200_SIM_ALU_DIVU
197			`OR1200_ALUOP_DIVU : begin
198			`if (b)`
199			`result = a / b;`
200			`else`
201			`result = 32'h00000000;`
202			`flag_we = 1'b0;`
203			`end`
204			`endif
205			`// synopsys translate_on`
206			`OR1200_ALUOP_COMP: begin
207			`flag_we = 1'b1;`
208			`result = 32'd0;`
209			`end`
210			default : begin // `OR1200_ALUOP_AND
211			`result = a & b;`
212			`flag_we = 1'b0;`
213			`end`
214			`endcase`
215			`end`
216
217			`//`
218			`// Shifts and rotation`
219			`//`
220			`always @(shrot_op or a or b) begin`
221			`case (shrot_op) // synopsys parallel_case`
222			`OR1200_SHROTOP_SLL :
223			`shifted_rotated = (a << b[4:0]);`
224			`OR1200_SHROTOP_SRL :
225			`shifted_rotated = (a >> b[4:0]);`
226			`ifdef OR1200_IMPL_ALU_ROTATE
227			`OR1200_SHROTOP_ROR :
228			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
229			`endif
230			`default:`
231			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
232			`endcase`
233			`end`
234
235			`//`
236			`// First type of compare implementation`
237			`//`
238			`ifdef OR1200_IMPL_ALU_COMP1
239			`always @(comp_op or a_eq_b or a_lt_b) begin`
240			`case(comp_op[2:0]) // synopsys parallel_case`
241			`OR1200_COP_SFEQ:
242			`flagforw = a_eq_b;`
243			`OR1200_COP_SFNE:
244			`flagforw = ~a_eq_b;`
245			`OR1200_COP_SFGT:
246			`flagforw = ~(a_eq_b \| a_lt_b);`
247			`OR1200_COP_SFGE:
248			`flagforw = ~a_lt_b;`
249			`OR1200_COP_SFLT:
250			`flagforw = a_lt_b;`
251			`OR1200_COP_SFLE:
252			`flagforw = a_eq_b \| a_lt_b;`
253			`// synopsys translate_off`
254			`default:`
255			`flagforw = 1'bx;`
256			`// synopsys translate_on`
257			`endcase`
258			`end`
259			`endif
260
261			`//`
262			`// Second type of compare implementation`
263			`//`
264			`ifdef OR1200_IMPL_ALU_COMP2
265			`always @(comp_op or comp_a or comp_b) begin`
266			`case(comp_op[2:0]) // synopsys parallel_case`
267			`OR1200_COP_SFEQ:
268			`flagforw = (comp_a == comp_b);`
269			`OR1200_COP_SFNE:
270			`flagforw = (comp_a != comp_b);`
271			`OR1200_COP_SFGT:
272			`flagforw = (comp_a > comp_b);`
273			`OR1200_COP_SFGE:
274			`flagforw = (comp_a >= comp_b);`
275			`OR1200_COP_SFLT:
276			`flagforw = (comp_a < comp_b);`
277			`OR1200_COP_SFLE:
278			`flagforw = (comp_a <= comp_b);`
279			`// synopsys translate_off`
280			`default:`
281			`flagforw = 1'bx;`
282			`// synopsys translate_on`
283			`endcase`
284			`end`
285			`endif
286
287			`endmodule`