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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Debug Unit                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Basic OR1200 debug unit.                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12  2001/11/30 18:58:00  simons
// Trap insn couses break after exits ex_insn.
//
// Revision 1.11  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10  2001/11/20 21:25:44  lampret
// Fixed dbg_is_o assignment width.
//
// Revision 1.9  2001/11/20 18:46:14  simons
// Break point bug fixed
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 18:09:53  lampret
// Fixed sensitivity list.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Debug unit
//
 
module or1200_du(
        // RISC Internal Interface
        clk, rst,
        dcpu_cyc_i, dcpu_stb_i, dcpu_we_i,
        icpu_cyc_i, icpu_stb_i, ex_freeze, branch_op, ex_insn, du_dsr,
        du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
        // External Debug Interface
        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// RISC Internal Interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input                           dcpu_cyc_i;     // LSU status
input                           dcpu_stb_i;     // LSU status
input                           dcpu_we_i;      // LSU status
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cyc_i;     // IFETCH unit status
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_stb_i;     // IFETCH unit status
input                           ex_freeze;      // EX stage freeze
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
input   [dw-1:0]         ex_insn;        // EX insn
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
output                          du_stall;       // Debug Unit Stall
output  [aw-1:0]         du_addr;        // Debug Unit Address
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
output                          du_read;        // Debug Unit Read Enable
output                          du_write;       // Debug Unit Write Enable
input   [12:0]                   du_except;      // Exception masked by DSR
input                           spr_cs;         // SPR Chip Select
input                           spr_write;      // SPR Read/Write
input   [aw-1:0]         spr_addr;       // SPR Address
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
 
//
// External Debug Interface
//
input                           dbg_stall_i;    // External Stall Input
input   [dw-1:0]         dbg_dat_i;      // External Data Input
input   [aw-1:0]         dbg_adr_i;      // External Address Input
input   [2:0]                    dbg_op_i;       // External Operation Select Input
input                           dbg_ewt_i;      // External Watchpoint Trigger Input
output  [3:0]                    dbg_lss_o;      // External Load/Store Unit Status
output  [1:0]                    dbg_is_o;       // External Insn Fetch Status
output  [10:0]                   dbg_wp_o;       // Watchpoints Outputs
output                          dbg_bp_o;       // Breakpoint Output
output  [dw-1:0]         dbg_dat_o;      // External Data Output
 
 
//
// Some connections go directly from the CPU through DU to Debug I/F
//
assign dbg_lss_o = dcpu_cyc_i & dcpu_stb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_is_o = {1'b0, icpu_cyc_i & icpu_stb_i};
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
 
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
 
`ifdef OR1200_DU_IMPLEMENTED
 
//
// Debug Mode Register 1 (only ST and BT implemented)
//
`ifdef OR1200_DU_DMR1
reg     [23:22]                 dmr1;           // DMR1 implemented (ST & BT)
`else
wire    [23:22]                 dmr1;           // DMR1 not implemented
`endif
 
//
// Debug Mode Register 2 (not implemented)
//
`ifdef OR1200_DU_DMR2
wire    [31:0]                   dmr2;           // DMR not implemented
`endif
 
//
// Debug Stop Register
//
`ifdef OR1200_DU_DSR
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
`else
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
`endif
 
//
// Debug Reason Register
//
`ifdef OR1200_DU_DRR
reg     [13:0]                   drr;            // DRR implemented
`else
wire    [13:0]                   drr;            // DRR not implemented
`endif
 
//
// Internal wires
//
wire                            dmr1_sel;       // DMR1 select
wire                            dsr_sel;        // DSR select
wire                            drr_sel;        // DRR select
reg                             dbg_bp_r;
`ifdef OR1200_DU_READREGS
reg     [31:0]                   spr_dat_o;
`endif
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
 
//
// DU registers address decoder
//
`ifdef OR1200_DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
`endif
`ifdef OR1200_DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
`endif
`ifdef OR1200_DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
`endif
 
//
// Decode started exception
//
always @(du_except) begin
        except_stop = 14'b0000_0000_0000;
        casex (du_except)
                13'b1_xxxx_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_HPINTE] = 1'b1;
                end
                13'b0_1xxx_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
                end
                13'b0_01xx_xxxx_xxxx:
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
                13'b0_001x_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                end
                13'b0_0001_xxxx_xxxx:
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
                13'b0_0000_1xxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
                end
                13'b0_0000_01xx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
                end
                13'b0_0000_001x_xxxx:
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
                13'b0_0000_0001_xxxx:
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                13'b0_0000_0000_1xxx:
                        except_stop[`OR1200_DU_DRR_LPINTE] = 1'b1;
                13'b0_0000_0000_01xx: begin
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
                end
                13'b0_0000_0000_001x: begin
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
                end
                13'b0_0000_0000_0001:
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
                default:
                        except_stop = 14'b0000_0000_0000;
        endcase
end
 
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
 
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
        if (rst)
// SIMON
//              dbg_bp_r <= #1 1'b1;
                dbg_bp_r <= #1 1'b0;
        else if (!ex_freeze)
                dbg_bp_r <= #1 |except_stop
`ifdef OR1200_DU_DMR1_ST
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
// DAMJAN                       | ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
// DAMJAN                       | ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif
                        ;
        else
                dbg_bp_r <= #1 |except_stop;
 
//
// Write to DMR1
//
`ifdef OR1200_DU_DMR1
always @(posedge clk or posedge rst)
        if (rst)
                dmr1 <= 2'b00;
        else if (dmr1_sel && spr_write)
                dmr1 <= #1 spr_dat_i[23:22];
`else
assign dmr1 = 2'b00;
`endif
 
//
// DMR2 bits tied to zero
//
`ifdef OR1200_DU_DMR2
assign dmr2 = 32'h0000_0000;
`endif
 
//
// Write to DSR
//
`ifdef OR1200_DU_DSR
always @(posedge clk or posedge rst)
        if (rst)
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
        else if (dsr_sel && spr_write)
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif
 
//
// Write to DRR
//
`ifdef OR1200_DU_DRR
always @(posedge clk or posedge rst)
        if (rst)
                drr <= 14'b0;
        else if (drr_sel && spr_write)
                drr <= #1 spr_dat_i[13:0];
        else
                drr <= #1 drr | except_stop;
`else
assign drr = 14'b0;
`endif
 
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2)
        case (spr_addr[`OR1200_SPR_OFS_BITS])
`ifdef OR1200_DU_DMR1
                `OR1200_DU_OFS_DMR1:
                        spr_dat_o = {8'b0, dmr1, 22'b0};
`endif
`ifdef OR1200_DU_DMR2
                `OR1200_DU_OFS_DMR2:
                        spr_dat_o = dmr2;
`endif
`ifdef OR1200_DU_DSR
                `OR1200_DU_OFS_DSR:
                        spr_dat_o = {18'b0, dsr};
`endif
`ifdef OR1200_DU_DRR
                `OR1200_DU_OFS_DRR:
                        spr_dat_o = {18'b0, drr};
`endif
                default:
                        spr_dat_o = 32'h0000_0000;
        endcase
`endif
 
//
// DSR alias
//
assign du_dsr = dsr;
 
`else
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
 
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef OR1200_DU_UNUSED_ZERO
`endif
`endif
 
`endif
 
endmodule

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[/] [or1k/] [tags/] [asyst_3/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Blame information for rev 562

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Debug Unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Basic OR1200 debug unit. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50	504	lampret	`// Revision 1.12 2001/11/30 18:58:00 simons`
51			`// Trap insn couses break after exits ex_insn.`
52			`//`
53			`// Revision 1.11 2001/11/23 08:38:51 lampret`
54			`// Changed DSR/DRR behavior and exception detection.`
55			`//`
56			`// Revision 1.10 2001/11/20 21:25:44 lampret`
57			`// Fixed dbg_is_o assignment width.`
58			`//`
59			`// Revision 1.9 2001/11/20 18:46:14 simons`
60			`// Break point bug fixed`
61			`//`
62			`// Revision 1.8 2001/11/18 08:36:28 lampret`
63			`// For GDB changed single stepping and disabled trap exception.`
64			`//`
65			`// Revision 1.7 2001/10/21 18:09:53 lampret`
66			`// Fixed sensitivity list.`
67			`//`
68			`// Revision 1.6 2001/10/14 13:12:09 lampret`
69			`// MP3 version.`
70			`//`
71			`//`
72
73			`// synopsys translate_off`
74			`include "timescale.v"
75			`// synopsys translate_on`
76			`include "or1200_defines.v"
77
78			`//`
79			`// Debug unit`
80			`//`
81
82			`module or1200_du(`
83			`// RISC Internal Interface`
84			`clk, rst,`
85			`dcpu_cyc_i, dcpu_stb_i, dcpu_we_i,`
86			`icpu_cyc_i, icpu_stb_i, ex_freeze, branch_op, ex_insn, du_dsr,`
87			`du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,`
88			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
89
90			`// External Debug Interface`
91			`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
92			`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o`
93			`);`
94
95			parameter dw = `OR1200_OPERAND_WIDTH;
96			parameter aw = `OR1200_OPERAND_WIDTH;
97
98			`//`
99			`// I/O`
100			`//`
101
102			`//`
103			`// RISC Internal Interface`
104			`//`
105			`input clk; // Clock`
106			`input rst; // Reset`
107			`input dcpu_cyc_i; // LSU status`
108			`input dcpu_stb_i; // LSU status`
109			`input dcpu_we_i; // LSU status`
110			input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cyc_i; // IFETCH unit status
111			input [`OR1200_FETCHOP_WIDTH-1:0] icpu_stb_i; // IFETCH unit status
112			`input ex_freeze; // EX stage freeze`
113			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
114			`input [dw-1:0] ex_insn; // EX insn`
115			output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
116			`output du_stall; // Debug Unit Stall`
117			`output [aw-1:0] du_addr; // Debug Unit Address`
118			`input [dw-1:0] du_dat_i; // Debug Unit Data In`
119			`output [dw-1:0] du_dat_o; // Debug Unit Data Out`
120			`output du_read; // Debug Unit Read Enable`
121			`output du_write; // Debug Unit Write Enable`
122			`input [12:0] du_except; // Exception masked by DSR`
123			`input spr_cs; // SPR Chip Select`
124			`input spr_write; // SPR Read/Write`
125			`input [aw-1:0] spr_addr; // SPR Address`
126			`input [dw-1:0] spr_dat_i; // SPR Data Input`
127			`output [dw-1:0] spr_dat_o; // SPR Data Output`
128
129			`//`
130			`// External Debug Interface`
131			`//`
132			`input dbg_stall_i; // External Stall Input`
133			`input [dw-1:0] dbg_dat_i; // External Data Input`
134			`input [aw-1:0] dbg_adr_i; // External Address Input`
135			`input [2:0] dbg_op_i; // External Operation Select Input`
136			`input dbg_ewt_i; // External Watchpoint Trigger Input`
137			`output [3:0] dbg_lss_o; // External Load/Store Unit Status`
138			`output [1:0] dbg_is_o; // External Insn Fetch Status`
139			`output [10:0] dbg_wp_o; // Watchpoints Outputs`
140			`output dbg_bp_o; // Breakpoint Output`
141			`output [dw-1:0] dbg_dat_o; // External Data Output`
142
143
144			`//`
145			`// Some connections go directly from the CPU through DU to Debug I/F`
146			`//`
147			`assign dbg_lss_o = dcpu_cyc_i & dcpu_stb_i ? {dcpu_we_i, 3'b000} : 4'b0000;`
148			`assign dbg_is_o = {1'b0, icpu_cyc_i & icpu_stb_i};`
149			`assign dbg_wp_o = 11'b000_0000_0000;`
150			`assign dbg_dat_o = du_dat_i;`
151
152			`//`
153			`// Some connections go directly from Debug I/F through DU to the CPU`
154			`//`
155			`assign du_stall = dbg_stall_i;`
156			`assign du_addr = dbg_adr_i;`
157			`assign du_dat_o = dbg_dat_i;`
158			assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
159			assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
160
161			`ifdef OR1200_DU_IMPLEMENTED
162
163			`//`
164			`// Debug Mode Register 1 (only ST and BT implemented)`
165			`//`
166			`ifdef OR1200_DU_DMR1
167			`reg [23:22] dmr1; // DMR1 implemented (ST & BT)`
168			`else
169			`wire [23:22] dmr1; // DMR1 not implemented`
170			`endif
171
172			`//`
173			`// Debug Mode Register 2 (not implemented)`
174			`//`
175			`ifdef OR1200_DU_DMR2
176			`wire [31:0] dmr2; // DMR not implemented`
177			`endif
178
179			`//`
180			`// Debug Stop Register`
181			`//`
182			`ifdef OR1200_DU_DSR
183			reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
184			`else
185			wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
186			`endif
187
188			`//`
189			`// Debug Reason Register`
190			`//`
191			`ifdef OR1200_DU_DRR
192			`reg [13:0] drr; // DRR implemented`
193			`else
194			`wire [13:0] drr; // DRR not implemented`
195			`endif
196
197			`//`
198			`// Internal wires`
199			`//`
200			`wire dmr1_sel; // DMR1 select`
201			`wire dsr_sel; // DSR select`
202			`wire drr_sel; // DRR select`
203			`reg dbg_bp_r;`
204			`ifdef OR1200_DU_READREGS
205			`reg [31:0] spr_dat_o;`
206			`endif
207			`reg [13:0] except_stop; // Exceptions that stop because of DSR`
208
209			`//`
210			`// DU registers address decoder`
211			`//`
212			`ifdef OR1200_DU_DMR1
213			assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
214			`endif
215			`ifdef OR1200_DU_DSR
216			assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
217			`endif
218			`ifdef OR1200_DU_DRR
219			assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
220			`endif
221
222			`//`
223			`// Decode started exception`
224			`//`
225			`always @(du_except) begin`
226			`except_stop = 14'b0000_0000_0000;`
227			`casex (du_except)`
228			`13'b1_xxxx_xxxx_xxxx: begin`
229			except_stop[`OR1200_DU_DRR_HPINTE] = 1'b1;
230			`end`
231			`13'b0_1xxx_xxxx_xxxx: begin`
232			except_stop[`OR1200_DU_DRR_IME] = 1'b1;
233			`end`
234			`13'b0_01xx_xxxx_xxxx:`
235			except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
236			`13'b0_001x_xxxx_xxxx: begin`
237			except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
238			`end`
239			`13'b0_0001_xxxx_xxxx:`
240			except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
241			`13'b0_0000_1xxx_xxxx: begin`
242			except_stop[`OR1200_DU_DRR_AE] = 1'b1;
243			`end`
244			`13'b0_0000_01xx_xxxx: begin`
245			except_stop[`OR1200_DU_DRR_DME] = 1'b1;
246			`end`
247			`13'b0_0000_001x_xxxx:`
248			except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
249			`13'b0_0000_0001_xxxx:`
250			except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
251			`13'b0_0000_0000_1xxx:`
252			except_stop[`OR1200_DU_DRR_LPINTE] = 1'b1;
253			`13'b0_0000_0000_01xx: begin`
254			except_stop[`OR1200_DU_DRR_RE] = 1'b1;
255			`end`
256			`13'b0_0000_0000_001x: begin`
257			except_stop[`OR1200_DU_DRR_TE] = 1'b1;
258			`end`
259			`13'b0_0000_0000_0001:`
260			except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
261			`default:`
262			`except_stop = 14'b0000_0000_0000;`
263			`endcase`
264			`end`
265
266			`//`
267			`// dbg_bp_o is registered`
268			`//`
269			`assign dbg_bp_o = dbg_bp_r;`
270
271			`//`
272			`// Breakpoint activation register`
273			`//`
274			`always @(posedge clk or posedge rst)`
275			`if (rst)`
276			`// SIMON`
277			`// dbg_bp_r <= #1 1'b1;`
278			`dbg_bp_r <= #1 1'b0;`
279			`else if (!ex_freeze)`
280			`dbg_bp_r <= #1 \|except_stop`
281			`ifdef OR1200_DU_DMR1_ST
282			\| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
283			// DAMJAN \| ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
284			`endif
285			`ifdef OR1200_DU_DMR1_BT
286			// DAMJAN \| ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
287			\| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
288			`endif
289			`;`
290			`else`
291	562	lampret	`dbg_bp_r <= #1 \|except_stop;`
292	504	lampret
293			`//`
294			`// Write to DMR1`
295			`//`
296			`ifdef OR1200_DU_DMR1
297			`always @(posedge clk or posedge rst)`
298			`if (rst)`
299			`dmr1 <= 2'b00;`
300			`else if (dmr1_sel && spr_write)`
301			`dmr1 <= #1 spr_dat_i[23:22];`
302			`else
303			`assign dmr1 = 2'b00;`
304			`endif
305
306			`//`
307			`// DMR2 bits tied to zero`
308			`//`
309			`ifdef OR1200_DU_DMR2
310			`assign dmr2 = 32'h0000_0000;`
311			`endif
312
313			`//`
314			`// Write to DSR`
315			`//`
316			`ifdef OR1200_DU_DSR
317			`always @(posedge clk or posedge rst)`
318			`if (rst)`
319			dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
320			`else if (dsr_sel && spr_write)`
321			dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
322			`else
323			assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
324			`endif
325
326			`//`
327			`// Write to DRR`
328			`//`
329			`ifdef OR1200_DU_DRR
330			`always @(posedge clk or posedge rst)`
331			`if (rst)`
332			`drr <= 14'b0;`
333			`else if (drr_sel && spr_write)`
334			`drr <= #1 spr_dat_i[13:0];`
335			`else`
336			`drr <= #1 drr \| except_stop;`
337			`else
338			`assign drr = 14'b0;`
339			`endif
340
341			`//`
342			`// Read DU registers`
343			`//`
344			`ifdef OR1200_DU_READREGS
345			`always @(spr_addr or dsr or drr or dmr1 or dmr2)`
346			case (spr_addr[`OR1200_SPR_OFS_BITS])
347			`ifdef OR1200_DU_DMR1
348			`OR1200_DU_OFS_DMR1:
349			`spr_dat_o = {8'b0, dmr1, 22'b0};`
350			`endif
351			`ifdef OR1200_DU_DMR2
352			`OR1200_DU_OFS_DMR2:
353			`spr_dat_o = dmr2;`
354			`endif
355			`ifdef OR1200_DU_DSR
356			`OR1200_DU_OFS_DSR:
357			`spr_dat_o = {18'b0, dsr};`
358			`endif
359			`ifdef OR1200_DU_DRR
360			`OR1200_DU_OFS_DRR:
361			`spr_dat_o = {18'b0, drr};`
362			`endif
363			`default:`
364			`spr_dat_o = 32'h0000_0000;`
365			`endcase`
366			`endif
367
368			`//`
369			`// DSR alias`
370			`//`
371			`assign du_dsr = dsr;`
372
373			`else
374
375			`//`
376			`// When DU is not implemented, drive all outputs as would when DU is disabled`
377			`//`
378			`assign dbg_bp_o = 1'b0;`
379			assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
380
381			`//`
382			`// Read DU registers`
383			`//`
384			`ifdef OR1200_DU_READREGS
385			`assign spr_dat_o = 32'h0000_0000;`
386			`ifdef OR1200_DU_UNUSED_ZERO
387			`endif
388			`endif
389
390			`endif
391
392			`endmodule`