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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Exception logic                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Handles all OR1K exceptions inside CPU block.               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.15  2001/11/27 23:13:11  lampret
// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
//
// Revision 1.14  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.13  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.12  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.11  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.10  2001/11/13 10:02:21  lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.9  2001/11/10 03:43:57  lampret
// Fixed exceptions.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_EXCEPTFSM_WIDTH 3
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
 
//
// Exception recognition and sequencing
//
 
module or1200_except(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
        sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
        branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
        if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
        except_started, except_stop,
        wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
        esr, sr, lsu_addr
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           sig_ibuserr;
input                           sig_dbuserr;
input                           sig_illegal;
input                           sig_align;
input                           sig_range;
input                           sig_dtlbmiss;
input                           sig_dmmufault;
input                           sig_inthigh;
input                           sig_syscall;
input                           sig_trap;
input                           sig_itlbmiss;
input                           sig_immufault;
input                           sig_intlow;
input                           branch_taken;
input                           id_freeze;
input                           ex_freeze;
input                           wb_freeze;
input                           if_stall;
input   [31:0]                   if_pc;
output  [31:2]                  lr_sav;
input   [31:0]                   datain;
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
input                           epcr_we;
input                           eear_we;
input                           esr_we;
input                           pc_we;
output  [31:0]                   epcr;
output  [31:0]                   eear;
output  [`OR1200_SR_WIDTH-1:0]           esr;
input   [`OR1200_SR_WIDTH-1:0]           sr;
input   [31:0]                   lsu_addr;
output                          flushpipe;
output                          extend_flush;
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
output                          except_start;
output                          except_started;
output  [12:0]                   except_stop;
output  [31:0]                   wb_pc;
output  [31:0]                   ex_pc;
output  [31:0]                   id_pc;
 
//
// Internal regs and wires
//
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
reg     [31:0]                   id_pc;
reg     [31:0]                   ex_pc;
reg     [31:0]                   wb_pc;
reg     [31:0]                   epcr;
reg     [31:0]                   eear;
reg     [`OR1200_SR_WIDTH-1:0]           esr;
reg     [3:0]                    id_exceptflags;
reg     [3:0]                    ex_exceptflags;
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
reg                             extend_flush;
reg                             extend_flush_last;
reg                             ex_dslot;
reg                             delayed1_ex_dslot;
reg                             delayed2_ex_dslot;
wire                            except_started;
wire    [12:0]                   except_trig;
wire                            except_flushpipe;
reg     [2:0]                    delayed_eir;
wire                            inthigh_pending;
wire                            intlow_pending;
 
//
// Simple combinatorial logic
//
assign except_started = extend_flush & except_start;
assign lr_sav = ex_pc[31:2];
//assign except_start = (except_type != `OR1200_EXCEPT_NONE);  // damjan
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
 
//
// Order defines exception detection priority
//
assign except_trig = {
                        inthigh_pending         & ~du_dsr[`OR1200_DU_DSR_HPINTE],
                        ex_exceptflags[2]       & ~du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[1]       & ~du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[3]       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & ~du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & ~du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & ~du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & ~du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                        ex_exceptflags[0]        & ~du_dsr[`OR1200_DU_DSR_LPINTE],
                        sig_range               & ~du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
                        sig_syscall             & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                };
assign except_stop = {
                        inthigh_pending         & du_dsr[`OR1200_DU_DSR_HPINTE],
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[3]       & du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_LPINTE],
                        sig_range               & du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                };
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                id_pc <= #1 32'd0;
                id_exceptflags <= #1 4'b0000;
        end
        else if (flushpipe) begin
                id_pc <= #1 32'h0000_0000;
                id_exceptflags <= #1 4'b0000;
        end
        else if (!id_freeze) begin
                id_pc <= #1 if_pc;
                id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
        end
end
 
//
// delayed_eir
//
// SR[EIR] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_eir
// together with SR[EIR] enables interrupts once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
        if (rst)
                delayed_eir <= #1 3'b000;
        else if (!sr[`OR1200_SR_EIR])
                delayed_eir <= #1 3'b000;
        else
                delayed_eir <= #1 {delayed_eir[1:0], 1'b1};
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 32'd0;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 1'b0;
                delayed2_ex_dslot <= #1 1'b0;
        end
        else if (flushpipe) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 32'h0000_0000;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 1'b0;
                delayed2_ex_dslot <= #1 1'b0;
        end
        else if (!ex_freeze & id_freeze) begin
                ex_dslot <= #1 1'b0;
                ex_pc <= #1 id_pc;
                ex_exceptflags <= #1 4'b0000;
                delayed1_ex_dslot <= #1 ex_dslot;
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
        end
        else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display("%t: ex_pc <= %h", $time, id_pc);
// synopsys translate_on
`endif
                ex_dslot <= #1 branch_taken;
                ex_pc <= #1 id_pc;
                ex_exceptflags <= #1 id_exceptflags;
                delayed1_ex_dslot <= #1 ex_dslot;
                delayed2_ex_dslot <= #1 delayed1_ex_dslot;
        end
end
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                wb_pc <= #1 32'd0;
        end
        else if (!wb_freeze) begin
                wb_pc <= #1 ex_pc;
        end
end
 
//
// Flush pipeline
//
assign flushpipe = except_flushpipe | pc_we | extend_flush;
 
//
// We have started execution of exception handler:
//  1. Asserted for 3 clock cycles
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig & !state;
 
//
// Exception FSM that sequences execution of exception handler
//
// except_type signals which exception handler we start fetching in:
//  1. Asserted in next clock cycle after exception is recognized
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_EXCEPTFSM_IDLE;
                except_type <= #1 `OR1200_EXCEPT_NONE;
                extend_flush <= #1 1'b0;
                epcr <= #1 32'b0;
                eear <= #1 32'b0;
                esr <= #1 `OR1200_SR_WIDTH'b010;
                extend_flush_last <= #1 1'b0;
        end
        else begin
                case (state)    // synopsys full_case parallel_case
                        `OR1200_EXCEPTFSM_IDLE:
                                if (except_flushpipe) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                        if (ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during first delay slot instruction.");
// synopsys translate_on
`endif
                                        end
                                        else if (delayed1_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during second (NOP) delay slot instruction.");
// synopsys translate_on
`endif
                                        end
                                        else if (delayed2_ex_dslot) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
// synopsys translate_on
`endif
                                        end
                                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                $display(" INFO: Exception during normal (no delay slot) instruction.");
// synopsys translate_on
`endif
                                        end
 
                                        esr <= #1 sr;
                                        casex (except_trig)
                                                13'b1_xxxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_HPINT;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_1xxx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_01xx_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_IPF;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_001x_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0001_xxxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_1xxx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_ALIGN;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_01xx_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_001x_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_DPF;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_0001_xxxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_BUSERR;
                                                        eear <= #1 lsu_addr;
                                                        epcr <= #1 ex_dslot ? wb_pc : ex_pc;
                                                end
                                                13'b0_0000_0000_1xxx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_LPINT;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_01xx: begin
                                                        except_type <= #1 `OR1200_EXCEPT_RANGE;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_001x: begin
                                                        except_type <= #1 `OR1200_EXCEPT_TRAP;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                13'b0_0000_0000_0001: begin
                                                        except_type <= #1 `OR1200_EXCEPT_SYSCALL;
                                                        epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
                                                end
                                                default:
                                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                        endcase
                                end
                                else if (pc_we) begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU1;
                                        extend_flush <= #1 1'b1;
                                end
                                else begin
                                        if (epcr_we)
                                                epcr <= #1 datain;
                                        if (eear_we)
                                                eear <= #1 datain;
                                        if (esr_we)
                                                esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
                                end
                        `OR1200_EXCEPTFSM_FLU1:
//                              if (!if_stall & !id_freeze)
                                        state <= #1 `OR1200_EXCEPTFSM_FLU2;
                        `OR1200_EXCEPTFSM_FLU2:
                                if (except_type == `OR1200_EXCEPT_TRAP) begin
                                        state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0;
                                        except_type <= #1 `OR1200_EXCEPT_NONE;
                                end
                                else
//                              if (!if_stall & !id_freeze)
                                        state <= #1 `OR1200_EXCEPTFSM_FLU3;
                        `OR1200_EXCEPTFSM_FLU3:
//                              if (!if_stall && !id_freeze)
                                        begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                                if (except_flushpipe)
                                                        $display(" INFO: EPCR0 %h  EEAR %h  ESR %h", epcr, eear, esr);
// synopsys translate_on
`endif
                                                state <= #1 `OR1200_EXCEPTFSM_FLU4;
                                        end
                        `OR1200_EXCEPTFSM_FLU4: begin
                                        state <= #1 `OR1200_EXCEPTFSM_FLU5;
                                        extend_flush <= #1 1'b0;
                                        extend_flush_last <= #1 1'b0; // damjan
                                end
                        `OR1200_EXCEPTFSM_FLU5: begin
                                if (!if_stall && !id_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display(" INFO: Just finished flushing pipeline.");
// synopsys translate_on
`endif
                                state <= #1 `OR1200_EXCEPTFSM_IDLE;
                                except_type <= #1 `OR1200_EXCEPT_NONE;
                                extend_flush_last <= #1 1'b0;
                        end
                        end
                endcase
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Exception logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Handles all OR1K exceptions inside CPU block. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	570	lampret	`// Revision 1.2 2002/01/14 06:18:22 lampret`
48			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
49			`//`
50	562	lampret	`// Revision 1.1 2002/01/03 08:16:15 lampret`
51			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
52			`//`
53	504	lampret	`// Revision 1.15 2001/11/27 23:13:11 lampret`
54			`// Fixed except_stop width and fixed EX PC for 1400444f no-ops.`
55			`//`
56			`// Revision 1.14 2001/11/23 08:38:51 lampret`
57			`// Changed DSR/DRR behavior and exception detection.`
58			`//`
59			`// Revision 1.13 2001/11/20 18:46:15 simons`
60			`// Break point bug fixed`
61			`//`
62			`// Revision 1.12 2001/11/18 09:58:28 lampret`
63			`// Fixed some l.trap typos.`
64			`//`
65			`// Revision 1.11 2001/11/18 08:36:28 lampret`
66			`// For GDB changed single stepping and disabled trap exception.`
67			`//`
68			`// Revision 1.10 2001/11/13 10:02:21 lampret`
69			`// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)`
70			`//`
71			`// Revision 1.9 2001/11/10 03:43:57 lampret`
72			`// Fixed exceptions.`
73			`//`
74			`// Revision 1.8 2001/10/21 17:57:16 lampret`
75			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
76			`//`
77			`// Revision 1.7 2001/10/14 13:12:09 lampret`
78			`// MP3 version.`
79			`//`
80			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
81			`// no message`
82			`//`
83			`// Revision 1.2 2001/08/09 13:39:33 lampret`
84			`// Major clean-up.`
85			`//`
86			`// Revision 1.1 2001/07/20 00:46:03 lampret`
87			`// Development version of RTL. Libraries are missing.`
88			`//`
89			`//`
90
91			`// synopsys translate_off`
92			`include "timescale.v"
93			`// synopsys translate_on`
94			`include "or1200_defines.v"
95
96			`define OR1200_EXCEPTFSM_WIDTH 3
97			`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
98			`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
99			`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
100			`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
101			`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
102			`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
103
104			`//`
105			`// Exception recognition and sequencing`
106			`//`
107
108			`module or1200_except(`
109			`// Clock and reset`
110			`clk, rst,`
111
112			`// Internal i/f`
113			`sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,`
114			`sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,`
115			`branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,`
116			`if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,`
117			`except_started, except_stop,`
118	562	lampret	`wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,`
119	504	lampret	`esr, sr, lsu_addr`
120			`);`
121
122			`//`
123			`// I/O`
124			`//`
125			`input clk;`
126			`input rst;`
127			`input sig_ibuserr;`
128			`input sig_dbuserr;`
129			`input sig_illegal;`
130			`input sig_align;`
131			`input sig_range;`
132			`input sig_dtlbmiss;`
133			`input sig_dmmufault;`
134			`input sig_inthigh;`
135			`input sig_syscall;`
136			`input sig_trap;`
137			`input sig_itlbmiss;`
138			`input sig_immufault;`
139			`input sig_intlow;`
140			`input branch_taken;`
141			`input id_freeze;`
142			`input ex_freeze;`
143			`input wb_freeze;`
144			`input if_stall;`
145			`input [31:0] if_pc;`
146			`output [31:2] lr_sav;`
147			`input [31:0] datain;`
148			input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
149			`input epcr_we;`
150			`input eear_we;`
151			`input esr_we;`
152			`input pc_we;`
153			`output [31:0] epcr;`
154			`output [31:0] eear;`
155			output [`OR1200_SR_WIDTH-1:0] esr;
156			input [`OR1200_SR_WIDTH-1:0] sr;
157			`input [31:0] lsu_addr;`
158			`output flushpipe;`
159			`output extend_flush;`
160			output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
161			`output except_start;`
162			`output except_started;`
163			`output [12:0] except_stop;`
164			`output [31:0] wb_pc;`
165			`output [31:0] ex_pc;`
166	562	lampret	`output [31:0] id_pc;`
167	504	lampret
168			`//`
169			`// Internal regs and wires`
170			`//`
171			reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
172			`reg [31:0] id_pc;`
173			`reg [31:0] ex_pc;`
174			`reg [31:0] wb_pc;`
175			`reg [31:0] epcr;`
176			`reg [31:0] eear;`
177			reg [`OR1200_SR_WIDTH-1:0] esr;
178			`reg [3:0] id_exceptflags;`
179			`reg [3:0] ex_exceptflags;`
180			reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
181			`reg extend_flush;`
182			`reg extend_flush_last;`
183			`reg ex_dslot;`
184			`reg delayed1_ex_dslot;`
185			`reg delayed2_ex_dslot;`
186			`wire except_started;`
187			`wire [12:0] except_trig;`
188			`wire except_flushpipe;`
189			`reg [2:0] delayed_eir;`
190			`wire inthigh_pending;`
191			`wire intlow_pending;`
192
193			`//`
194			`// Simple combinatorial logic`
195			`//`
196			`assign except_started = extend_flush & except_start;`
197			`assign lr_sav = ex_pc[31:2];`
198	562	lampret	//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
199			assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
200			assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
201	504	lampret	assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
202
203			`//`
204			`// Order defines exception detection priority`
205			`//`
206			`assign except_trig = {`
207			inthigh_pending & ~du_dsr[`OR1200_DU_DSR_HPINTE],
208			ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_IME],
209			ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IPFE],
210			ex_exceptflags[3] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
211			sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
212			sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
213			sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
214			sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
215			sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
216			ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
217	570	lampret	sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
218	562	lampret	sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
219	570	lampret	sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
220	504	lampret	`};`
221			`assign except_stop = {`
222			inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
223			ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
224			ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
225			ex_exceptflags[3] & du_dsr[`OR1200_DU_DSR_BUSEE],
226			sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
227			sig_align & du_dsr[`OR1200_DU_DSR_AE],
228			sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
229			sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
230			sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
231			ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
232	570	lampret	sig_range & du_dsr[`OR1200_DU_DSR_RE],
233	562	lampret	sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
234	570	lampret	sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
235	504	lampret	`};`
236
237			`//`
238			`// PC and Exception flags pipelines`
239			`//`
240			`always @(posedge clk or posedge rst) begin`
241			`if (rst) begin`
242			`id_pc <= #1 32'd0;`
243			`id_exceptflags <= #1 4'b0000;`
244			`end`
245	562	lampret	`else if (flushpipe) begin`
246			`id_pc <= #1 32'h0000_0000;`
247			`id_exceptflags <= #1 4'b0000;`
248			`end`
249	504	lampret	`else if (!id_freeze) begin`
250			`id_pc <= #1 if_pc;`
251			`id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };`
252			`end`
253			`end`
254
255			`//`
256			`// delayed_eir`
257			`//`
258			`// SR[EIR] should not enable interrupts right away`
259			`// when it is restored with l.rfe. Instead delayed_eir`
260			`// together with SR[EIR] enables interrupts once`
261			`// pipeline is again ready.`
262			`//`
263			`always @(posedge rst or posedge clk)`
264			`if (rst)`
265			`delayed_eir <= #1 3'b000;`
266			else if (!sr[`OR1200_SR_EIR])
267			`delayed_eir <= #1 3'b000;`
268			`else`
269			`delayed_eir <= #1 {delayed_eir[1:0], 1'b1};`
270
271			`//`
272			`// PC and Exception flags pipelines`
273			`//`
274			`always @(posedge clk or posedge rst) begin`
275			`if (rst) begin`
276			`ex_dslot <= #1 1'b0;`
277			`ex_pc <= #1 32'd0;`
278			`ex_exceptflags <= #1 4'b0000;`
279			`delayed1_ex_dslot <= #1 1'b0;`
280			`delayed2_ex_dslot <= #1 1'b0;`
281			`end`
282	562	lampret	`else if (flushpipe) begin`
283			`ex_dslot <= #1 1'b0;`
284			`ex_pc <= #1 32'h0000_0000;`
285			`ex_exceptflags <= #1 4'b0000;`
286			`delayed1_ex_dslot <= #1 1'b0;`
287			`delayed2_ex_dslot <= #1 1'b0;`
288			`end`
289	504	lampret	`else if (!ex_freeze & id_freeze) begin`
290			`ex_dslot <= #1 1'b0;`
291			`ex_pc <= #1 id_pc;`
292			`ex_exceptflags <= #1 4'b0000;`
293			`delayed1_ex_dslot <= #1 ex_dslot;`
294			`delayed2_ex_dslot <= #1 delayed1_ex_dslot;`
295			`end`
296			`else if (!ex_freeze) begin`
297			`ifdef OR1200_VERBOSE
298			`// synopsys translate_off`
299			`$display("%t: ex_pc <= %h", $time, id_pc);`
300			`// synopsys translate_on`
301			`endif
302			`ex_dslot <= #1 branch_taken;`
303			`ex_pc <= #1 id_pc;`
304			`ex_exceptflags <= #1 id_exceptflags;`
305			`delayed1_ex_dslot <= #1 ex_dslot;`
306			`delayed2_ex_dslot <= #1 delayed1_ex_dslot;`
307			`end`
308			`end`
309
310			`//`
311			`// PC and Exception flags pipelines`
312			`//`
313			`always @(posedge clk or posedge rst) begin`
314			`if (rst) begin`
315			`wb_pc <= #1 32'd0;`
316			`end`
317			`else if (!wb_freeze) begin`
318			`wb_pc <= #1 ex_pc;`
319			`end`
320			`end`
321
322			`//`
323			`// Flush pipeline`
324			`//`
325	562	lampret	`assign flushpipe = except_flushpipe \| pc_we \| extend_flush;`
326	504	lampret
327			`//`
328			`// We have started execution of exception handler:`
329			`// 1. Asserted for 3 clock cycles`
330			`// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler`
331			`//`
332	562	lampret	`assign except_flushpipe = \|except_trig & !state;`
333	504	lampret
334			`//`
335			`// Exception FSM that sequences execution of exception handler`
336			`//`
337			`// except_type signals which exception handler we start fetching in:`
338			`// 1. Asserted in next clock cycle after exception is recognized`
339			`//`
340			`always @(posedge clk or posedge rst) begin`
341			`if (rst) begin`
342			state <= #1 `OR1200_EXCEPTFSM_IDLE;
343			except_type <= #1 `OR1200_EXCEPT_NONE;
344			`extend_flush <= #1 1'b0;`
345			`epcr <= #1 32'b0;`
346			`eear <= #1 32'b0;`
347			esr <= #1 `OR1200_SR_WIDTH'b010;
348			`extend_flush_last <= #1 1'b0;`
349			`end`
350			`else begin`
351			`case (state) // synopsys full_case parallel_case`
352			`OR1200_EXCEPTFSM_IDLE:
353			`if (except_flushpipe) begin`
354			state <= #1 `OR1200_EXCEPTFSM_FLU1;
355			`extend_flush <= #1 1'b1;`
356			`if (ex_dslot) begin`
357			`ifdef OR1200_VERBOSE
358			`// synopsys translate_off`
359			`$display(" INFO: Exception during first delay slot instruction.");`
360			`// synopsys translate_on`
361			`endif
362			`end`
363			`else if (delayed1_ex_dslot) begin`
364			`ifdef OR1200_VERBOSE
365			`// synopsys translate_off`
366			`$display(" INFO: Exception during second (NOP) delay slot instruction.");`
367			`// synopsys translate_on`
368			`endif
369			`end`
370			`else if (delayed2_ex_dslot) begin`
371			`ifdef OR1200_VERBOSE
372			`// synopsys translate_off`
373			`$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");`
374			`// synopsys translate_on`
375			`endif
376			`end`
377			`else begin`
378			`ifdef OR1200_VERBOSE
379			`// synopsys translate_off`
380			`$display(" INFO: Exception during normal (no delay slot) instruction.");`
381			`// synopsys translate_on`
382			`endif
383			`end`
384
385			`esr <= #1 sr;`
386			`casex (except_trig)`
387			`13'b1_xxxx_xxxx_xxxx: begin`
388			except_type <= #1 `OR1200_EXCEPT_HPINT;
389			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
390			`end`
391			`13'b0_1xxx_xxxx_xxxx: begin`
392			except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
393			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
394			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
395			`end`
396			`13'b0_01xx_xxxx_xxxx: begin`
397			except_type <= #1 `OR1200_EXCEPT_IPF;
398			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
399			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
400			`end`
401			`13'b0_001x_xxxx_xxxx: begin`
402			except_type <= #1 `OR1200_EXCEPT_BUSERR;
403			`eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
404			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
405			`end`
406			`13'b0_0001_xxxx_xxxx: begin`
407			except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
408			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
409			`end`
410			`13'b0_0000_1xxx_xxxx: begin`
411			except_type <= #1 `OR1200_EXCEPT_ALIGN;
412			`eear <= #1 lsu_addr;`
413			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
414			`end`
415			`13'b0_0000_01xx_xxxx: begin`
416			except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
417			`eear <= #1 lsu_addr;`
418			`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
419			`end`
420			`13'b0_0000_001x_xxxx: begin`
421			except_type <= #1 `OR1200_EXCEPT_DPF;
422			`eear <= #1 lsu_addr;`
423			`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
424			`end`
425			`13'b0_0000_0001_xxxx: begin`
426			except_type <= #1 `OR1200_EXCEPT_BUSERR;
427			`eear <= #1 lsu_addr;`
428	562	lampret	`epcr <= #1 ex_dslot ? wb_pc : ex_pc;`
429	504	lampret	`end`
430			`13'b0_0000_0000_1xxx: begin`
431			except_type <= #1 `OR1200_EXCEPT_LPINT;
432			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
433			`end`
434			`13'b0_0000_0000_01xx: begin`
435			except_type <= #1 `OR1200_EXCEPT_RANGE;
436			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
437			`end`
438			`13'b0_0000_0000_001x: begin`
439			except_type <= #1 `OR1200_EXCEPT_TRAP;
440			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
441			`end`
442			`13'b0_0000_0000_0001: begin`
443			except_type <= #1 `OR1200_EXCEPT_SYSCALL;
444			`epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;`
445			`end`
446			`default:`
447			except_type <= #1 `OR1200_EXCEPT_NONE;
448			`endcase`
449			`end`
450			`else if (pc_we) begin`
451			state <= #1 `OR1200_EXCEPTFSM_FLU1;
452			`extend_flush <= #1 1'b1;`
453			`end`
454			`else begin`
455			`if (epcr_we)`
456			`epcr <= #1 datain;`
457			`if (eear_we)`
458			`eear <= #1 datain;`
459			`if (esr_we)`
460			esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
461			`end`
462			`OR1200_EXCEPTFSM_FLU1:
463	562	lampret	`// if (!if_stall & !id_freeze)`
464	504	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU2;
465			`OR1200_EXCEPTFSM_FLU2:
466			if (except_type == `OR1200_EXCEPT_TRAP) begin
467			state <= #1 `OR1200_EXCEPTFSM_IDLE;
468			`extend_flush <= #1 1'b0;`
469			`extend_flush_last <= #1 1'b0;`
470			except_type <= #1 `OR1200_EXCEPT_NONE;
471			`end`
472	562	lampret	`else`
473			`// if (!if_stall & !id_freeze)`
474	504	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU3;
475			`OR1200_EXCEPTFSM_FLU3:
476	562	lampret	`// if (!if_stall && !id_freeze)`
477	504	lampret	`begin`
478			`ifdef OR1200_VERBOSE
479			`// synopsys translate_off`
480			`if (except_flushpipe)`
481			`$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);`
482			`// synopsys translate_on`
483			`endif
484			state <= #1 `OR1200_EXCEPTFSM_FLU4;
485			`end`
486			`OR1200_EXCEPTFSM_FLU4: begin
487	562	lampret	state <= #1 `OR1200_EXCEPTFSM_FLU5;
488			`extend_flush <= #1 1'b0;`
489			`extend_flush_last <= #1 1'b0; // damjan`
490			`end`
491	504	lampret	`OR1200_EXCEPTFSM_FLU5: begin
492	562	lampret	`if (!if_stall && !id_freeze) begin`
493	504	lampret	`ifdef OR1200_VERBOSE
494			`// synopsys translate_off`
495			`$display(" INFO: Just finished flushing pipeline.");`
496			`// synopsys translate_on`
497			`endif
498			state <= #1 `OR1200_EXCEPTFSM_IDLE;
499			except_type <= #1 `OR1200_EXCEPT_NONE;
500			`extend_flush_last <= #1 1'b0;`

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