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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's instruction fetch                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, instruction fetch, interface to IC.                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_if(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
 
        // Internal i/f
        if_freeze, if_insn, if_pc, flushpipe,
        if_stall, has_dslot, taken, genpc_refetch, rfe,
        except_itlbmiss, except_immufault, except_ibuserr
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
input   [31:0]                   icpu_dat_i;
input                           icpu_ack_i;
input                           icpu_rty_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
input   [3:0]                    icpu_tag_i;
 
//
// Internal i/f
//
input                           if_freeze;
output  [31:0]                   if_insn;
output  [31:0]                   if_pc;
input                           flushpipe;
output                          if_stall;
input                           has_dslot;
input                           taken;
output                          genpc_refetch;
input                           rfe;
output                          except_itlbmiss;
output                          except_immufault;
output                          except_ibuserr;
 
//
// Internal wires and regs
//
reg     [31:0]                   insn_saved;
reg     [31:0]                   addr_saved;
reg                             saved;
 
//
// IF stage insn
//
assign if_insn = icpu_err_i | has_dslot & taken | rfe ? {`OR1200_OR32_NOP, 26'h000_444F} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h000_666F};
assign if_pc = saved ? addr_saved : icpu_adr_i;
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
 
//
// Flag for saved insn/address
//
always @(posedge clk or posedge rst)
        if (rst)
                saved <= #1 1'b0;
        else if (flushpipe)
                saved <= #1 1'b0;
        else if (icpu_ack_i & if_freeze & !saved)
                saved <= #1 1'b1;
        else if (!if_freeze)
                saved <= #1 1'b0;
 
//
// Store fetched instruction
//
always @(posedge clk or posedge rst)
        if (rst)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
        else if (flushpipe)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
        else if (icpu_ack_i & if_freeze & !saved)
                insn_saved <= #1 icpu_dat_i;
        else if (!if_freeze)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
 
//
// Store fetched instruction's address
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_saved <= #1 32'h00000000;
        else if (flushpipe)
                addr_saved <= #1 32'h00000000;
        else if (icpu_ack_i & if_freeze & !saved)
                addr_saved <= #1 icpu_adr_i;
        else if (!if_freeze)
                addr_saved <= #1 icpu_adr_i;
 
endmodule

Line No.	Rev	Author	Line
1	504	lampret
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's instruction fetch ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// PC, instruction fetch, interface to IC. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.10 2001/11/20 18:46:15 simons`
49			`// Break point bug fixed`
50			`//`
51			`// Revision 1.9 2001/11/18 09:58:28 lampret`
52			`// Fixed some l.trap typos.`
53			`//`
54			`// Revision 1.8 2001/11/18 08:36:28 lampret`
55			`// For GDB changed single stepping and disabled trap exception.`
56			`//`
57			`// Revision 1.7 2001/10/21 17:57:16 lampret`
58			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
59			`//`
60			`// Revision 1.6 2001/10/14 13:12:09 lampret`
61			`// MP3 version.`
62			`//`
63			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
64			`// no message`
65			`//`
66			`// Revision 1.1 2001/08/09 13:39:33 lampret`
67			`// Major clean-up.`
68			`//`
69			`//`
70
71			`// synopsys translate_off`
72			`include "timescale.v"
73			`// synopsys translate_on`
74			`include "or1200_defines.v"
75
76			`module or1200_if(`
77			`// Clock and reset`
78			`clk, rst,`
79
80			`// External i/f to IC`
81			`icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,`
82
83			`// Internal i/f`
84			`if_freeze, if_insn, if_pc, flushpipe,`
85			`if_stall, has_dslot, taken, genpc_refetch, rfe,`
86			`except_itlbmiss, except_immufault, except_ibuserr`
87			`);`
88
89			`//`
90			`// I/O`
91			`//`
92
93			`//`
94			`// Clock and reset`
95			`//`
96			`input clk;`
97			`input rst;`
98
99			`//`
100			`// External i/f to IC`
101			`//`
102			`input [31:0] icpu_dat_i;`
103			`input icpu_ack_i;`
104			`input icpu_rty_i;`
105			`input icpu_err_i;`
106			`input [31:0] icpu_adr_i;`
107			`input [3:0] icpu_tag_i;`
108
109			`//`
110			`// Internal i/f`
111			`//`
112			`input if_freeze;`
113			`output [31:0] if_insn;`
114			`output [31:0] if_pc;`
115			`input flushpipe;`
116			`output if_stall;`
117			`input has_dslot;`
118			`input taken;`
119			`output genpc_refetch;`
120			`input rfe;`
121			`output except_itlbmiss;`
122			`output except_immufault;`
123			`output except_ibuserr;`
124
125			`//`
126			`// Internal wires and regs`
127			`//`
128			`reg [31:0] insn_saved;`
129			`reg [31:0] addr_saved;`
130			`reg saved;`
131
132			`//`
133			`// IF stage insn`
134			`//`
135			assign if_insn = icpu_err_i \| has_dslot & taken \| rfe ? {`OR1200_OR32_NOP, 26'h000_444F} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h000_666F};
136			`assign if_pc = saved ? addr_saved : icpu_adr_i;`
137			`assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;`
138			`assign genpc_refetch = saved & icpu_ack_i;`
139			assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
140			assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
141			assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
142
143			`//`
144			`// Flag for saved insn/address`
145			`//`
146			`always @(posedge clk or posedge rst)`
147			`if (rst)`
148			`saved <= #1 1'b0;`
149			`else if (flushpipe)`
150			`saved <= #1 1'b0;`
151			`else if (icpu_ack_i & if_freeze & !saved)`
152			`saved <= #1 1'b1;`
153			`else if (!if_freeze)`
154			`saved <= #1 1'b0;`
155
156			`//`
157			`// Store fetched instruction`
158			`//`
159			`always @(posedge clk or posedge rst)`
160			`if (rst)`
161			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
162			`else if (flushpipe)`
163			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
164			`else if (icpu_ack_i & if_freeze & !saved)`
165			`insn_saved <= #1 icpu_dat_i;`
166			`else if (!if_freeze)`
167			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
168
169			`//`
170			`// Store fetched instruction's address`
171			`//`
172			`always @(posedge clk or posedge rst)`
173			`if (rst)`
174			`addr_saved <= #1 32'h00000000;`
175			`else if (flushpipe)`
176			`addr_saved <= #1 32'h00000000;`
177			`else if (icpu_ack_i & if_freeze & !saved)`
178			`addr_saved <= #1 icpu_adr_i;`
179			`else if (!if_freeze)`
180			`addr_saved <= #1 icpu_adr_i;`
181
182			`endmodule`

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[/] [or1k/] [tags/] [asyst_3/] [or1200/] [rtl/] [verilog/] [or1200_if.v] - Blame information for rev 504