| 1 |
199 |
simons |
/*
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* linux/drivers/block/triton.c Version 1.13 Aug 12, 1996
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* Version 1.13a June 1998 - new chipsets
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* Version 1.13b July 1998 - DMA blacklist
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*
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* Copyright (c) 1995-1996 Mark Lord
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* May be copied or modified under the terms of the GNU General Public License
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*/
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/*
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* This module provides support for Bus Master IDE DMA functions in various
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* motherboard chipsets and PCI controller cards.
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* Please check /Documentation/ide.txt and /Documentation/udma.txt for details.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/pci.h>
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#include <linux/bios32.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#include "ide.h"
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#undef DISPLAY_TRITON_TIMINGS /* define this to display timings */
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#undef DISPLAY_APOLLO_TIMINGS /* define this for extensive debugging information */
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#if defined(CONFIG_PROC_FS) && defined(DISPLAY_APOLLO_TIMINGS)
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#include <linux/stat.h>
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#include <linux/proc_fs.h>
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#include <linux/via_ide_dma.h>
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#endif
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/*
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* good_dma_drives() lists the model names (from "hdparm -i")
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* of drives which do not support mword2 DMA but which are
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* known to work fine with this interface under Linux.
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*/
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const char *good_dma_drives[] = {"Micropolis 2112A",
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"CONNER CTMA 4000",
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"CONNER CTT8000-A",
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NULL};
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/*
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* bad_dma_drives() lists the model names (from "hdparm -i")
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* of drives which supposedly support (U)DMA but which are
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* known to corrupt data with this interface under Linux.
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*
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* Note: the list was generated by statistical analysis of problem
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* reports. It's not clear if there are problems with the drives,
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* or with some combination of drive/controller or what.
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*
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* You can forcibly override this if you wish. This is the kernel
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* 'Tread carefully' list.
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*
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* Finally see http://www.wdc.com/quality/err-rec.html if you have
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* one of the listed drives.
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*/
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const char *bad_dma_drives[] = {"WDC AC11000H",
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"WDC AC22100H",
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"WDC AC32500H",
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"WDC AC33100H",
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NULL};
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/*
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* Our Physical Region Descriptor (PRD) table should be large enough
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* to handle the biggest I/O request we are likely to see. Since requests
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* can have no more than 256 sectors, and since the typical blocksize is
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* two sectors, we could get by with a limit of 128 entries here for the
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* usual worst case. Most requests seem to include some contiguous blocks,
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* further reducing the number of table entries required.
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*
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* The driver reverts to PIO mode for individual requests that exceed
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* this limit (possible with 512 byte blocksizes, eg. MSDOS f/s), so handling
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* 100% of all crazy scenarios here is not necessary.
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*
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* As it turns out though, we must allocate a full 4KB page for this,
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* so the two PRD tables (ide0 & ide1) will each get half of that,
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* allowing each to have about 256 entries (8 bytes each) from this.
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*/
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#define PRD_BYTES 8
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#define PRD_ENTRIES (PAGE_SIZE / (2 * PRD_BYTES))
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#define DEFAULT_BMIBA 0xe800 /* in case BIOS did not init it */
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#define DEFAULT_BMCRBA 0xcc00 /* VIA's default value */
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/*
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* dma_intr() is the handler for disk read/write DMA interrupts
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*/
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static void dma_intr (ide_drive_t *drive)
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{
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byte stat, dma_stat;
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int i;
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struct request *rq = HWGROUP(drive)->rq;
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unsigned short dma_base = HWIF(drive)->dma_base;
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outb(inb(dma_base)&~1, dma_base); /* stop DMA operation */
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dma_stat = inb(dma_base+2); /* get DMA status */
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stat = GET_STAT(); /* get drive status */
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if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
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if ((dma_stat & 7) == 4) { /* verify good DMA status */
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rq = HWGROUP(drive)->rq;
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for (i = rq->nr_sectors; i > 0;) {
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i -= rq->current_nr_sectors;
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ide_end_request(1, HWGROUP(drive));
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}
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return;
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| 115 |
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}
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printk("%s: bad DMA status: 0x%02x\n", drive->name, dma_stat);
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}
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sti();
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ide_error(drive, "dma_intr", stat);
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}
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/*
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* build_dmatable() prepares a dma request.
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* Returns 0 if all went okay, returns 1 otherwise.
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*/
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static int build_dmatable (ide_drive_t *drive)
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{
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struct request *rq = HWGROUP(drive)->rq;
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struct buffer_head *bh = rq->bh;
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unsigned long size, addr, *table = HWIF(drive)->dmatable;
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unsigned int count = 0;
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do {
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/*
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* Determine addr and size of next buffer area. We assume that
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* individual virtual buffers are always composed linearly in
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* physical memory. For example, we assume that any 8kB buffer
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* is always composed of two adjacent physical 4kB pages rather
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* than two possibly non-adjacent physical 4kB pages.
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*/
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if (bh == NULL) { /* paging and tape requests have (rq->bh == NULL) */
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addr = virt_to_bus (rq->buffer);
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#ifdef CONFIG_BLK_DEV_IDETAPE
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if (drive->media == ide_tape)
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size = drive->tape.pc->request_transfer;
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else
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#endif /* CONFIG_BLK_DEV_IDETAPE */
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size = rq->nr_sectors << 9;
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} else {
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/* group sequential buffers into one large buffer */
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addr = virt_to_bus (bh->b_data);
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size = bh->b_size;
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while ((bh = bh->b_reqnext) != NULL) {
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if ((addr + size) != virt_to_bus (bh->b_data))
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break;
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size += bh->b_size;
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}
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| 158 |
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}
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| 159 |
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/*
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* Fill in the dma table, without crossing any 64kB boundaries.
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* We assume 16-bit alignment of all blocks.
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*/
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while (size) {
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if (++count >= PRD_ENTRIES) {
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printk("%s: DMA table too small\n", drive->name);
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return 1; /* revert to PIO for this request */
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} else {
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unsigned long bcount = 0x10000 - (addr & 0xffff);
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if (bcount > size)
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bcount = size;
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*table++ = addr;
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*table++ = bcount & 0xffff;
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addr += bcount;
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size -= bcount;
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}
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}
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} while (bh != NULL);
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if (count) {
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*--table |= 0x80000000; /* set End-Of-Table (EOT) bit */
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return 0;
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}
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printk("%s: empty DMA table?\n", drive->name);
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return 1; /* let the PIO routines handle this weirdness */
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}
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| 186 |
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| 187 |
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/*
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| 188 |
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* We will only enable drives with multi-word (mode2) (U)DMA capabilities,
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| 189 |
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* and ignore the very rare cases of drives that can only do single-word
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| 190 |
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* (modes 0 & 1) (U)DMA transfers. We also discard "blacklisted" hard disks.
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*/
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static int config_drive_for_dma (ide_drive_t *drive)
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{
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const char **list;
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struct hd_driveid *id = drive->id;
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| 197 |
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if (id && (id->capability & 1)) {
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/* Consult the list of known "bad" drives */
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list = bad_dma_drives;
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while (*list) {
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if (!strcmp(*list++,id->model)) {
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drive->using_dma = 0; /* no DMA */
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printk("ide: Disabling DMA modes on %s drive (%s).\n", drive->name, id->model);
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return 1; /* DMA disabled */
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}
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| 206 |
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}
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| 207 |
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/* Enable DMA on any drive that has mode 2 UltraDMA enabled */
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| 208 |
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if (id->field_valid & 4) /* UltraDMA */
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| 209 |
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if ((id->dma_ultra & 0x404) == 0x404) {
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| 210 |
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drive->using_dma = 1;
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return 0; /* DMA enabled */
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| 212 |
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}
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/* Enable DMA on any drive that has mode2 DMA enabled */
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| 214 |
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if (id->field_valid & 2) /* regular DMA */
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| 215 |
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if ((id->dma_mword & 0x404) == 0x404) {
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| 216 |
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drive->using_dma = 1;
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return 0; /* DMA enabled */
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| 218 |
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}
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| 219 |
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/* Consult the list of known "good" drives */
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| 220 |
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list = good_dma_drives;
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while (*list) {
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| 222 |
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if (!strcmp(*list++,id->model)) {
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| 223 |
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drive->using_dma = 1;
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| 224 |
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return 0; /* DMA enabled */
|
| 225 |
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}
|
| 226 |
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}
|
| 227 |
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}
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| 228 |
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return 1; /* DMA not enabled */
|
| 229 |
|
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}
|
| 230 |
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| 231 |
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/*
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| 232 |
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* triton_dmaproc() initiates/aborts DMA read/write operations on a drive.
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| 233 |
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*
|
| 234 |
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* The caller is assumed to have selected the drive and programmed the drive's
|
| 235 |
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* sector address using CHS or LBA. All that remains is to prepare for DMA
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| 236 |
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* and then issue the actual read/write DMA/PIO command to the drive.
|
| 237 |
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*
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| 238 |
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* For ATAPI devices, we just prepare for DMA and return. The caller should
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| 239 |
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* then issue the packet command to the drive and call us again with
|
| 240 |
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* ide_dma_begin afterwards.
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| 241 |
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*
|
| 242 |
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* Returns 0 if all went well.
|
| 243 |
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* Returns 1 if DMA read/write could not be started, in which case
|
| 244 |
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* the caller should revert to PIO for the current request.
|
| 245 |
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*/
|
| 246 |
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static int triton_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
|
| 247 |
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{
|
| 248 |
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unsigned long dma_base = HWIF(drive)->dma_base;
|
| 249 |
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unsigned int reading = (1 << 3);
|
| 250 |
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|
| 251 |
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switch (func) {
|
| 252 |
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case ide_dma_abort:
|
| 253 |
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outb(inb(dma_base)&~1, dma_base); /* stop DMA */
|
| 254 |
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return 0;
|
| 255 |
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case ide_dma_check:
|
| 256 |
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return config_drive_for_dma (drive);
|
| 257 |
|
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case ide_dma_write:
|
| 258 |
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reading = 0;
|
| 259 |
|
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case ide_dma_read:
|
| 260 |
|
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break;
|
| 261 |
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case ide_dma_status_bad:
|
| 262 |
|
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return ((inb(dma_base+2) & 7) != 4); /* verify good DMA status */
|
| 263 |
|
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case ide_dma_transferred:
|
| 264 |
|
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#if 0
|
| 265 |
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return (number of bytes actually transferred);
|
| 266 |
|
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#else
|
| 267 |
|
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return (0);
|
| 268 |
|
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#endif
|
| 269 |
|
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case ide_dma_begin:
|
| 270 |
|
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outb(inb(dma_base)|1, dma_base); /* begin DMA */
|
| 271 |
|
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return 0;
|
| 272 |
|
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default:
|
| 273 |
|
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printk("triton_dmaproc: unsupported func: %d\n", func);
|
| 274 |
|
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return 1;
|
| 275 |
|
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}
|
| 276 |
|
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if (build_dmatable (drive))
|
| 277 |
|
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return 1;
|
| 278 |
|
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outl(virt_to_bus (HWIF(drive)->dmatable), dma_base + 4); /* PRD table */
|
| 279 |
|
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outb(reading, dma_base); /* specify r/w */
|
| 280 |
|
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outb(inb(dma_base+2)|0x06, dma_base+2); /* clear status bits */
|
| 281 |
|
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#ifdef CONFIG_BLK_DEV_IDEATAPI
|
| 282 |
|
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if (drive->media != ide_disk)
|
| 283 |
|
|
return 0;
|
| 284 |
|
|
#endif /* CONFIG_BLK_DEV_IDEATAPI */
|
| 285 |
|
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ide_set_handler(drive, &dma_intr, WAIT_CMD); /* issue cmd to drive */
|
| 286 |
|
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OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
|
| 287 |
|
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outb(inb(dma_base)|1, dma_base); /* begin DMA */
|
| 288 |
|
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return 0;
|
| 289 |
|
|
}
|
| 290 |
|
|
|
| 291 |
|
|
#ifdef DISPLAY_TRITON_TIMINGS
|
| 292 |
|
|
/*
|
| 293 |
|
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* print_triton_drive_flags() displays the currently programmed options
|
| 294 |
|
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* in the i82371 (Triton) for a given drive.
|
| 295 |
|
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*
|
| 296 |
|
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* If fastDMA is "no", then slow ISA timings are used for DMA data xfers.
|
| 297 |
|
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* If fastPIO is "no", then slow ISA timings are used for PIO data xfers.
|
| 298 |
|
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* If IORDY is "no", then IORDY is assumed to always be asserted.
|
| 299 |
|
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* If PreFetch is "no", then data pre-fetch/post are not used.
|
| 300 |
|
|
*
|
| 301 |
|
|
* When "fastPIO" and/or "fastDMA" are "yes", then faster PCI timings and
|
| 302 |
|
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* back-to-back 16-bit data transfers are enabled, using the sample_CLKs
|
| 303 |
|
|
* and recovery_CLKs (PCI clock cycles) timing parameters for that interface.
|
| 304 |
|
|
*/
|
| 305 |
|
|
static void print_triton_drive_flags (unsigned int unit, byte flags)
|
| 306 |
|
|
{
|
| 307 |
|
|
printk(" %s ", unit ? "slave :" : "master:");
|
| 308 |
|
|
printk( "fastDMA=%s", (flags&9) ? "on " : "off");
|
| 309 |
|
|
printk(" PreFetch=%s", (flags&4) ? "on " : "off");
|
| 310 |
|
|
printk(" IORDY=%s", (flags&2) ? "on " : "off");
|
| 311 |
|
|
printk(" fastPIO=%s\n", ((flags&9)==1) ? "on " : "off");
|
| 312 |
|
|
}
|
| 313 |
|
|
#endif /* DISPLAY_TRITON_TIMINGS */
|
| 314 |
|
|
|
| 315 |
|
|
static void init_triton_dma (ide_hwif_t *hwif, unsigned short base)
|
| 316 |
|
|
{
|
| 317 |
|
|
static unsigned long dmatable = 0;
|
| 318 |
|
|
|
| 319 |
|
|
printk(" %s: BM-DMA at 0x%04x-0x%04x", hwif->name, base, base+7);
|
| 320 |
|
|
if (check_region(base, 8)) {
|
| 321 |
|
|
printk(" -- ERROR, PORTS ALREADY IN USE");
|
| 322 |
|
|
} else {
|
| 323 |
|
|
request_region(base, 8, "IDE DMA");
|
| 324 |
|
|
hwif->dma_base = base;
|
| 325 |
|
|
if (!dmatable) {
|
| 326 |
|
|
/*
|
| 327 |
|
|
* The BM-DMA uses a full 32-bits, so we can
|
| 328 |
|
|
* safely use __get_free_page() here instead
|
| 329 |
|
|
* of __get_dma_pages() -- no ISA limitations.
|
| 330 |
|
|
*/
|
| 331 |
|
|
dmatable = __get_free_pages(GFP_KERNEL, 1, 0);
|
| 332 |
|
|
}
|
| 333 |
|
|
if (dmatable) {
|
| 334 |
|
|
hwif->dmatable = (unsigned long *) dmatable;
|
| 335 |
|
|
dmatable += (PRD_ENTRIES * PRD_BYTES);
|
| 336 |
|
|
outl(virt_to_bus(hwif->dmatable), base + 4);
|
| 337 |
|
|
hwif->dmaproc = &triton_dmaproc;
|
| 338 |
|
|
}
|
| 339 |
|
|
}
|
| 340 |
|
|
printk("\n");
|
| 341 |
|
|
}
|
| 342 |
|
|
|
| 343 |
|
|
/*
|
| 344 |
|
|
* Set VIA Chipset Timings for (U)DMA modes enabled.
|
| 345 |
|
|
*/
|
| 346 |
|
|
static int set_via_timings (byte bus, byte fn, byte post, byte flush)
|
| 347 |
|
|
{
|
| 348 |
|
|
byte via_config = 0;
|
| 349 |
|
|
int rc = 0;
|
| 350 |
|
|
|
| 351 |
|
|
/* setting IDE read prefetch buffer and IDE post write buffer */
|
| 352 |
|
|
if ((rc = pcibios_read_config_byte(bus, fn, 0x41, &via_config)))
|
| 353 |
|
|
return (1);
|
| 354 |
|
|
if ((rc = pcibios_write_config_byte(bus, fn, 0x41, via_config | post)))
|
| 355 |
|
|
return (1);
|
| 356 |
|
|
|
| 357 |
|
|
/* setting Channel read and End-of-sector FIFO flush: */
|
| 358 |
|
|
if ((rc = pcibios_read_config_byte(bus, fn, 0x46, &via_config)))
|
| 359 |
|
|
return (1);
|
| 360 |
|
|
if ((rc = pcibios_write_config_byte(bus, fn, 0x46, via_config | flush)))
|
| 361 |
|
|
return (1);
|
| 362 |
|
|
|
| 363 |
|
|
return (0);
|
| 364 |
|
|
}
|
| 365 |
|
|
|
| 366 |
|
|
/*
|
| 367 |
|
|
* ide_init_triton() prepares the IDE driver for DMA operation.
|
| 368 |
|
|
* This routine is called once, from ide.c during driver initialization,
|
| 369 |
|
|
* for each BM-DMA chipset which is found (rarely more than one).
|
| 370 |
|
|
*/
|
| 371 |
|
|
void ide_init_triton (byte bus, byte fn)
|
| 372 |
|
|
{
|
| 373 |
|
|
int rc = 0, h;
|
| 374 |
|
|
int dma_enabled = 0;
|
| 375 |
|
|
unsigned short io[6], count = 0, step_count = 0;
|
| 376 |
|
|
unsigned short pcicmd, vendor, device, class;
|
| 377 |
|
|
unsigned int bmiba, timings, reg, tmp;
|
| 378 |
|
|
unsigned int addressbios = 0;
|
| 379 |
|
|
|
| 380 |
|
|
#ifdef DISPLAY_APOLLO_TIMINGS
|
| 381 |
|
|
bmide_bus = bus;
|
| 382 |
|
|
bmide_fn = fn;
|
| 383 |
|
|
#endif /* DISPLAY_APOLLO_TIMINGS */
|
| 384 |
|
|
|
| 385 |
|
|
/*
|
| 386 |
|
|
* We pick up the vendor, device, and class info for selecting the correct
|
| 387 |
|
|
* controller that is supported. Since we can access this routine more than
|
| 388 |
|
|
* once with the use of onboard and off-board EIDE controllers, a method
|
| 389 |
|
|
* of determining "who is who for what" is needed.
|
| 390 |
|
|
*/
|
| 391 |
|
|
|
| 392 |
|
|
pcibios_read_config_word (bus, fn, PCI_VENDOR_ID, &vendor);
|
| 393 |
|
|
pcibios_read_config_word (bus, fn, PCI_DEVICE_ID, &device);
|
| 394 |
|
|
pcibios_read_config_word (bus, fn, PCI_CLASS_DEVICE, &class);
|
| 395 |
|
|
|
| 396 |
|
|
switch(vendor) {
|
| 397 |
|
|
case PCI_VENDOR_ID_INTEL:
|
| 398 |
|
|
printk("ide: Intel 82371 (single FIFO) DMA Bus Mastering IDE ");
|
| 399 |
|
|
break;
|
| 400 |
|
|
case PCI_VENDOR_ID_SI:
|
| 401 |
|
|
printk("ide: SiS 5513 (dual FIFO) DMA Bus Mastering IDE ");
|
| 402 |
|
|
break;
|
| 403 |
|
|
case PCI_VENDOR_ID_VIA:
|
| 404 |
|
|
printk("ide: VIA VT82C586B (split FIFO) UDMA Bus Mastering IDE ");
|
| 405 |
|
|
break;
|
| 406 |
|
|
case PCI_VENDOR_ID_PROMISE:
|
| 407 |
|
|
/* PCI_CLASS_STORAGE_RAID == class */
|
| 408 |
|
|
/*
|
| 409 |
|
|
* I have been able to make my Promise Ultra33 UDMA card change class.
|
| 410 |
|
|
* It has reported as both PCI_CLASS_STORAGE_RAID and PCI_CLASS_STORAGE_IDE.
|
| 411 |
|
|
* Since the PCI_CLASS_STORAGE_RAID mode should automatically mirror the
|
| 412 |
|
|
* two halves of the PCI_CONFIG register data, but sometimes it forgets.
|
| 413 |
|
|
* Thus we guarantee that they are identical, with a quick check and
|
| 414 |
|
|
* correction if needed.
|
| 415 |
|
|
* PDC20246 (primary) PDC20247 (secondary) IDE hwif's.
|
| 416 |
|
|
*
|
| 417 |
|
|
* Note that Promise "stories,fibs,..." about this device not being
|
| 418 |
|
|
* capable of ATAPI and AT devices.
|
| 419 |
|
|
*/
|
| 420 |
|
|
if (PCI_CLASS_STORAGE_RAID == class) {
|
| 421 |
|
|
unsigned char irq1 = 0, irq2 = 0;
|
| 422 |
|
|
pcibios_read_config_byte (bus, fn, PCI_INTERRUPT_LINE, &irq1);
|
| 423 |
|
|
pcibios_read_config_byte (bus, fn, (PCI_INTERRUPT_LINE)|0x80, &irq2);
|
| 424 |
|
|
if (irq1 != irq2) {
|
| 425 |
|
|
pcibios_write_config_byte(bus, fn, (PCI_INTERRUPT_LINE)|0x80, irq1);
|
| 426 |
|
|
}
|
| 427 |
|
|
}
|
| 428 |
|
|
case PCI_VENDOR_ID_ARTOP:
|
| 429 |
|
|
/* PCI_CLASS_STORAGE_SCSI == class */
|
| 430 |
|
|
/*
|
| 431 |
|
|
* I have found that by stroking rom_enable_bit on both the AEC6210U/UF and
|
| 432 |
|
|
* PDC20246 controller cards, the features desired are almost guaranteed
|
| 433 |
|
|
* to be enabled and compatible. This ROM may not be registered in the
|
| 434 |
|
|
* config data, but it can be turned on. Registration failure has only
|
| 435 |
|
|
* been observed if and only if Linux sets up the pci_io_address in the
|
| 436 |
|
|
* 0x6000 range. If they are setup in the 0xef00 range it is reported.
|
| 437 |
|
|
* WHY??? got me.........
|
| 438 |
|
|
*/
|
| 439 |
|
|
printk("ide: %s UDMA Bus Mastering ",
|
| 440 |
|
|
(vendor == PCI_VENDOR_ID_ARTOP) ? "AEC6210" : "PDC20246");
|
| 441 |
|
|
pcibios_read_config_dword(bus, fn, PCI_ROM_ADDRESS, &addressbios);
|
| 442 |
|
|
if (addressbios) {
|
| 443 |
|
|
pcibios_write_config_byte(bus, fn, PCI_ROM_ADDRESS, addressbios | PCI_ROM_ADDRESS_ENABLE);
|
| 444 |
|
|
printk("with ROM enabled at 0x%08x", addressbios);
|
| 445 |
|
|
}
|
| 446 |
|
|
/*
|
| 447 |
|
|
* This was stripped out of 2.1.XXX kernel code and parts from a patch called
|
| 448 |
|
|
* promise_update. This finds the PCI_BASE_ADDRESS spaces and makes them
|
| 449 |
|
|
* available for configuration later.
|
| 450 |
|
|
* PCI_BASE_ADDRESS_0 hwif0->io_base
|
| 451 |
|
|
* PCI_BASE_ADDRESS_1 hwif0->ctl_port
|
| 452 |
|
|
* PCI_BASE_ADDRESS_2 hwif1->io_base
|
| 453 |
|
|
* PCI_BASE_ADDRESS_3 hwif1->ctl_port
|
| 454 |
|
|
* PCI_BASE_ADDRESS_4 bmiba
|
| 455 |
|
|
*/
|
| 456 |
|
|
memset(io, 0, 6 * sizeof(unsigned short));
|
| 457 |
|
|
for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
|
| 458 |
|
|
pcibios_read_config_dword(bus, fn, reg, &tmp);
|
| 459 |
|
|
if (tmp & PCI_BASE_ADDRESS_SPACE_IO)
|
| 460 |
|
|
io[count++] = tmp & PCI_BASE_ADDRESS_IO_MASK;
|
| 461 |
|
|
}
|
| 462 |
|
|
break;
|
| 463 |
|
|
default:
|
| 464 |
|
|
return;
|
| 465 |
|
|
}
|
| 466 |
|
|
|
| 467 |
|
|
printk("\n Controller on PCI bus %d function %d\n", bus, fn);
|
| 468 |
|
|
|
| 469 |
|
|
/*
|
| 470 |
|
|
* See if IDE and BM-DMA features are enabled:
|
| 471 |
|
|
*/
|
| 472 |
|
|
if ((rc = pcibios_read_config_word(bus, fn, PCI_COMMAND, &pcicmd)))
|
| 473 |
|
|
goto quit;
|
| 474 |
|
|
if ((pcicmd & 1) == 0) {
|
| 475 |
|
|
printk("ide: ports are not enabled (BIOS)\n");
|
| 476 |
|
|
goto quit;
|
| 477 |
|
|
}
|
| 478 |
|
|
if ((pcicmd & 4) == 0) {
|
| 479 |
|
|
printk("ide: BM-DMA feature is not enabled (BIOS)\n");
|
| 480 |
|
|
} else {
|
| 481 |
|
|
/*
|
| 482 |
|
|
* Get the bmiba base address
|
| 483 |
|
|
*/
|
| 484 |
|
|
int try_again = 1;
|
| 485 |
|
|
do {
|
| 486 |
|
|
if ((rc = pcibios_read_config_dword(bus, fn, PCI_BASE_ADDRESS_4, &bmiba)))
|
| 487 |
|
|
goto quit;
|
| 488 |
|
|
bmiba &= 0xfff0; /* extract port base address */
|
| 489 |
|
|
if (bmiba) {
|
| 490 |
|
|
dma_enabled = 1;
|
| 491 |
|
|
break;
|
| 492 |
|
|
} else {
|
| 493 |
|
|
printk("ide: BM-DMA base register is invalid (0x%04x, PnP BIOS problem)\n", bmiba);
|
| 494 |
|
|
if (inb(((vendor == PCI_VENDOR_ID_VIA) ? DEFAULT_BMCRBA : DEFAULT_BMIBA)) != 0xff || !try_again)
|
| 495 |
|
|
break;
|
| 496 |
|
|
printk("ide: setting BM-DMA base register to 0x%04x\n", ((vendor == PCI_VENDOR_ID_VIA) ? DEFAULT_BMCRBA : DEFAULT_BMIBA));
|
| 497 |
|
|
if ((rc = pcibios_write_config_word(bus, fn, PCI_COMMAND, pcicmd&~1)))
|
| 498 |
|
|
goto quit;
|
| 499 |
|
|
rc = pcibios_write_config_dword(bus, fn, 0x20, ((vendor == PCI_VENDOR_ID_VIA) ? DEFAULT_BMCRBA : DEFAULT_BMIBA)|1);
|
| 500 |
|
|
if (pcibios_write_config_word(bus, fn, PCI_COMMAND, pcicmd|5) || rc)
|
| 501 |
|
|
goto quit;
|
| 502 |
|
|
}
|
| 503 |
|
|
} while (try_again--);
|
| 504 |
|
|
}
|
| 505 |
|
|
|
| 506 |
|
|
/*
|
| 507 |
|
|
* See if ide port(s) are enabled
|
| 508 |
|
|
*/
|
| 509 |
|
|
if ((rc = pcibios_read_config_dword(bus, fn,
|
| 510 |
|
|
(vendor == PCI_VENDOR_ID_PROMISE) ? 0x50 :
|
| 511 |
|
|
(vendor == PCI_VENDOR_ID_ARTOP) ? 0x54 :
|
| 512 |
|
|
0x40, &timings)))
|
| 513 |
|
|
goto quit;
|
| 514 |
|
|
/*
|
| 515 |
|
|
* We do a vendor check since the Ultra33 and AEC6210
|
| 516 |
|
|
* holds their timings in a different location.
|
| 517 |
|
|
*/
|
| 518 |
|
|
printk("ide: timings == %08x\n", timings);
|
| 519 |
|
|
|
| 520 |
|
|
/*
|
| 521 |
|
|
* The switch preserves some stuff that was original.
|
| 522 |
|
|
*/
|
| 523 |
|
|
switch(vendor) {
|
| 524 |
|
|
case PCI_VENDOR_ID_INTEL:
|
| 525 |
|
|
if (!(timings & 0x80008000)) {
|
| 526 |
|
|
printk("ide: INTEL: neither port is enabled\n");
|
| 527 |
|
|
goto quit;
|
| 528 |
|
|
}
|
| 529 |
|
|
break;
|
| 530 |
|
|
case PCI_VENDOR_ID_VIA:
|
| 531 |
|
|
if(!(timings & 0x03)) {
|
| 532 |
|
|
printk("ide: VIA: neither port is enabled\n");
|
| 533 |
|
|
goto quit;
|
| 534 |
|
|
}
|
| 535 |
|
|
break;
|
| 536 |
|
|
case PCI_VENDOR_ID_SI:
|
| 537 |
|
|
case PCI_VENDOR_ID_PROMISE:
|
| 538 |
|
|
case PCI_VENDOR_ID_ARTOP:
|
| 539 |
|
|
default:
|
| 540 |
|
|
break;
|
| 541 |
|
|
}
|
| 542 |
|
|
|
| 543 |
|
|
/*
|
| 544 |
|
|
* Save the dma_base port addr for each interface
|
| 545 |
|
|
*/
|
| 546 |
|
|
for (h = 0; h < MAX_HWIFS; ++h) {
|
| 547 |
|
|
ide_hwif_t *hwif = &ide_hwifs[h];
|
| 548 |
|
|
|
| 549 |
|
|
/*
|
| 550 |
|
|
* This prevents the first contoller from accidentally
|
| 551 |
|
|
* initalizing the hwif's that it does not use and block
|
| 552 |
|
|
* an off-board ide-pci from getting in the game.
|
| 553 |
|
|
*/
|
| 554 |
|
|
if (step_count >= 2) {
|
| 555 |
|
|
goto quit;
|
| 556 |
|
|
}
|
| 557 |
|
|
#ifdef CONFIG_BLK_DEV_OFFBOARD
|
| 558 |
|
|
/*
|
| 559 |
|
|
* This is a forced override for the onboard ide controller
|
| 560 |
|
|
* to be enabled, if one chooses to have an offboard ide-pci
|
| 561 |
|
|
* card as the primary booting device. This beasty is
|
| 562 |
|
|
* for offboard UDMA upgrades with hard disks, but saving
|
| 563 |
|
|
* the onboard DMA2 controllers for CDROMS, TAPES, ZIPS, etc...
|
| 564 |
|
|
*/
|
| 565 |
|
|
if ((vendor == PCI_VENDOR_ID_INTEL) ||
|
| 566 |
|
|
(vendor == PCI_VENDOR_ID_SI) ||
|
| 567 |
|
|
(vendor == PCI_VENDOR_ID_VIA)) {
|
| 568 |
|
|
if (h == 2) {
|
| 569 |
|
|
hwif->io_base = 0x1f0;
|
| 570 |
|
|
hwif->ctl_port = 0x3f6;
|
| 571 |
|
|
hwif->irq = 14;
|
| 572 |
|
|
hwif->noprobe = 0;
|
| 573 |
|
|
}
|
| 574 |
|
|
if (h == 3) {
|
| 575 |
|
|
hwif->io_base = 0x170;
|
| 576 |
|
|
hwif->ctl_port = 0x376;
|
| 577 |
|
|
hwif->irq = 15;
|
| 578 |
|
|
hwif->noprobe = 0;
|
| 579 |
|
|
}
|
| 580 |
|
|
}
|
| 581 |
|
|
#endif /* CONFIG_BLK_DEV_OFFBOARD */
|
| 582 |
|
|
/*
|
| 583 |
|
|
* If the chipset is listed as "ide_unknown", lets get a
|
| 584 |
|
|
* hwif while they last. This does the first check on
|
| 585 |
|
|
* the current availability of the ide_hwifs[h] in question.
|
| 586 |
|
|
*/
|
| 587 |
|
|
if (hwif->chipset != ide_unknown) {
|
| 588 |
|
|
continue;
|
| 589 |
|
|
} else if (vendor == PCI_VENDOR_ID_INTEL) {
|
| 590 |
|
|
unsigned short time;
|
| 591 |
|
|
#ifdef DISPLAY_TRITON_TIMINGS
|
| 592 |
|
|
byte s_clks, r_clks;
|
| 593 |
|
|
unsigned short devid;
|
| 594 |
|
|
#endif /* DISPLAY_TRITON_TIMINGS */
|
| 595 |
|
|
if (hwif->io_base == 0x1f0) {
|
| 596 |
|
|
time = timings & 0xffff;
|
| 597 |
|
|
if ((time & 0x8000) == 0) /* interface enabled? */
|
| 598 |
|
|
continue;
|
| 599 |
|
|
hwif->chipset = ide_triton;
|
| 600 |
|
|
if (dma_enabled)
|
| 601 |
|
|
init_triton_dma(hwif, bmiba);
|
| 602 |
|
|
step_count++;
|
| 603 |
|
|
} else if (hwif->io_base == 0x170) {
|
| 604 |
|
|
time = timings >> 16;
|
| 605 |
|
|
if ((time & 0x8000) == 0) /* interface enabled? */
|
| 606 |
|
|
continue;
|
| 607 |
|
|
hwif->chipset = ide_triton;
|
| 608 |
|
|
if (dma_enabled)
|
| 609 |
|
|
init_triton_dma(hwif, bmiba + 8);
|
| 610 |
|
|
step_count++;
|
| 611 |
|
|
} else {
|
| 612 |
|
|
continue;
|
| 613 |
|
|
}
|
| 614 |
|
|
#ifdef DISPLAY_TRITON_TIMINGS
|
| 615 |
|
|
s_clks = ((~time >> 12) & 3) + 2;
|
| 616 |
|
|
r_clks = ((~time >> 8) & 3) + 1;
|
| 617 |
|
|
printk(" %s timing: (0x%04x) sample_CLKs=%d, recovery_CLKs=%d\n",
|
| 618 |
|
|
hwif->name, time, s_clks, r_clks);
|
| 619 |
|
|
if ((time & 0x40) && !pcibios_read_config_word(bus, fn, PCI_DEVICE_ID, &devid)
|
| 620 |
|
|
&& devid == PCI_DEVICE_ID_INTEL_82371SB_1) {
|
| 621 |
|
|
byte stime;
|
| 622 |
|
|
if (pcibios_read_config_byte(bus, fn, 0x44, &stime)) {
|
| 623 |
|
|
if (hwif->io_base == 0x1f0) {
|
| 624 |
|
|
s_clks = ~stime >> 6;
|
| 625 |
|
|
r_clks = ~stime >> 4;
|
| 626 |
|
|
} else {
|
| 627 |
|
|
s_clks = ~stime >> 2;
|
| 628 |
|
|
r_clks = ~stime;
|
| 629 |
|
|
}
|
| 630 |
|
|
s_clks = (s_clks & 3) + 2;
|
| 631 |
|
|
r_clks = (r_clks & 3) + 1;
|
| 632 |
|
|
printk(" slave: sample_CLKs=%d, recovery_CLKs=%d\n",
|
| 633 |
|
|
s_clks, r_clks);
|
| 634 |
|
|
}
|
| 635 |
|
|
}
|
| 636 |
|
|
print_triton_drive_flags (0, time & 0xf);
|
| 637 |
|
|
print_triton_drive_flags (1, (time >> 4) & 0xf);
|
| 638 |
|
|
#endif /* DISPLAY_TRITON_TIMINGS */
|
| 639 |
|
|
} else if (vendor == PCI_VENDOR_ID_SI) {
|
| 640 |
|
|
if (hwif->io_base == 0x1f0) {
|
| 641 |
|
|
hwif->chipset = ide_triton;
|
| 642 |
|
|
if (dma_enabled)
|
| 643 |
|
|
init_triton_dma(hwif, bmiba);
|
| 644 |
|
|
step_count++;
|
| 645 |
|
|
} else if (hwif->io_base == 0x170) {
|
| 646 |
|
|
hwif->chipset = ide_triton;
|
| 647 |
|
|
if (dma_enabled)
|
| 648 |
|
|
init_triton_dma(hwif, bmiba + 8);
|
| 649 |
|
|
step_count++;
|
| 650 |
|
|
} else {
|
| 651 |
|
|
continue;
|
| 652 |
|
|
}
|
| 653 |
|
|
} else if(vendor == PCI_VENDOR_ID_VIA) {
|
| 654 |
|
|
if (hwif->io_base == 0x1f0) {
|
| 655 |
|
|
if((timings & 0x02) == 0)
|
| 656 |
|
|
continue;
|
| 657 |
|
|
hwif->chipset = ide_triton;
|
| 658 |
|
|
if (dma_enabled)
|
| 659 |
|
|
init_triton_dma(hwif, bmiba);
|
| 660 |
|
|
if (set_via_timings(bus, fn, 0xc0, 0xa0))
|
| 661 |
|
|
goto quit;
|
| 662 |
|
|
#ifdef DISPLAY_APOLLO_TIMINGS
|
| 663 |
|
|
proc_register_dynamic(&proc_root, &via_proc_entry);
|
| 664 |
|
|
#endif /* DISPLAY_APOLLO_TIMINGS */
|
| 665 |
|
|
step_count++;
|
| 666 |
|
|
} else if (hwif->io_base == 0x170) {
|
| 667 |
|
|
if((timings & 0x01) == 0)
|
| 668 |
|
|
continue;
|
| 669 |
|
|
hwif->chipset = ide_triton;
|
| 670 |
|
|
if (dma_enabled)
|
| 671 |
|
|
init_triton_dma(hwif, bmiba + 8);
|
| 672 |
|
|
if (set_via_timings(bus, fn, 0x30, 0x50))
|
| 673 |
|
|
goto quit;
|
| 674 |
|
|
step_count++;
|
| 675 |
|
|
} else {
|
| 676 |
|
|
continue;
|
| 677 |
|
|
}
|
| 678 |
|
|
} else if ((vendor == PCI_VENDOR_ID_PROMISE) ||
|
| 679 |
|
|
(vendor == PCI_VENDOR_ID_ARTOP)) {
|
| 680 |
|
|
/*
|
| 681 |
|
|
* This silly tmp = h routine allows an off-board ide-pci card to
|
| 682 |
|
|
* be booted as primary hwifgroup, provided that the onboard
|
| 683 |
|
|
* controllers are disabled. If they are active, then we wait our
|
| 684 |
|
|
* turn for hwif assignment.
|
| 685 |
|
|
*/
|
| 686 |
|
|
unsigned char irq = 0;
|
| 687 |
|
|
pcibios_read_config_byte (bus, fn, PCI_INTERRUPT_LINE, &irq);
|
| 688 |
|
|
if ((h == 0) || (h == 1)) {
|
| 689 |
|
|
tmp = h * 2;
|
| 690 |
|
|
} else {
|
| 691 |
|
|
tmp = (h - 2) * 2;
|
| 692 |
|
|
}
|
| 693 |
|
|
hwif->io_base = io[tmp];
|
| 694 |
|
|
hwif->ctl_port = io[tmp + 1] + 2;
|
| 695 |
|
|
hwif->irq = irq;
|
| 696 |
|
|
hwif->noprobe = 0;
|
| 697 |
|
|
|
| 698 |
|
|
if (vendor == PCI_VENDOR_ID_ARTOP) {
|
| 699 |
|
|
hwif->serialized = 1;
|
| 700 |
|
|
}
|
| 701 |
|
|
|
| 702 |
|
|
if (dma_enabled) {
|
| 703 |
|
|
if (!check_region(bmiba, 8)) {
|
| 704 |
|
|
hwif->chipset = ide_udma;
|
| 705 |
|
|
init_triton_dma(hwif, bmiba);
|
| 706 |
|
|
step_count++;
|
| 707 |
|
|
} else if (!check_region((bmiba + 0x08), 8)) {
|
| 708 |
|
|
if ((vendor == PCI_VENDOR_ID_PROMISE) &&
|
| 709 |
|
|
(!check_region(bmiba+16, 16))) {
|
| 710 |
|
|
request_region(bmiba+16, 16, "PDC20246");
|
| 711 |
|
|
}
|
| 712 |
|
|
hwif->chipset = ide_udma;
|
| 713 |
|
|
init_triton_dma(hwif, bmiba + 8);
|
| 714 |
|
|
step_count++;
|
| 715 |
|
|
} else {
|
| 716 |
|
|
continue;
|
| 717 |
|
|
}
|
| 718 |
|
|
}
|
| 719 |
|
|
}
|
| 720 |
|
|
}
|
| 721 |
|
|
|
| 722 |
|
|
quit: if (rc) printk("ide: pcibios access failed - %s\n", pcibios_strerror(rc));
|
| 723 |
|
|
}
|
