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[/] [or1k/] [tags/] [before_ORP/] [uclinux/] [uClinux-2.0.x/] [drivers/] [net/] [sk_g16.h] - Blame information for rev 1765

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1 199 simons 
/*-
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 *
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 * This software may be used and distributed according to the terms
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 * of the GNU Public License, incorporated herein by reference.
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 *
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 * Module         : sk_g16.h
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 * Version        : $Revision: 1.1.1.1 $
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 *
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 * Author         : M.Hipp (mhipp@student.uni-tuebingen.de)
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 * changes by     : Patrick J.D. Weichmann
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 *
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 * Date Created   : 94/05/25
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 *
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 * Description    : In here are all necessary definitions of
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 *                  the am7990 (LANCE) chip used for writing a
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 *                  network device driver which uses this chip
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 *
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 * $Log: not supported by cvs2svn $
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 * Revision 1.1.1.1  2001/07/02 17:58:22  simons
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 * Initial revision
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 *
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-*/
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#ifndef SK_G16_H
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#define SK_G16_H
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/*
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 *      Control and Status Register 0 (CSR0) bit definitions
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 *
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 * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write)
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 *
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 */
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#define CSR0_ERR        0x8000  /* Error summary (R) */
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#define CSR0_BABL       0x4000  /* Babble transmitter timeout error (RC) */
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#define CSR0_CERR       0x2000  /* Collision Error (RC) */
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#define CSR0_MISS       0x1000  /* Missed packet (RC) */
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#define CSR0_MERR       0x0800  /* Memory Error  (RC) */
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#define CSR0_RINT       0x0400  /* Receiver Interrupt (RC) */
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#define CSR0_TINT       0x0200  /* Transmit Interrupt (RC) */
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#define CSR0_IDON       0x0100  /* Initialization Done (RC) */
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#define CSR0_INTR       0x0080  /* Interrupt Flag (R) */
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#define CSR0_INEA       0x0040  /* Interrupt Enable (RW) */
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#define CSR0_RXON       0x0020  /* Receiver on (R) */
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#define CSR0_TXON       0x0010  /* Transmitter on (R) */
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#define CSR0_TDMD       0x0008  /* Transmit Demand (RS) */
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#define CSR0_STOP       0x0004  /* Stop (RS) */
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#define CSR0_STRT       0x0002  /* Start (RS) */
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#define CSR0_INIT       0x0001  /* Initialize (RS) */
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#define CSR0_CLRALL     0x7f00  /* mask for all clearable bits */
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/*
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 *    Control and Status Register 3 (CSR3) bit definitions
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 *
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 */
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#define CSR3_BSWAP      0x0004  /* Byte Swap (RW) */
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#define CSR3_ACON       0x0002  /* ALE Control (RW) */
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#define CSR3_BCON       0x0001  /* Byte Control (RW) */
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/*
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 *      Initialization Block Mode operation Bit Definitions.
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 */
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#define MODE_PROM       0x8000  /* Promiscuous Mode */
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#define MODE_INTL       0x0040  /* Internal Loopback */
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#define MODE_DRTY       0x0020  /* Disable Retry */
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#define MODE_COLL       0x0010  /* Force Collision */
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#define MODE_DTCR       0x0008  /* Disable Transmit CRC) */
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#define MODE_LOOP       0x0004  /* Loopback */
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#define MODE_DTX        0x0002  /* Disable the Transmitter */
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#define MODE_DRX        0x0001  /* Disable the Receiver */
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#define MODE_NORMAL     0x0000  /* Normal operation mode */
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/*
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 *      Receive message descriptor status bit definitions.
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 */
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#define RX_OWN          0x80    /* Owner bit 0 = host, 1 = lance */
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#define RX_ERR          0x40    /* Error Summary */
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#define RX_FRAM         0x20    /* Framing Error */
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#define RX_OFLO         0x10    /* Overflow Error */
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#define RX_CRC          0x08    /* CRC Error */
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#define RX_BUFF         0x04    /* Buffer Error */
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#define RX_STP          0x02    /* Start of Packet */
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#define RX_ENP          0x01    /* End of Packet */
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/*
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 *      Transmit message descriptor status bit definitions.
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 */
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#define TX_OWN          0x80    /* Owner bit 0 = host, 1 = lance */
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#define TX_ERR          0x40    /* Error Summary */
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#define TX_MORE         0x10    /* More the 1 retry needed to Xmit */
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#define TX_ONE          0x08    /* One retry needed to Xmit */
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#define TX_DEF          0x04    /* Deferred */
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#define TX_STP          0x02    /* Start of Packet */
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#define TX_ENP          0x01    /* End of Packet */
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/*
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 *      Transmit status (2) (valid if TX_ERR == 1)
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 */
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#define TX_BUFF         0x8000  /* Buffering error (no ENP) */
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#define TX_UFLO         0x4000  /* Underflow (late memory) */
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#define TX_LCOL         0x1000  /* Late collision */
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#define TX_LCAR         0x0400  /* Loss of Carrier */
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#define TX_RTRY         0x0200  /* Failed after 16 retransmissions  */
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#define TX_TDR          0x003f  /* Time-domain-reflectometer-value */
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/*
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 * Structures used for Communication with the LANCE
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 */
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/* LANCE Initialize Block */
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struct init_block
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{
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  unsigned short mode;     /* Mode Register */
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  unsigned char  paddr[6]; /* Physical Address (MAC) */
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  unsigned char  laddr[8]; /* Logical Filter Address (not used) */
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  unsigned int   rdrp;     /* Receive Descriptor Ring pointer */
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  unsigned int   tdrp;     /* Transmit Descriptor Ring pointer */
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};
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/* Receive Message Descriptor Entry */
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struct rmd
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{
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  union
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  {
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    unsigned long buffer;     /* Address of buffer */
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    struct
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    {
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      unsigned char unused[3];
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      unsigned volatile char status;   /* Status Bits */
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    } s;
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  } u;
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  volatile short blen;        /* Buffer Length (two's complement) */
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  unsigned short mlen;        /* Message Byte Count */
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};
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/* Transmit Message Descriptor Entry */
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struct tmd
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{
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  union
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  {
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    unsigned long  buffer;    /* Address of buffer */
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    struct
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    {
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      unsigned char unused[3];
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      unsigned volatile char status;   /* Status Bits */
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    } s;
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  } u;
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  unsigned short blen;             /* Buffer Length (two's complement) */
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  unsigned volatile short status2; /* Error Status Bits */
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};
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#endif /* End of SK_G16_H */

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