1 |
199 |
simons |
/**************************************************************************
|
2 |
|
|
* Initio A100 device driver for Linux.
|
3 |
|
|
*
|
4 |
|
|
* Copyright (c) 1994-1998 Initio Corporation
|
5 |
|
|
* All rights reserved.
|
6 |
|
|
*
|
7 |
|
|
* This program is free software; you can redistribute it and/or modify
|
8 |
|
|
* it under the terms of the GNU General Public License as published by
|
9 |
|
|
* the Free Software Foundation; either version 2, or (at your option)
|
10 |
|
|
* any later version.
|
11 |
|
|
*
|
12 |
|
|
* This program is distributed in the hope that it will be useful,
|
13 |
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
15 |
|
|
* GNU General Public License for more details.
|
16 |
|
|
*
|
17 |
|
|
* You should have received a copy of the GNU General Public License
|
18 |
|
|
* along with this program; see the file COPYING. If not, write to
|
19 |
|
|
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
|
20 |
|
|
*
|
21 |
|
|
* --------------------------------------------------------------------------
|
22 |
|
|
*
|
23 |
|
|
* Redistribution and use in source and binary forms, with or without
|
24 |
|
|
* modification, are permitted provided that the following conditions
|
25 |
|
|
* are met:
|
26 |
|
|
* 1. Redistributions of source code must retain the above copyright
|
27 |
|
|
* notice, this list of conditions, and the following disclaimer,
|
28 |
|
|
* without modification, immediately at the beginning of the file.
|
29 |
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
30 |
|
|
* notice, this list of conditions and the following disclaimer in the
|
31 |
|
|
* documentation and/or other materials provided with the distribution.
|
32 |
|
|
* 3. The name of the author may not be used to endorse or promote products
|
33 |
|
|
* derived from this software without specific prior written permission.
|
34 |
|
|
*
|
35 |
|
|
* Where this Software is combined with software released under the terms of
|
36 |
|
|
* the GNU Public License ("GPL") and the terms of the GPL would require the
|
37 |
|
|
* combined work to also be released under the terms of the GPL, the terms
|
38 |
|
|
* and conditions of this License will apply in addition to those of the
|
39 |
|
|
* GPL with the exception of any terms or conditions of this License that
|
40 |
|
|
* conflict with, or are expressly prohibited by, the GPL.
|
41 |
|
|
*
|
42 |
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
43 |
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
44 |
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
45 |
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
46 |
|
|
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
47 |
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
48 |
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
49 |
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
50 |
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
51 |
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
52 |
|
|
* SUCH DAMAGE.
|
53 |
|
|
*
|
54 |
|
|
**************************************************************************
|
55 |
|
|
*
|
56 |
|
|
* Module: inia100.h
|
57 |
|
|
* Description: INI-A100U2W LINUX device driver header
|
58 |
|
|
* Revision History:
|
59 |
|
|
* 06/18/98 HL, Initial Version 1.02
|
60 |
|
|
* 12/19/98 bv, v1.02a Use spinlocks for 2.1.95 and up.
|
61 |
|
|
**************************************************************************/
|
62 |
|
|
|
63 |
|
|
#define ULONG unsigned long
|
64 |
|
|
#define PVOID void *
|
65 |
|
|
#define USHORT unsigned short
|
66 |
|
|
#define UCHAR unsigned char
|
67 |
|
|
#define BYTE unsigned char
|
68 |
|
|
#define WORD unsigned short
|
69 |
|
|
#define DWORD unsigned long
|
70 |
|
|
#define UBYTE unsigned char
|
71 |
|
|
#define UWORD unsigned short
|
72 |
|
|
#define UDWORD unsigned long
|
73 |
|
|
#ifdef ALPHA
|
74 |
|
|
#define U32 unsigned int
|
75 |
|
|
#else
|
76 |
|
|
#define U32 unsigned long
|
77 |
|
|
#endif
|
78 |
|
|
|
79 |
|
|
#ifndef NULL
|
80 |
|
|
#define NULL 0 /* zero */
|
81 |
|
|
#endif
|
82 |
|
|
#ifndef TRUE
|
83 |
|
|
#define TRUE (1) /* boolean true */
|
84 |
|
|
#endif
|
85 |
|
|
#ifndef FALSE
|
86 |
|
|
#define FALSE (0) /* boolean false */
|
87 |
|
|
#endif
|
88 |
|
|
#ifndef FAILURE
|
89 |
|
|
#define FAILURE (-1)
|
90 |
|
|
#endif
|
91 |
|
|
#if 1
|
92 |
|
|
#define ORC_MAXQUEUE 245
|
93 |
|
|
#else
|
94 |
|
|
#define ORC_MAXQUEUE 25
|
95 |
|
|
#endif
|
96 |
|
|
|
97 |
|
|
#define TOTAL_SG_ENTRY 32
|
98 |
|
|
#define MAX_TARGETS 16
|
99 |
|
|
#define IMAX_CDB 15
|
100 |
|
|
#define SENSE_SIZE 14
|
101 |
|
|
#define MAX_SUPPORTED_ADAPTERS 4
|
102 |
|
|
#define SUCCESSFUL 0x00
|
103 |
|
|
|
104 |
|
|
#define I920_DEVICE_ID 0x0002 /* Initio's inic-950 product ID */
|
105 |
|
|
|
106 |
|
|
/************************************************************************/
|
107 |
|
|
/* Scatter-Gather Element Structure */
|
108 |
|
|
/************************************************************************/
|
109 |
|
|
typedef struct ORC_SG_Struc {
|
110 |
|
|
U32 SG_Ptr; /* Data Pointer */
|
111 |
|
|
U32 SG_Len; /* Data Length */
|
112 |
|
|
} ORC_SG;
|
113 |
|
|
|
114 |
|
|
typedef struct inia100_Adpt_Struc {
|
115 |
|
|
UWORD ADPT_BIOS; /* 0 */
|
116 |
|
|
UWORD ADPT_BASE; /* 1 */
|
117 |
|
|
UBYTE ADPT_Bus; /* 2 */
|
118 |
|
|
UBYTE ADPT_Device; /* 3 */
|
119 |
|
|
UBYTE ADPT_INTR; /* 4 */
|
120 |
|
|
} INIA100_ADPT_STRUCT;
|
121 |
|
|
|
122 |
|
|
|
123 |
|
|
/* SCSI related definition */
|
124 |
|
|
#define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
|
125 |
|
|
#define DISC_ALLOW 0xC0 /* Disconnect is allowed */
|
126 |
|
|
|
127 |
|
|
|
128 |
|
|
#define ORC_OFFSET_SCB 16
|
129 |
|
|
#define ORC_MAX_SCBS 250
|
130 |
|
|
#define MAX_CHANNELS 2
|
131 |
|
|
#define MAX_ESCB_ELE 64
|
132 |
|
|
#define TCF_DRV_255_63 0x0400
|
133 |
|
|
|
134 |
|
|
/********************************************************/
|
135 |
|
|
/* Orchid Configuration Register Set */
|
136 |
|
|
/********************************************************/
|
137 |
|
|
#define ORC_PVID 0x00 /* Vendor ID */
|
138 |
|
|
#define ORC_VENDOR_ID 0x1101 /* Orchid vendor ID */
|
139 |
|
|
#define ORC_PDID 0x02 /* Device ID */
|
140 |
|
|
#define ORC_DEVICE_ID 0x1060 /* Orchid device ID */
|
141 |
|
|
#define ORC_COMMAND 0x04 /* Command */
|
142 |
|
|
#define BUSMS 0x04 /* BUS MASTER Enable */
|
143 |
|
|
#define IOSPA 0x01 /* IO Space Enable */
|
144 |
|
|
#define ORC_STATUS 0x06 /* Status register */
|
145 |
|
|
#define ORC_REVISION 0x08 /* Revision number */
|
146 |
|
|
#define ORC_BASE 0x10 /* Base address */
|
147 |
|
|
#define ORC_BIOS 0x50 /* Expansion ROM base address */
|
148 |
|
|
#define ORC_INT_NUM 0x3C /* Interrupt line */
|
149 |
|
|
#define ORC_INT_PIN 0x3D /* Interrupt pin */
|
150 |
|
|
|
151 |
|
|
|
152 |
|
|
/********************************************************/
|
153 |
|
|
/* Orchid Host Command Set */
|
154 |
|
|
/********************************************************/
|
155 |
|
|
#define ORC_CMD_NOP 0x00 /* Host command - NOP */
|
156 |
|
|
#define ORC_CMD_VERSION 0x01 /* Host command - Get F/W version */
|
157 |
|
|
#define ORC_CMD_ECHO 0x02 /* Host command - ECHO */
|
158 |
|
|
#define ORC_CMD_SET_NVM 0x03 /* Host command - Set NVRAM */
|
159 |
|
|
#define ORC_CMD_GET_NVM 0x04 /* Host command - Get NVRAM */
|
160 |
|
|
#define ORC_CMD_GET_BUS_STATUS 0x05 /* Host command - Get SCSI bus status */
|
161 |
|
|
#define ORC_CMD_ABORT_SCB 0x06 /* Host command - Abort SCB */
|
162 |
|
|
#define ORC_CMD_ISSUE_SCB 0x07 /* Host command - Issue SCB */
|
163 |
|
|
|
164 |
|
|
/********************************************************/
|
165 |
|
|
/* Orchid Register Set */
|
166 |
|
|
/********************************************************/
|
167 |
|
|
#define ORC_GINTS 0xA0 /* Global Interrupt Status */
|
168 |
|
|
#define QINT 0x04 /* Reply Queue Interrupt */
|
169 |
|
|
#define ORC_GIMSK 0xA1 /* Global Interrupt MASK */
|
170 |
|
|
#define MQINT 0x04 /* Mask Reply Queue Interrupt */
|
171 |
|
|
#define ORC_GCFG 0xA2 /* Global Configure */
|
172 |
|
|
#define EEPRG 0x01 /* Enable EEPROM programming */
|
173 |
|
|
#define ORC_GSTAT 0xA3 /* Global status */
|
174 |
|
|
#define WIDEBUS 0x10 /* Wide SCSI Devices connected */
|
175 |
|
|
#define ORC_HDATA 0xA4 /* Host Data */
|
176 |
|
|
#define ORC_HCTRL 0xA5 /* Host Control */
|
177 |
|
|
#define SCSIRST 0x80 /* SCSI bus reset */
|
178 |
|
|
#define HDO 0x40 /* Host data out */
|
179 |
|
|
#define HOSTSTOP 0x02 /* Host stop RISC engine */
|
180 |
|
|
#define DEVRST 0x01 /* Device reset */
|
181 |
|
|
#define ORC_HSTUS 0xA6 /* Host Status */
|
182 |
|
|
#define HDI 0x02 /* Host data in */
|
183 |
|
|
#define RREADY 0x01 /* RISC engine is ready to receive */
|
184 |
|
|
#define ORC_NVRAM 0xA7 /* Nvram port address */
|
185 |
|
|
#define SE2CS 0x008
|
186 |
|
|
#define SE2CLK 0x004
|
187 |
|
|
#define SE2DO 0x002
|
188 |
|
|
#define SE2DI 0x001
|
189 |
|
|
#define ORC_PQUEUE 0xA8 /* Posting queue FIFO */
|
190 |
|
|
#define ORC_PQCNT 0xA9 /* Posting queue FIFO Cnt */
|
191 |
|
|
#define ORC_RQUEUE 0xAA /* Reply queue FIFO */
|
192 |
|
|
#define ORC_RQUEUECNT 0xAB /* Reply queue FIFO Cnt */
|
193 |
|
|
#define ORC_FWBASEADR 0xAC /* Firmware base address */
|
194 |
|
|
|
195 |
|
|
#define ORC_EBIOSADR0 0xB0 /* External Bios address */
|
196 |
|
|
#define ORC_EBIOSADR1 0xB1 /* External Bios address */
|
197 |
|
|
#define ORC_EBIOSADR2 0xB2 /* External Bios address */
|
198 |
|
|
#define ORC_EBIOSDATA 0xB3 /* External Bios address */
|
199 |
|
|
|
200 |
|
|
#define ORC_SCBSIZE 0xB7 /* SCB size register */
|
201 |
|
|
#define ORC_SCBBASE0 0xB8 /* SCB base address 0 */
|
202 |
|
|
#define ORC_SCBBASE1 0xBC /* SCB base address 1 */
|
203 |
|
|
|
204 |
|
|
#define ORC_RISCCTL 0xE0 /* RISC Control */
|
205 |
|
|
#define PRGMRST 0x002
|
206 |
|
|
#define DOWNLOAD 0x001
|
207 |
|
|
#define ORC_PRGMCTR0 0xE2 /* RISC program counter */
|
208 |
|
|
#define ORC_PRGMCTR1 0xE3 /* RISC program counter */
|
209 |
|
|
#define ORC_RISCRAM 0xEC /* RISC RAM data port 4 bytes */
|
210 |
|
|
|
211 |
|
|
typedef struct orc_extended_scb { /* Extended SCB */
|
212 |
|
|
ORC_SG ESCB_SGList[TOTAL_SG_ENTRY]; /*0 Start of SG list */
|
213 |
|
|
unsigned char *SCB_Srb; /*50 SRB Pointer */
|
214 |
|
|
// Scsi_Cmnd *SCB_Srb; /*50 SRB Pointer */
|
215 |
|
|
} ESCB;
|
216 |
|
|
|
217 |
|
|
/***********************************************************************
|
218 |
|
|
SCSI Control Block
|
219 |
|
|
************************************************************************/
|
220 |
|
|
typedef struct orc_scb { /* Scsi_Ctrl_Blk */
|
221 |
|
|
UBYTE SCB_Opcode; /*00 SCB command code&residual */
|
222 |
|
|
UBYTE SCB_Flags; /*01 SCB Flags */
|
223 |
|
|
UBYTE SCB_Target; /*02 Target Id */
|
224 |
|
|
UBYTE SCB_Lun; /*03 Lun */
|
225 |
|
|
U32 SCB_Reserved0; /*04 Reserved for ORCHID must 0 */
|
226 |
|
|
U32 SCB_XferLen; /*08 Data Transfer Length */
|
227 |
|
|
U32 SCB_Reserved1; /*0C Reserved for ORCHID must 0 */
|
228 |
|
|
U32 SCB_SGLen; /*10 SG list # * 8 */
|
229 |
|
|
U32 SCB_SGPAddr; /*14 SG List Buf physical Addr */
|
230 |
|
|
U32 SCB_SGPAddrHigh; /*18 SG Buffer high physical Addr */
|
231 |
|
|
UBYTE SCB_HaStat; /*1C Host Status */
|
232 |
|
|
UBYTE SCB_TaStat; /*1D Target Status */
|
233 |
|
|
UBYTE SCB_Status; /*1E SCB status */
|
234 |
|
|
UBYTE SCB_Link; /*1F Link pointer, default 0xFF */
|
235 |
|
|
UBYTE SCB_SenseLen; /*20 Sense Allocation Length */
|
236 |
|
|
UBYTE SCB_CDBLen; /*21 CDB Length */
|
237 |
|
|
UBYTE SCB_Ident; /*22 Identify */
|
238 |
|
|
UBYTE SCB_TagMsg; /*23 Tag Message */
|
239 |
|
|
UBYTE SCB_CDB[IMAX_CDB]; /*24 SCSI CDBs */
|
240 |
|
|
UBYTE SCB_ScbIdx; /*3C Index for this ORCSCB */
|
241 |
|
|
U32 SCB_SensePAddr; /*34 Sense Buffer physical Addr */
|
242 |
|
|
|
243 |
|
|
ESCB *SCB_EScb; /*38 Extended SCB Pointer */
|
244 |
|
|
#ifndef ALPHA
|
245 |
|
|
UBYTE SCB_Reserved2[4]; /*3E Reserved for Driver use */
|
246 |
|
|
#endif
|
247 |
|
|
} ORC_SCB;
|
248 |
|
|
|
249 |
|
|
/* Opcodes of ORCSCB_Opcode */
|
250 |
|
|
#define ORC_EXECSCSI 0x00 /* SCSI initiator command with residual */
|
251 |
|
|
#define ORC_BUSDEVRST 0x01 /* SCSI Bus Device Reset */
|
252 |
|
|
|
253 |
|
|
/* Status of ORCSCB_Status */
|
254 |
|
|
#define SCB_COMPLETE 0x00 /* SCB request completed */
|
255 |
|
|
#define SCB_POST 0x01 /* SCB is posted by the HOST */
|
256 |
|
|
|
257 |
|
|
/* Bit Definition for ORCSCB_Flags */
|
258 |
|
|
#define SCF_DISINT 0x01 /* Disable HOST interrupt */
|
259 |
|
|
#define SCF_DIR 0x18 /* Direction bits */
|
260 |
|
|
#define SCF_NO_DCHK 0x00 /* Direction determined by SCSI */
|
261 |
|
|
#define SCF_DIN 0x08 /* From Target to Initiator */
|
262 |
|
|
#define SCF_DOUT 0x10 /* From Initiator to Target */
|
263 |
|
|
#define SCF_NO_XF 0x18 /* No data transfer */
|
264 |
|
|
#define SCF_POLL 0x40
|
265 |
|
|
|
266 |
|
|
/* Error Codes for ORCSCB_HaStat */
|
267 |
|
|
#define HOST_SEL_TOUT 0x11
|
268 |
|
|
#define HOST_DO_DU 0x12
|
269 |
|
|
#define HOST_BUS_FREE 0x13
|
270 |
|
|
#define HOST_BAD_PHAS 0x14
|
271 |
|
|
#define HOST_INV_CMD 0x16
|
272 |
|
|
#define HOST_SCSI_RST 0x1B
|
273 |
|
|
#define HOST_DEV_RST 0x1C
|
274 |
|
|
|
275 |
|
|
|
276 |
|
|
/* Error Codes for ORCSCB_TaStat */
|
277 |
|
|
#define TARGET_CHK_COND 0x02
|
278 |
|
|
#define TARGET_BUSY 0x08
|
279 |
|
|
#define TARGET_TAG_FULL 0x28
|
280 |
|
|
|
281 |
|
|
|
282 |
|
|
/* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
|
283 |
|
|
#define MSG_STAG 0x20
|
284 |
|
|
#define MSG_HTAG 0x21
|
285 |
|
|
#define MSG_OTAG 0x22
|
286 |
|
|
|
287 |
|
|
#define MSG_IGNOREWIDE 0x23
|
288 |
|
|
|
289 |
|
|
#define MSG_IDENT 0x80
|
290 |
|
|
#define MSG_DISC 0x40 /* Disconnect allowed */
|
291 |
|
|
|
292 |
|
|
|
293 |
|
|
/* SCSI MESSAGE */
|
294 |
|
|
#define MSG_EXTEND 0x01
|
295 |
|
|
#define MSG_SDP 0x02
|
296 |
|
|
#define MSG_ABORT 0x06
|
297 |
|
|
#define MSG_REJ 0x07
|
298 |
|
|
#define MSG_NOP 0x08
|
299 |
|
|
#define MSG_PARITY 0x09
|
300 |
|
|
#define MSG_DEVRST 0x0C
|
301 |
|
|
#define MSG_STAG 0x20
|
302 |
|
|
|
303 |
|
|
/***********************************************************************
|
304 |
|
|
Target Device Control Structure
|
305 |
|
|
**********************************************************************/
|
306 |
|
|
|
307 |
|
|
typedef struct ORC_Tar_Ctrl_Struc {
|
308 |
|
|
UBYTE TCS_DrvDASD; /* 6 */
|
309 |
|
|
UBYTE TCS_DrvSCSI; /* 7 */
|
310 |
|
|
UBYTE TCS_DrvHead; /* 8 */
|
311 |
|
|
UWORD TCS_DrvFlags; /* 4 */
|
312 |
|
|
UBYTE TCS_DrvSector; /* 7 */
|
313 |
|
|
} ORC_TCS, *PORC_TCS;
|
314 |
|
|
|
315 |
|
|
/* Bit Definition for TCF_DrvFlags */
|
316 |
|
|
#define TCS_DF_NODASD_SUPT 0x20 /* Suppress OS/2 DASD Mgr support */
|
317 |
|
|
#define TCS_DF_NOSCSI_SUPT 0x40 /* Suppress OS/2 SCSI Mgr support */
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
/***********************************************************************
|
321 |
|
|
Host Adapter Control Structure
|
322 |
|
|
************************************************************************/
|
323 |
|
|
typedef struct ORC_Ha_Ctrl_Struc {
|
324 |
|
|
USHORT HCS_Base; /* 00 */
|
325 |
|
|
UBYTE HCS_Index; /* 02 */
|
326 |
|
|
UBYTE HCS_Intr; /* 04 */
|
327 |
|
|
UBYTE HCS_SCSI_ID; /* 06 H/A SCSI ID */
|
328 |
|
|
UBYTE HCS_BIOS; /* 07 BIOS configuration */
|
329 |
|
|
|
330 |
|
|
UBYTE HCS_Flags; /* 0B */
|
331 |
|
|
UBYTE HCS_HAConfig1; /* 1B SCSI0MAXTags */
|
332 |
|
|
UBYTE HCS_MaxTar; /* 1B SCSI0MAXTags */
|
333 |
|
|
|
334 |
|
|
USHORT HCS_Units; /* Number of units this adapter */
|
335 |
|
|
USHORT HCS_AFlags; /* Adapter info. defined flags */
|
336 |
|
|
ULONG HCS_Timeout; /* Adapter timeout value */
|
337 |
|
|
PVOID HCS_virScbArray; /* 28 Virtual Pointer to SCB array */
|
338 |
|
|
U32 HCS_physScbArray; /* Scb Physical address */
|
339 |
|
|
PVOID HCS_virEscbArray; /* Virtual pointer to ESCB Scatter list */
|
340 |
|
|
U32 HCS_physEscbArray; /* scatter list Physical address */
|
341 |
|
|
UBYTE TargetFlag[16]; /* 30 target configuration, TCF_EN_TAG */
|
342 |
|
|
UBYTE MaximumTags[16]; /* 40 ORC_MAX_SCBS */
|
343 |
|
|
UBYTE ActiveTags[16][16]; /* 50 */
|
344 |
|
|
ORC_TCS HCS_Tcs[16]; /* 28 */
|
345 |
|
|
U32 BitAllocFlag[MAX_CHANNELS][8]; /* Max STB is 256, So 256/32 */
|
346 |
|
|
#if LINUX_VERSION_CODE >= CVT_LINUX_VERSION(2,1,95)
|
347 |
|
|
spinlock_t BitAllocFlagLock;
|
348 |
|
|
#endif
|
349 |
|
|
ULONG pSRB_head;
|
350 |
|
|
ULONG pSRB_tail;
|
351 |
|
|
#if LINUX_VERSION_CODE >= CVT_LINUX_VERSION(2,1,95)
|
352 |
|
|
spinlock_t pSRB_lock;
|
353 |
|
|
#endif
|
354 |
|
|
} ORC_HCS;
|
355 |
|
|
|
356 |
|
|
/* Bit Definition for HCS_Flags */
|
357 |
|
|
|
358 |
|
|
#define HCF_SCSI_RESET 0x01 /* SCSI BUS RESET */
|
359 |
|
|
#define HCF_PARITY 0x02 /* parity card */
|
360 |
|
|
#define HCF_LVDS 0x10 /* parity card */
|
361 |
|
|
|
362 |
|
|
/* Bit Definition for TargetFlag */
|
363 |
|
|
|
364 |
|
|
#define TCF_EN_255 0x08
|
365 |
|
|
#define TCF_EN_TAG 0x10
|
366 |
|
|
#define TCF_BUSY 0x20
|
367 |
|
|
#define TCF_DISCONNECT 0x40
|
368 |
|
|
#define TCF_SPIN_UP 0x80
|
369 |
|
|
|
370 |
|
|
/* Bit Definition for HCS_AFlags */
|
371 |
|
|
#define HCS_AF_IGNORE 0x01 /* Adapter ignore */
|
372 |
|
|
#define HCS_AF_DISABLE_RESET 0x10 /* Adapter disable reset */
|
373 |
|
|
#define HCS_AF_DISABLE_ADPT 0x80 /* Adapter disable */
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
/*---------------------------------------*/
|
377 |
|
|
/* TimeOut for RESET to complete (30s) */
|
378 |
|
|
/* */
|
379 |
|
|
/* After a RESET the drive is checked */
|
380 |
|
|
/* every 200ms. */
|
381 |
|
|
/*---------------------------------------*/
|
382 |
|
|
#define DELAYED_RESET_MAX (30*1000L)
|
383 |
|
|
#define DELAYED_RESET_INTERVAL 200L
|
384 |
|
|
|
385 |
|
|
/*----------------------------------------------*/
|
386 |
|
|
/* TimeOut for IRQ from last interrupt (5s) */
|
387 |
|
|
/*----------------------------------------------*/
|
388 |
|
|
#define IRQ_TIMEOUT_INTERVAL (5*1000L)
|
389 |
|
|
|
390 |
|
|
/*----------------------------------------------*/
|
391 |
|
|
/* Retry Delay interval (200ms) */
|
392 |
|
|
/*----------------------------------------------*/
|
393 |
|
|
#define DELAYED_RETRY_INTERVAL 200L
|
394 |
|
|
|
395 |
|
|
#define INQUIRY_SIZE 36
|
396 |
|
|
#define CAPACITY_SIZE 8
|
397 |
|
|
#define DEFAULT_SENSE_LEN 14
|
398 |
|
|
|
399 |
|
|
#define DEVICE_NOT_FOUND 0x86
|
400 |
|
|
|
401 |
|
|
/*----------------------------------------------*/
|
402 |
|
|
/* Definition for PCI device */
|
403 |
|
|
/*----------------------------------------------*/
|
404 |
|
|
#define MAX_PCI_DEVICES 21
|
405 |
|
|
#define MAX_PCI_BUSES 8
|
406 |
|
|
|
407 |
|
|
typedef struct Adpt_Struc {
|
408 |
|
|
USHORT ADPT_BIOS; /* 0 */
|
409 |
|
|
UBYTE ADPT_BASE; /* 1 */
|
410 |
|
|
UBYTE ADPT_Bus; /* 2 */
|
411 |
|
|
UBYTE ADPT_Device; /* 3 */
|
412 |
|
|
UBYTE ADPT_Reserved[3];
|
413 |
|
|
} JACS, *PJACS;
|
414 |
|
|
|
415 |
|
|
typedef struct _NVRAM {
|
416 |
|
|
/*----------header ---------------*/
|
417 |
|
|
UCHAR SubVendorID0; /* 00 - Sub Vendor ID */
|
418 |
|
|
UCHAR SubVendorID1; /* 00 - Sub Vendor ID */
|
419 |
|
|
UCHAR SubSysID0; /* 02 - Sub System ID */
|
420 |
|
|
UCHAR SubSysID1; /* 02 - Sub System ID */
|
421 |
|
|
UCHAR SubClass; /* 04 - Sub Class */
|
422 |
|
|
UCHAR VendorID0; /* 05 - Vendor ID */
|
423 |
|
|
UCHAR VendorID1; /* 05 - Vendor ID */
|
424 |
|
|
UCHAR DeviceID0; /* 07 - Device ID */
|
425 |
|
|
UCHAR DeviceID1; /* 07 - Device ID */
|
426 |
|
|
UCHAR Reserved0[2]; /* 09 - Reserved */
|
427 |
|
|
UCHAR Revision; /* 0B - Revision of data structure */
|
428 |
|
|
/* ----Host Adapter Structure ---- */
|
429 |
|
|
UCHAR NumOfCh; /* 0C - Number of SCSI channel */
|
430 |
|
|
UCHAR BIOSConfig1; /* 0D - BIOS configuration 1 */
|
431 |
|
|
UCHAR BIOSConfig2; /* 0E - BIOS boot channel&target ID */
|
432 |
|
|
UCHAR BIOSConfig3; /* 0F - BIOS configuration 3 */
|
433 |
|
|
/* ----SCSI channel Structure ---- */
|
434 |
|
|
/* from "CTRL-I SCSI Host Adapter SetUp menu " */
|
435 |
|
|
UCHAR SCSI0Id; /* 10 - Channel 0 SCSI ID */
|
436 |
|
|
UCHAR SCSI0Config; /* 11 - Channel 0 SCSI configuration */
|
437 |
|
|
UCHAR SCSI0MaxTags; /* 12 - Channel 0 Maximum tags */
|
438 |
|
|
UCHAR SCSI0ResetTime; /* 13 - Channel 0 Reset recovering time */
|
439 |
|
|
UCHAR ReservedforChannel0[2]; /* 14 - Reserved */
|
440 |
|
|
|
441 |
|
|
/* ----SCSI target Structure ---- */
|
442 |
|
|
/* from "CTRL-I SCSI device SetUp menu " */
|
443 |
|
|
UCHAR Target00Config; /* 16 - Channel 0 Target 0 config */
|
444 |
|
|
UCHAR Target01Config; /* 17 - Channel 0 Target 1 config */
|
445 |
|
|
UCHAR Target02Config; /* 18 - Channel 0 Target 2 config */
|
446 |
|
|
UCHAR Target03Config; /* 19 - Channel 0 Target 3 config */
|
447 |
|
|
UCHAR Target04Config; /* 1A - Channel 0 Target 4 config */
|
448 |
|
|
UCHAR Target05Config; /* 1B - Channel 0 Target 5 config */
|
449 |
|
|
UCHAR Target06Config; /* 1C - Channel 0 Target 6 config */
|
450 |
|
|
UCHAR Target07Config; /* 1D - Channel 0 Target 7 config */
|
451 |
|
|
UCHAR Target08Config; /* 1E - Channel 0 Target 8 config */
|
452 |
|
|
UCHAR Target09Config; /* 1F - Channel 0 Target 9 config */
|
453 |
|
|
UCHAR Target0AConfig; /* 20 - Channel 0 Target A config */
|
454 |
|
|
UCHAR Target0BConfig; /* 21 - Channel 0 Target B config */
|
455 |
|
|
UCHAR Target0CConfig; /* 22 - Channel 0 Target C config */
|
456 |
|
|
UCHAR Target0DConfig; /* 23 - Channel 0 Target D config */
|
457 |
|
|
UCHAR Target0EConfig; /* 24 - Channel 0 Target E config */
|
458 |
|
|
UCHAR Target0FConfig; /* 25 - Channel 0 Target F config */
|
459 |
|
|
|
460 |
|
|
UCHAR SCSI1Id; /* 26 - Channel 1 SCSI ID */
|
461 |
|
|
UCHAR SCSI1Config; /* 27 - Channel 1 SCSI configuration */
|
462 |
|
|
UCHAR SCSI1MaxTags; /* 28 - Channel 1 Maximum tags */
|
463 |
|
|
UCHAR SCSI1ResetTime; /* 29 - Channel 1 Reset recovering time */
|
464 |
|
|
UCHAR ReservedforChannel1[2]; /* 2A - Reserved */
|
465 |
|
|
|
466 |
|
|
/* ----SCSI target Structure ---- */
|
467 |
|
|
/* from "CTRL-I SCSI device SetUp menu " */
|
468 |
|
|
UCHAR Target10Config; /* 2C - Channel 1 Target 0 config */
|
469 |
|
|
UCHAR Target11Config; /* 2D - Channel 1 Target 1 config */
|
470 |
|
|
UCHAR Target12Config; /* 2E - Channel 1 Target 2 config */
|
471 |
|
|
UCHAR Target13Config; /* 2F - Channel 1 Target 3 config */
|
472 |
|
|
UCHAR Target14Config; /* 30 - Channel 1 Target 4 config */
|
473 |
|
|
UCHAR Target15Config; /* 31 - Channel 1 Target 5 config */
|
474 |
|
|
UCHAR Target16Config; /* 32 - Channel 1 Target 6 config */
|
475 |
|
|
UCHAR Target17Config; /* 33 - Channel 1 Target 7 config */
|
476 |
|
|
UCHAR Target18Config; /* 34 - Channel 1 Target 8 config */
|
477 |
|
|
UCHAR Target19Config; /* 35 - Channel 1 Target 9 config */
|
478 |
|
|
UCHAR Target1AConfig; /* 36 - Channel 1 Target A config */
|
479 |
|
|
UCHAR Target1BConfig; /* 37 - Channel 1 Target B config */
|
480 |
|
|
UCHAR Target1CConfig; /* 38 - Channel 1 Target C config */
|
481 |
|
|
UCHAR Target1DConfig; /* 39 - Channel 1 Target D config */
|
482 |
|
|
UCHAR Target1EConfig; /* 3A - Channel 1 Target E config */
|
483 |
|
|
UCHAR Target1FConfig; /* 3B - Channel 1 Target F config */
|
484 |
|
|
UCHAR reserved[3]; /* 3C - Reserved */
|
485 |
|
|
/* ---------- CheckSum ---------- */
|
486 |
|
|
UCHAR CheckSum; /* 3F - Checksum of NVRam */
|
487 |
|
|
} NVRAM, *PNVRAM;
|
488 |
|
|
|
489 |
|
|
/* Bios Configuration for nvram->BIOSConfig1 */
|
490 |
|
|
#define NBC_BIOSENABLE 0x01 /* BIOS enable */
|
491 |
|
|
#define NBC_CDROM 0x02 /* Support bootable CDROM */
|
492 |
|
|
#define NBC_REMOVABLE 0x04 /* Support removable drive */
|
493 |
|
|
|
494 |
|
|
/* Bios Configuration for nvram->BIOSConfig2 */
|
495 |
|
|
#define NBB_TARGET_MASK 0x0F /* Boot SCSI target ID number */
|
496 |
|
|
#define NBB_CHANL_MASK 0xF0 /* Boot SCSI channel number */
|
497 |
|
|
|
498 |
|
|
/* Bit definition for nvram->SCSIConfig */
|
499 |
|
|
#define NCC_BUSRESET 0x01 /* Reset SCSI bus at power up */
|
500 |
|
|
#define NCC_PARITYCHK 0x02 /* SCSI parity enable */
|
501 |
|
|
#define NCC_LVDS 0x10 /* Enable LVDS */
|
502 |
|
|
#define NCC_ACTTERM1 0x20 /* Enable active terminator 1 */
|
503 |
|
|
#define NCC_ACTTERM2 0x40 /* Enable active terminator 2 */
|
504 |
|
|
#define NCC_AUTOTERM 0x80 /* Enable auto termination */
|
505 |
|
|
|
506 |
|
|
/* Bit definition for nvram->TargetxConfig */
|
507 |
|
|
#define NTC_PERIOD 0x07 /* Maximum Sync. Speed */
|
508 |
|
|
#define NTC_1GIGA 0x08 /* 255 head / 63 sectors (64/32) */
|
509 |
|
|
#define NTC_NO_SYNC 0x10 /* NO SYNC. NEGO */
|
510 |
|
|
#define NTC_NO_WIDESYNC 0x20 /* NO WIDE SYNC. NEGO */
|
511 |
|
|
#define NTC_DISC_ENABLE 0x40 /* Enable SCSI disconnect */
|
512 |
|
|
#define NTC_SPINUP 0x80 /* Start disk drive */
|
513 |
|
|
|
514 |
|
|
/* Default NVRam values */
|
515 |
|
|
#define NBC_DEFAULT (NBC_ENABLE)
|
516 |
|
|
#define NCC_DEFAULT (NCC_BUSRESET | NCC_AUTOTERM | NCC_PARITYCHK)
|
517 |
|
|
#define NCC_MAX_TAGS 0x20 /* Maximum tags per target */
|
518 |
|
|
#define NCC_RESET_TIME 0x0A /* SCSI RESET recovering time */
|
519 |
|
|
#define NTC_DEFAULT (NTC_1GIGA | NTC_NO_WIDESYNC | NTC_DISC_ENABLE)
|
520 |
|
|
|
521 |
|
|
typedef union { /* Union define for mechanism 1 */
|
522 |
|
|
struct {
|
523 |
|
|
unsigned char RegNum;
|
524 |
|
|
unsigned char FcnNum:3;
|
525 |
|
|
unsigned char DeviceNum:5;
|
526 |
|
|
unsigned char BusNum;
|
527 |
|
|
unsigned char Reserved:7;
|
528 |
|
|
unsigned char Enable:1;
|
529 |
|
|
} sConfigAdr;
|
530 |
|
|
unsigned long lConfigAdr;
|
531 |
|
|
} CONFIG_ADR;
|
532 |
|
|
|
533 |
|
|
typedef union { /* Union define for mechanism 2 */
|
534 |
|
|
struct {
|
535 |
|
|
unsigned char RegNum;
|
536 |
|
|
unsigned char DeviceNum;
|
537 |
|
|
unsigned short Reserved;
|
538 |
|
|
} sHostAdr;
|
539 |
|
|
unsigned long lHostAdr;
|
540 |
|
|
} HOST_ADR;
|
541 |
|
|
|
542 |
|
|
#define ORC_RD(x,y) (UCHAR)(inb( (int)((ULONG)((ULONG)x+(UCHAR)y)) ))
|
543 |
|
|
#define ORC_RDLONG(x,y) (long)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) ))
|
544 |
|
|
|
545 |
|
|
#define ORC_WR( adr,data) outb( (UCHAR)(data), (int)(adr))
|
546 |
|
|
#define ORC_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr))
|
547 |
|
|
#define ORC_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr))
|
548 |
|
|
|
549 |
|
|
|
550 |
|
|
#define SCSI_ABORT_SNOOZE 0
|
551 |
|
|
#define SCSI_ABORT_SUCCESS 1
|
552 |
|
|
#define SCSI_ABORT_PENDING 2
|
553 |
|
|
#define SCSI_ABORT_BUSY 3
|
554 |
|
|
#define SCSI_ABORT_NOT_RUNNING 4
|
555 |
|
|
#define SCSI_ABORT_ERROR 5
|
556 |
|
|
|
557 |
|
|
#define SCSI_RESET_SNOOZE 0
|
558 |
|
|
#define SCSI_RESET_PUNT 1
|
559 |
|
|
#define SCSI_RESET_SUCCESS 2
|
560 |
|
|
#define SCSI_RESET_PENDING 3
|
561 |
|
|
#define SCSI_RESET_WAKEUP 4
|
562 |
|
|
#define SCSI_RESET_NOT_RUNNING 5
|
563 |
|
|
#define SCSI_RESET_ERROR 6
|
564 |
|
|
|
565 |
|
|
#define SCSI_RESET_SYNCHRONOUS 0x01
|
566 |
|
|
#define SCSI_RESET_ASYNCHRONOUS 0x02
|
567 |
|
|
#define SCSI_RESET_SUGGEST_BUS_RESET 0x04
|
568 |
|
|
#define SCSI_RESET_SUGGEST_HOST_RESET 0x08
|
569 |
|
|
|
570 |
|
|
#define SCSI_RESET_BUS_RESET 0x100
|
571 |
|
|
#define SCSI_RESET_HOST_RESET 0x200
|
572 |
|
|
#define SCSI_RESET_ACTION 0xff
|