OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [before_ORP/] [uclinux/] [uClinux-2.0.x/] [include/] [asm-i960/] [i960jx.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 199 simons
#ifndef _I960JX_H
2
#define _I960JX_H
3
 
4
#include <asm/i960.h>
5
/* Default Logical Memory Configuration Register */
6
#define DLMCON  0xFF008100
7
 
8
/* Logical Memory Address/Mask Registers */
9
#define LMADR0  0xFF008108
10
#define LMMR0   0xFF00810C
11
#define LMADR1  0xFF008110
12
#define LMMR1   0xFF008114
13
 
14
/* Instruction Breakpoint Registers */
15
#define IPB0    0xFF008400
16
#define IPB1    0xFF008404
17
 
18
/* Data Address Breakpoint Registers */
19
#define DAB0    0xFF008420
20
#define DAB1    0xFF008424
21
 
22
/* Breakpoint Control Register */
23
#define BPCON   0xFF008440
24
 
25
/* Interrupt Mask - IMSK and Interrupt Pending Registers - -IPND */
26
#define IPND    0xFF008500
27
#define IMSK    0xFF008504
28
 
29
/* Interrupt Control Register */
30
#define ICON    0xFF008510
31
 
32
/* Interrupt Mapping Registers */
33
#define IMAP0   0xFF008520
34
#define IMAP1   0xFF008524
35
#define IMAP2   0xFF008528
36
 
37
/* Physical Memory Control Registers */
38
#define PMCON0_1        0xFF008600
39
#define PMCON2_3        0xFF008608
40
#define PMCON4_5        0xFF008610
41
#define PMCON6_7        0xFF008618
42
#define PMCON8_9        0xFF008620
43
#define PMCON10_11      0xFF008628
44
#define PMCON12_13      0xFF008630
45
#define PMCON14_15      0xFF008638
46
 
47
/* Bus Control Register */
48
#define BCON    0xFF0086FC
49
 
50
/* Initial PRCB address; might be changed by calls to sysctl */
51
#define INITIAL_PRCB    0xFF008700
52
 
53
#ifndef __ASSEMBLY__
54
/* PRCB */
55
typedef struct {
56
        void*   pr_fault_tab;           /* fault handlers */
57
        void*   pr_ctl_tab;             /* control table */
58
        reg_t   pr_acreg;               /* AC reg initial image */
59
        reg_t   pr_fault_cw;            /* fault config word */
60
        itab_t* pr_intr_tab;            /* interrupt handlers */
61
        void*   pr_syscall_tab;         /* system calls */
62
        void*   pr_reserved;            /* unused */
63
        void*   pr_intr_stack;          /* interrupt stack */
64
        reg_t   pr_icache_cw;           /* icache config word */
65
        reg_t   pr_regcache_cw;         /* register cache config word */
66
} prcb_t;
67
#endif /* __ASSEMBLY__ */
68
 
69
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.