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markom |
/* CPU family header for i960base.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef CPU_I960BASE_H
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#define CPU_I960BASE_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 1
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* program counter */
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USI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) (CPU (h_pc) = (x))
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/* general registers */
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SI h_gr[32];
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#define GET_H_GR(a1) CPU (h_gr)[a1]
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#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
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/* condition code */
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SI h_cc;
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#define GET_H_CC() CPU (h_cc)
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#define SET_H_CC(x) (CPU (h_cc) = (x))
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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} I960BASE_CPU_DATA;
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/* Cover fns for register access. */
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USI i960base_h_pc_get (SIM_CPU *);
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void i960base_h_pc_set (SIM_CPU *, USI);
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SI i960base_h_gr_get (SIM_CPU *, UINT);
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void i960base_h_gr_set (SIM_CPU *, UINT, SI);
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SI i960base_h_cc_get (SIM_CPU *);
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void i960base_h_cc_set (SIM_CPU *, SI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN i960base_fetch_register;
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extern CPUREG_STORE_FN i960base_store_register;
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typedef struct {
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int empty;
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} MODEL_I960KA_DATA;
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typedef struct {
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int empty;
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} MODEL_I960CA_DATA;
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/* Instruction argument buffer. */
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union sem_fields {
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struct { /* no operands */
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int empty;
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} fmt_empty;
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struct { /* */
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IADDR i_ctrl_disp;
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} sfmt_bno;
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struct { /* */
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SI* i_br_src1;
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unsigned char out_br_src1;
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} sfmt_testno_reg;
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struct { /* */
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IADDR i_br_disp;
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SI* i_br_src2;
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UINT f_br_src1;
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unsigned char in_br_src2;
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} sfmt_cmpobe_lit;
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struct { /* */
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IADDR i_br_disp;
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SI* i_br_src1;
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SI* i_br_src2;
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unsigned char in_br_src1;
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unsigned char in_br_src2;
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} sfmt_cmpobe_reg;
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struct { /* */
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SI* i_dst;
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UINT f_src1;
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UINT f_src2;
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UINT f_srcdst;
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unsigned char out_dst;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
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} sfmt_emul3;
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struct { /* */
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SI* i_dst;
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SI* i_src1;
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UINT f_src2;
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UINT f_srcdst;
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unsigned char in_src1;
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unsigned char out_dst;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
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} sfmt_emul2;
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struct { /* */
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SI* i_dst;
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SI* i_src2;
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UINT f_src1;
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UINT f_srcdst;
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unsigned char in_src2;
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unsigned char out_dst;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
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} sfmt_emul1;
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struct { /* */
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SI* i_dst;
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SI* i_src1;
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SI* i_src2;
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UINT f_srcdst;
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unsigned char in_src1;
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unsigned char in_src2;
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unsigned char out_dst;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
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} sfmt_emul;
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struct { /* */
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SI* i_abase;
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SI* i_st_src;
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UINT f_offset;
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UINT f_srcdst;
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unsigned char in_abase;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_1;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_2;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_3;
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unsigned char in_st_src;
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} sfmt_stq_indirect_offset;
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struct { /* */
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SI* i_abase;
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SI* i_dst;
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UINT f_offset;
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UINT f_srcdst;
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unsigned char in_abase;
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unsigned char out_dst;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
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} sfmt_ldq_indirect_offset;
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struct { /* */
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SI* i_abase;
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SI* i_index;
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SI* i_st_src;
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UINT f_optdisp;
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UINT f_scale;
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UINT f_srcdst;
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unsigned char in_abase;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_1;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_2;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_3;
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unsigned char in_index;
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unsigned char in_st_src;
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} sfmt_stq_indirect_index_disp;
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struct { /* */
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SI* i_abase;
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SI* i_dst;
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SI* i_index;
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UINT f_optdisp;
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UINT f_scale;
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UINT f_srcdst;
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unsigned char in_abase;
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unsigned char in_index;
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unsigned char out_dst;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
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} sfmt_ldq_indirect_index_disp;
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struct { /* */
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SI* i_dst;
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SI* i_src1;
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UINT f_src1;
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UINT f_srcdst;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_1;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_2;
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unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_3;
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unsigned char in_src1;
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unsigned char out_dst;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
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unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
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} sfmt_movq;
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struct { /* */
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UINT f_optdisp;
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unsigned char in_h_gr_0;
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unsigned char in_h_gr_1;
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unsigned char in_h_gr_10;
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unsigned char in_h_gr_11;
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unsigned char in_h_gr_12;
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unsigned char in_h_gr_13;
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unsigned char in_h_gr_14;
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unsigned char in_h_gr_15;
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unsigned char in_h_gr_2;
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unsigned char in_h_gr_3;
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unsigned char in_h_gr_31;
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unsigned char in_h_gr_4;
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unsigned char in_h_gr_5;
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unsigned char in_h_gr_6;
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unsigned char in_h_gr_7;
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unsigned char in_h_gr_8;
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unsigned char in_h_gr_9;
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unsigned char out_h_gr_0;
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unsigned char out_h_gr_1;
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unsigned char out_h_gr_10;
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unsigned char out_h_gr_11;
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unsigned char out_h_gr_12;
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unsigned char out_h_gr_13;
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unsigned char out_h_gr_14;
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unsigned char out_h_gr_15;
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unsigned char out_h_gr_2;
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unsigned char out_h_gr_3;
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unsigned char out_h_gr_31;
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unsigned char out_h_gr_4;
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unsigned char out_h_gr_5;
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unsigned char out_h_gr_6;
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unsigned char out_h_gr_7;
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unsigned char out_h_gr_8;
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unsigned char out_h_gr_9;
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} sfmt_callx_disp;
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struct { /* */
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SI* i_abase;
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UINT f_offset;
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unsigned char in_abase;
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unsigned char in_h_gr_0;
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unsigned char in_h_gr_1;
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unsigned char in_h_gr_10;
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unsigned char in_h_gr_11;
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unsigned char in_h_gr_12;
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unsigned char in_h_gr_13;
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unsigned char in_h_gr_14;
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unsigned char in_h_gr_15;
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unsigned char in_h_gr_2;
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unsigned char in_h_gr_3;
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unsigned char in_h_gr_31;
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unsigned char in_h_gr_4;
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unsigned char in_h_gr_5;
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unsigned char in_h_gr_6;
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unsigned char in_h_gr_7;
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unsigned char in_h_gr_8;
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unsigned char in_h_gr_9;
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unsigned char out_h_gr_0;
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unsigned char out_h_gr_1;
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unsigned char out_h_gr_10;
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unsigned char out_h_gr_11;
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unsigned char out_h_gr_12;
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unsigned char out_h_gr_13;
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| 265 |
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unsigned char out_h_gr_14;
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| 266 |
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unsigned char out_h_gr_15;
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| 267 |
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unsigned char out_h_gr_2;
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| 268 |
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unsigned char out_h_gr_3;
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| 269 |
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unsigned char out_h_gr_31;
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| 270 |
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unsigned char out_h_gr_4;
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| 271 |
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unsigned char out_h_gr_5;
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| 272 |
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unsigned char out_h_gr_6;
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| 273 |
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unsigned char out_h_gr_7;
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| 274 |
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unsigned char out_h_gr_8;
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| 275 |
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unsigned char out_h_gr_9;
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| 276 |
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} sfmt_callx_indirect_offset;
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#if WITH_SCACHE_PBB
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/* Writeback handler. */
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struct {
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/* Pointer to argbuf entry for insn whose results need writing back. */
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const struct argbuf *abuf;
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} write;
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| 283 |
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/* x-before handler */
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struct {
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/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
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int first_p;
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} before;
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| 288 |
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/* x-after handler */
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struct {
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int empty;
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| 291 |
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} after;
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| 292 |
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/* This entry is used to terminate each pbb. */
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struct {
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/* Number of insns in pbb. */
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int insn_count;
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/* Next pbb to execute. */
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SCACHE *next;
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| 298 |
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SCACHE *branch_target;
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} chain;
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#endif
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};
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| 303 |
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/* The ARGBUF struct. */
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struct argbuf {
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| 305 |
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/* These are the baseclass definitions. */
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IADDR addr;
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| 307 |
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const IDESC *idesc;
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| 308 |
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char trace_p;
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| 309 |
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char profile_p;
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| 310 |
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/* ??? Temporary hack for skip insns. */
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| 311 |
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char skip_count;
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| 312 |
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char unused;
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| 313 |
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/* cpu specific data follows */
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union sem semantic;
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| 315 |
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int written;
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| 316 |
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union sem_fields fields;
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| 317 |
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};
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| 318 |
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| 319 |
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/* A cached insn.
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| 320 |
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| 321 |
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??? SCACHE used to contain more than just argbuf. We could delete the
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| 322 |
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type entirely and always just use ARGBUF, but for future concerns and as
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| 323 |
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a level of abstraction it is left in. */
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| 324 |
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| 325 |
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struct scache {
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| 326 |
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struct argbuf argbuf;
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| 327 |
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};
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| 328 |
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| 329 |
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|
/* Macros to simplify extraction, reading and semantic code.
|
| 330 |
|
|
These define and assign the local vars that contain the insn's fields. */
|
| 331 |
|
|
|
| 332 |
|
|
#define EXTRACT_IFMT_EMPTY_VARS \
|
| 333 |
|
|
unsigned int length;
|
| 334 |
|
|
#define EXTRACT_IFMT_EMPTY_CODE \
|
| 335 |
|
|
length = 0; \
|
| 336 |
|
|
|
| 337 |
|
|
#define EXTRACT_IFMT_MULO_VARS \
|
| 338 |
|
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UINT f_opcode; \
|
| 339 |
|
|
UINT f_srcdst; \
|
| 340 |
|
|
UINT f_src2; \
|
| 341 |
|
|
UINT f_m3; \
|
| 342 |
|
|
UINT f_m2; \
|
| 343 |
|
|
UINT f_m1; \
|
| 344 |
|
|
UINT f_opcode2; \
|
| 345 |
|
|
UINT f_zero; \
|
| 346 |
|
|
UINT f_src1; \
|
| 347 |
|
|
unsigned int length;
|
| 348 |
|
|
#define EXTRACT_IFMT_MULO_CODE \
|
| 349 |
|
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length = 4; \
|
| 350 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 351 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 352 |
|
|
f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 353 |
|
|
f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
|
| 354 |
|
|
f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
|
| 355 |
|
|
f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
|
| 356 |
|
|
f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
|
| 357 |
|
|
f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
|
| 358 |
|
|
f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
|
| 359 |
|
|
|
| 360 |
|
|
#define EXTRACT_IFMT_MULO1_VARS \
|
| 361 |
|
|
UINT f_opcode; \
|
| 362 |
|
|
UINT f_srcdst; \
|
| 363 |
|
|
UINT f_src2; \
|
| 364 |
|
|
UINT f_m3; \
|
| 365 |
|
|
UINT f_m2; \
|
| 366 |
|
|
UINT f_m1; \
|
| 367 |
|
|
UINT f_opcode2; \
|
| 368 |
|
|
UINT f_zero; \
|
| 369 |
|
|
UINT f_src1; \
|
| 370 |
|
|
unsigned int length;
|
| 371 |
|
|
#define EXTRACT_IFMT_MULO1_CODE \
|
| 372 |
|
|
length = 4; \
|
| 373 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 374 |
|
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f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 375 |
|
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f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 376 |
|
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f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
|
| 377 |
|
|
f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
|
| 378 |
|
|
f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
|
| 379 |
|
|
f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
|
| 380 |
|
|
f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
|
| 381 |
|
|
f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
|
| 382 |
|
|
|
| 383 |
|
|
#define EXTRACT_IFMT_MULO2_VARS \
|
| 384 |
|
|
UINT f_opcode; \
|
| 385 |
|
|
UINT f_srcdst; \
|
| 386 |
|
|
UINT f_src2; \
|
| 387 |
|
|
UINT f_m3; \
|
| 388 |
|
|
UINT f_m2; \
|
| 389 |
|
|
UINT f_m1; \
|
| 390 |
|
|
UINT f_opcode2; \
|
| 391 |
|
|
UINT f_zero; \
|
| 392 |
|
|
UINT f_src1; \
|
| 393 |
|
|
unsigned int length;
|
| 394 |
|
|
#define EXTRACT_IFMT_MULO2_CODE \
|
| 395 |
|
|
length = 4; \
|
| 396 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 397 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 398 |
|
|
f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 399 |
|
|
f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
|
| 400 |
|
|
f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
|
| 401 |
|
|
f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
|
| 402 |
|
|
f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
|
| 403 |
|
|
f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
|
| 404 |
|
|
f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
|
| 405 |
|
|
|
| 406 |
|
|
#define EXTRACT_IFMT_MULO3_VARS \
|
| 407 |
|
|
UINT f_opcode; \
|
| 408 |
|
|
UINT f_srcdst; \
|
| 409 |
|
|
UINT f_src2; \
|
| 410 |
|
|
UINT f_m3; \
|
| 411 |
|
|
UINT f_m2; \
|
| 412 |
|
|
UINT f_m1; \
|
| 413 |
|
|
UINT f_opcode2; \
|
| 414 |
|
|
UINT f_zero; \
|
| 415 |
|
|
UINT f_src1; \
|
| 416 |
|
|
unsigned int length;
|
| 417 |
|
|
#define EXTRACT_IFMT_MULO3_CODE \
|
| 418 |
|
|
length = 4; \
|
| 419 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 420 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 421 |
|
|
f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 422 |
|
|
f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
|
| 423 |
|
|
f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
|
| 424 |
|
|
f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
|
| 425 |
|
|
f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
|
| 426 |
|
|
f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
|
| 427 |
|
|
f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
|
| 428 |
|
|
|
| 429 |
|
|
#define EXTRACT_IFMT_LDA_OFFSET_VARS \
|
| 430 |
|
|
UINT f_opcode; \
|
| 431 |
|
|
UINT f_srcdst; \
|
| 432 |
|
|
UINT f_abase; \
|
| 433 |
|
|
UINT f_modea; \
|
| 434 |
|
|
UINT f_zeroa; \
|
| 435 |
|
|
UINT f_offset; \
|
| 436 |
|
|
unsigned int length;
|
| 437 |
|
|
#define EXTRACT_IFMT_LDA_OFFSET_CODE \
|
| 438 |
|
|
length = 4; \
|
| 439 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 440 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 441 |
|
|
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 442 |
|
|
f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
|
| 443 |
|
|
f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
|
| 444 |
|
|
f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \
|
| 445 |
|
|
|
| 446 |
|
|
#define EXTRACT_IFMT_LDA_INDIRECT_VARS \
|
| 447 |
|
|
UINT f_opcode; \
|
| 448 |
|
|
UINT f_srcdst; \
|
| 449 |
|
|
UINT f_abase; \
|
| 450 |
|
|
UINT f_modeb; \
|
| 451 |
|
|
UINT f_scale; \
|
| 452 |
|
|
UINT f_zerob; \
|
| 453 |
|
|
UINT f_index; \
|
| 454 |
|
|
unsigned int length;
|
| 455 |
|
|
#define EXTRACT_IFMT_LDA_INDIRECT_CODE \
|
| 456 |
|
|
length = 4; \
|
| 457 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 458 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 459 |
|
|
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 460 |
|
|
f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
|
| 461 |
|
|
f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
|
| 462 |
|
|
f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
|
| 463 |
|
|
f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
|
| 464 |
|
|
|
| 465 |
|
|
#define EXTRACT_IFMT_LDA_DISP_VARS \
|
| 466 |
|
|
UINT f_opcode; \
|
| 467 |
|
|
UINT f_optdisp; \
|
| 468 |
|
|
UINT f_srcdst; \
|
| 469 |
|
|
UINT f_abase; \
|
| 470 |
|
|
UINT f_modeb; \
|
| 471 |
|
|
UINT f_scale; \
|
| 472 |
|
|
UINT f_zerob; \
|
| 473 |
|
|
UINT f_index; \
|
| 474 |
|
|
/* Contents of trailing part of insn. */ \
|
| 475 |
|
|
UINT word_1; \
|
| 476 |
|
|
unsigned int length;
|
| 477 |
|
|
#define EXTRACT_IFMT_LDA_DISP_CODE \
|
| 478 |
|
|
length = 8; \
|
| 479 |
|
|
word_1 = GETIMEMUSI (current_cpu, pc + 4); \
|
| 480 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 481 |
|
|
f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \
|
| 482 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 483 |
|
|
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 484 |
|
|
f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
|
| 485 |
|
|
f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
|
| 486 |
|
|
f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
|
| 487 |
|
|
f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
|
| 488 |
|
|
|
| 489 |
|
|
#define EXTRACT_IFMT_ST_OFFSET_VARS \
|
| 490 |
|
|
UINT f_opcode; \
|
| 491 |
|
|
UINT f_srcdst; \
|
| 492 |
|
|
UINT f_abase; \
|
| 493 |
|
|
UINT f_modea; \
|
| 494 |
|
|
UINT f_zeroa; \
|
| 495 |
|
|
UINT f_offset; \
|
| 496 |
|
|
unsigned int length;
|
| 497 |
|
|
#define EXTRACT_IFMT_ST_OFFSET_CODE \
|
| 498 |
|
|
length = 4; \
|
| 499 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 500 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 501 |
|
|
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 502 |
|
|
f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
|
| 503 |
|
|
f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
|
| 504 |
|
|
f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \
|
| 505 |
|
|
|
| 506 |
|
|
#define EXTRACT_IFMT_ST_INDIRECT_VARS \
|
| 507 |
|
|
UINT f_opcode; \
|
| 508 |
|
|
UINT f_srcdst; \
|
| 509 |
|
|
UINT f_abase; \
|
| 510 |
|
|
UINT f_modeb; \
|
| 511 |
|
|
UINT f_scale; \
|
| 512 |
|
|
UINT f_zerob; \
|
| 513 |
|
|
UINT f_index; \
|
| 514 |
|
|
unsigned int length;
|
| 515 |
|
|
#define EXTRACT_IFMT_ST_INDIRECT_CODE \
|
| 516 |
|
|
length = 4; \
|
| 517 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 518 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 519 |
|
|
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 520 |
|
|
f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
|
| 521 |
|
|
f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
|
| 522 |
|
|
f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
|
| 523 |
|
|
f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
|
| 524 |
|
|
|
| 525 |
|
|
#define EXTRACT_IFMT_ST_DISP_VARS \
|
| 526 |
|
|
UINT f_opcode; \
|
| 527 |
|
|
UINT f_optdisp; \
|
| 528 |
|
|
UINT f_srcdst; \
|
| 529 |
|
|
UINT f_abase; \
|
| 530 |
|
|
UINT f_modeb; \
|
| 531 |
|
|
UINT f_scale; \
|
| 532 |
|
|
UINT f_zerob; \
|
| 533 |
|
|
UINT f_index; \
|
| 534 |
|
|
/* Contents of trailing part of insn. */ \
|
| 535 |
|
|
UINT word_1; \
|
| 536 |
|
|
unsigned int length;
|
| 537 |
|
|
#define EXTRACT_IFMT_ST_DISP_CODE \
|
| 538 |
|
|
length = 8; \
|
| 539 |
|
|
word_1 = GETIMEMUSI (current_cpu, pc + 4); \
|
| 540 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 541 |
|
|
f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \
|
| 542 |
|
|
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 543 |
|
|
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 544 |
|
|
f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
|
| 545 |
|
|
f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
|
| 546 |
|
|
f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
|
| 547 |
|
|
f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
|
| 548 |
|
|
|
| 549 |
|
|
#define EXTRACT_IFMT_CMPOBE_REG_VARS \
|
| 550 |
|
|
UINT f_opcode; \
|
| 551 |
|
|
UINT f_br_src1; \
|
| 552 |
|
|
UINT f_br_src2; \
|
| 553 |
|
|
UINT f_br_m1; \
|
| 554 |
|
|
SI f_br_disp; \
|
| 555 |
|
|
UINT f_br_zero; \
|
| 556 |
|
|
unsigned int length;
|
| 557 |
|
|
#define EXTRACT_IFMT_CMPOBE_REG_CODE \
|
| 558 |
|
|
length = 4; \
|
| 559 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 560 |
|
|
f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 561 |
|
|
f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 562 |
|
|
f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
|
| 563 |
|
|
f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
|
| 564 |
|
|
f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
|
| 565 |
|
|
|
| 566 |
|
|
#define EXTRACT_IFMT_CMPOBE_LIT_VARS \
|
| 567 |
|
|
UINT f_opcode; \
|
| 568 |
|
|
UINT f_br_src1; \
|
| 569 |
|
|
UINT f_br_src2; \
|
| 570 |
|
|
UINT f_br_m1; \
|
| 571 |
|
|
SI f_br_disp; \
|
| 572 |
|
|
UINT f_br_zero; \
|
| 573 |
|
|
unsigned int length;
|
| 574 |
|
|
#define EXTRACT_IFMT_CMPOBE_LIT_CODE \
|
| 575 |
|
|
length = 4; \
|
| 576 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 577 |
|
|
f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
|
| 578 |
|
|
f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
|
| 579 |
|
|
f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
|
| 580 |
|
|
f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
|
| 581 |
|
|
f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
|
| 582 |
|
|
|
| 583 |
|
|
#define EXTRACT_IFMT_BNO_VARS \
|
| 584 |
|
|
UINT f_opcode; \
|
| 585 |
|
|
SI f_ctrl_disp; \
|
| 586 |
|
|
UINT f_ctrl_zero; \
|
| 587 |
|
|
unsigned int length;
|
| 588 |
|
|
#define EXTRACT_IFMT_BNO_CODE \
|
| 589 |
|
|
length = 4; \
|
| 590 |
|
|
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
|
| 591 |
|
|
f_ctrl_disp = ((((EXTRACT_MSB0_INT (insn, 32, 8, 22)) << (2))) + (pc)); \
|
| 592 |
|
|
f_ctrl_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
|
| 593 |
|
|
|
| 594 |
|
|
/* Collection of various things for the trace handler to use. */
|
| 595 |
|
|
|
| 596 |
|
|
typedef struct trace_record {
|
| 597 |
|
|
IADDR pc;
|
| 598 |
|
|
/* FIXME:wip */
|
| 599 |
|
|
} TRACE_RECORD;
|
| 600 |
|
|
|
| 601 |
|
|
#endif /* CPU_I960BASE_H */
|
