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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [dbg_interface/] [dbg_trace.v] - Blame information for rev 769

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_trace.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:19:09  igorm
// no message
//
// Revision 1.4  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3  2001/09/19 11:55:13  mohor
// Asynchronous set/reset not used in trace any more.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:06  mohor
// Initial release
//
//
 
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
 
// module Trace
module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,
                  Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,
                  WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
                  BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
                  RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
                  RecordINSTR,
                  WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
                  WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
                  WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
                  LSSStopValid, IStopValid
                 );
 
parameter Tp = 1;
 
 
input [10:0] Wp;              // Watchpoints
input        Bp;              // Breakpoint
input [31:0] DataIn;          // Data from the RISC
input [3:0]  LsStatus;        // Load/Store status
input [1:0]  IStatus;         // Instruction status
 
input        Mclk;            // Master clock (RISC clock)
input        Reset;           // Reset
input        ReadBuffer;      // Instruction for reading a sample from the Buffer
 
// from registers
input ContinMode;             // Continous mode of the trace
input TraceEnable_reg;        // Trace is enabled (enabled by writing a bit in the register)
 
input [10:0] WpTrigger;       // Signals that come from registers to set the trigger
input        BpTrigger;       // Signals that come from registers to set the trigger
input [3:0]  LSSTrigger;      // Signals that come from registers to set the trigger
input [1:0]  ITrigger;        // Signals that come from registers to set the trigger
input [1:0]  TriggerOper;     // Signals that come from registers to set the trigger
 
input [10:0] WpQualif;        // Signals that come from registers to set the qualifier
input        BpQualif;        // Signals that come from registers to set the qualifier
input [3:0]  LSSQualif;       // Signals that come from registers to set the qualifier
input [1:0]  IQualif;         // Signals that come from registers to set the qualifier
input [1:0]  QualifOper;      // Signals that come from registers to set the qualifier
 
input [10:0] WpStop;          // Signals that come from registers to set the stop condition
input        BpStop;          // Signals that come from registers to set the stop condition
input [3:0]  LSSStop;         // Signals that come from registers to set the stop condition
input [1:0]  IStop;           // Signals that come from registers to set the stop condition
input [1:0]  StopOper;        // Signals that come from registers to set the stop condition
 
input RecordPC;               // Signals that come from registers for defining the sample for recording
input RecordLSEA;             // Signals that come from registers for defining the sample for recording
input RecordLDATA;            // Signals that come from registers for defining the sample for recording
input RecordSDATA;            // Signals that come from registers for defining the sample for recording
input RecordReadSPR;          // Signals that come from registers for defining the sample for recording
input RecordWriteSPR;         // Signals that come from registers for defining the sample for recording
input RecordINSTR;            // Signals that come from registers for defining the sample for recording
 
input WpTriggerValid;         // Signals that come from registers and indicate which trigger conditions are valid
input BpTriggerValid;         // Signals that come from registers and indicate which trigger conditions are valid
input LSSTriggerValid;        // Signals that come from registers and indicate which trigger conditions are valid
input ITriggerValid;          // Signals that come from registers and indicate which trigger conditions are valid
 
input WpQualifValid;          // Signals that come from registers and indicate which qualifier conditions are valid
input BpQualifValid;          // Signals that come from registers and indicate which qualifier conditions are valid
input LSSQualifValid;         // Signals that come from registers and indicate which qualifier conditions are valid
input IQualifValid;           // Signals that come from registers and indicate which qualifier conditions are valid
 
input WpStopValid;            // Signals that come from registers and indicate which stop conditions are valid
input BpStopValid;            // Signals that come from registers and indicate which stop conditions are valid
input LSSStopValid;           // Signals that come from registers and indicate which stop conditions are valid
input IStopValid;             // Signals that come from registers and indicate which stop conditions are valid
// end: from registers
 
 
output [`OPSELECTWIDTH-1:0]  OpSelect;  // Operation select (what kind of information is avaliable on the DataIn)
output        RiscStall_O;              // CPU stall (stalls the RISC)
output [39:0] TraceChain;               // Scan shain from the trace module
 
reg TraceEnable_d;
reg TraceEnable;
 
 
 
reg [`TRACECOUNTERWIDTH:0] Counter;
reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
reg RiscStall;
reg RiscStall_q;
reg [`OPSELECTWIDTH-1:0] StallCounter;
 
reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
 
reg TriggerLatch;
 
 
/**********************************************************************************
*                                                                                 *
*   Generation of the trigger                                                     *
*                                                                                 *
**********************************************************************************/
wire TempWpTrigger = |(Wp[10:0] & WpTrigger[10:0]);
wire TempBpTrigger = Bp & BpTrigger;
wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];
wire TempITrigger = IStatus[1:0] == ITrigger[1:0];
 
wire TempTriggerAND =  (  (TempWpTrigger  | ~WpTriggerValid)
                        & (TempBpTrigger  | ~BpTriggerValid)
                        & (TempLSSTrigger | ~LSSTriggerValid)
                        & (TempITrigger   | ~ITriggerValid)
                       )
                       & (WpTriggerValid | BpTriggerValid | LSSTriggerValid | ITriggerValid);
 
wire TempTriggerOR =   (  (TempWpTrigger  &  WpTriggerValid)
                        | (TempBpTrigger  &  BpTriggerValid)
                        | (TempLSSTrigger &  LSSTriggerValid)
                        | (TempITrigger   &  ITriggerValid)
                       );
 
wire Trigger = TraceEnable & (~TriggerOper[1]?  1 :                               // any
                               TriggerOper[0]?  TempTriggerAND : TempTriggerOR    // AND : OR
                             );
 
/**********************************************************************************
*                                                                                 *
*   Generation of the qualifier                                                   *
*                                                                                 *
**********************************************************************************/
wire TempWpQualifier = |(Wp[10:0] & WpQualif[10:0]);
wire TempBpQualifier = Bp & BpQualif;
wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];
wire TempIQualifier = IStatus[1:0] == IQualif[1:0];
 
wire TempQualifierAND =  (  (TempWpQualifier  | ~WpQualifValid)
                          & (TempBpQualifier  | ~BpQualifValid)
                          & (TempLSSQualifier | ~LSSQualifValid)
                          & (TempIQualifier   | ~IQualifValid)
                         )
                         & (WpQualifValid | BpQualifValid | LSSQualifValid | IQualifValid);
 
wire TempQualifierOR =   (  (TempWpQualifier  &  WpQualifValid)
                          | (TempBpQualifier  &  BpQualifValid)
                          | (TempLSSQualifier &  LSSQualifValid)
                          | (TempIQualifier   &  IQualifValid)
                         );
 
 
wire Stop;
wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 :                                   // any
                                         QualifOper[0]? TempQualifierAND  :  TempQualifierOR  // AND : OR
                                       );
 
/**********************************************************************************
*                                                                                 *
*   Generation of the stop signal                                                 *
*                                                                                 *
**********************************************************************************/
wire TempWpStop = |(Wp[10:0] & WpStop[10:0]);
wire TempBpStop = Bp & BpStop;
wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];
wire TempIStop = IStatus[1:0] == IStop[1:0];
 
wire TempStopAND =       (  (TempWpStop  | ~WpStopValid)
                          & (TempBpStop  | ~BpStopValid)
                          & (TempLSSStop | ~LSSStopValid)
                          & (TempIStop   | ~IStopValid)
                         )
                         & (WpStopValid | BpStopValid | LSSStopValid | IStopValid);
 
wire TempStopOR =        (  (TempWpStop  &  WpStopValid)
                          | (TempBpStop  &  BpStopValid)
                          | (TempLSSStop &  LSSStopValid)
                          | (TempIStop   &  IStopValid)
                         );
 
 
assign Stop = TraceEnable & (~StopOper[1]? 0 :                         // nothing
                              StopOper[0]? TempStopAND  :  TempStopOR  // AND : OR
                            );
 
 
 
/**********************************************************************************
*                                                                                 *
*   Generation of the TriggerLatch                                                *
*                                                                                 *
**********************************************************************************/
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    TriggerLatch<=#Tp 0;
  else
  if(TriggerLatch & ~TraceEnable)
    TriggerLatch<=#Tp 0;
  else
  if(Trigger)
    TriggerLatch<=#Tp 1;
end
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   TraceEnable Synchronization                                                   *
*                                                                                 *
**********************************************************************************/
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    begin
      TraceEnable_d<=#Tp 0;
      TraceEnable<=#Tp 0;
    end
  else
    begin
      TraceEnable_d<=#Tp TraceEnable_reg;
      TraceEnable<=#Tp TraceEnable_d;
    end
end
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   RiscStall, counter and pointers generation                                     *
*                                                                                 *
**********************************************************************************/
reg BufferFullDetected;
wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
 
wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
wire IncrementCounter = RiscStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
wire IncrementPointer = RiscStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
 
wire WriteSample = IncrementPointer;
 
wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
wire CounterEn = IncrementCounter ^ Decrement;
 
wire SyncResetCpuStall;
wire ResetStallCounter;
reg BufferFull_q;
reg BufferFull_2q;
 
reg Qualifier_mclk;
 
always @(posedge Mclk)
begin
  Qualifier_mclk<=#Tp Qualifier;
  BufferFull_q<=#Tp BufferFull;
  BufferFull_2q<=#Tp BufferFull_q;
  RiscStall_q <=#Tp RiscStall_O;
end
 
 
wire FirstCpuStall =    Qualifier & ~Qualifier_mclk & TriggerLatch              |
                        Qualifier_mclk & Trigger & ~TriggerLatch                |
                        Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch   ;
 
 
//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
 
wire SyncSetCpuStall = RiscStall_O & ~RiscStall_q |
                        Qualifier_mclk & TriggerLatch &
                       (
                        (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
                        (~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0)                   |
                        ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
                       );
 
assign SyncResetCpuStall = (
                            (~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
                            (~ContinMode &  ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
                            ( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
                           );
 
assign RiscStall_O = FirstCpuStall | RiscStall;
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    Counter<=#Tp 0;
  else
  if(CounterEn)
    if(IncrementCounter)
      Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
    else
      Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    WritePointer<=#Tp 0;
  else
  if(IncrementPointer)
    WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
end
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    ReadPointer<=#Tp 0;
  else
  if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
    ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
  else
  if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
    ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
end
 
always @(posedge Mclk)
begin
  if(~TraceEnable)
    BufferFullDetected<=#Tp 0;
  else
  if(ContinMode & BufferFull)
    BufferFullDetected<=#Tp 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
  if(Reset)
    RiscStall<=#Tp 0;
  else
  if(SyncResetCpuStall)
    RiscStall<=#Tp 0;
  else
  if(SyncSetCpuStall)
    RiscStall<=#Tp 1;
end
 
 
always @(posedge Mclk)
begin
  if(ResetStallCounter)
    StallCounter<=#Tp 0;
  else
  if(RiscStall_q & (~BufferFull | ContinMode))
    StallCounter<=#Tp StallCounter+1;
end
 
assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
 
 
/**********************************************************************************
*                                                                                 *
*   Valid status                                                                  *
*                                                                                 *
**********************************************************************************/
wire Valid = ~BufferEmpty;
 
 
/**********************************************************************************
*                                                                                 *
*   Writing and reading the sample to/from the buffer                             *
*                                                                                 *
**********************************************************************************/
always @ (posedge Mclk)
begin
  if(WriteSample)
    Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
end
 
assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};
 
 
 
/**********************************************************************************
*                                                                                 *
*   Operation select (to select which kind of data appears on the DATAIN lines)   *
*                                                                                 *
**********************************************************************************/
assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
 
 
 
/**********************************************************************************
*                                                                                 *
*   Selecting which parts are going to be recorded as part of the sample          *
*                                                                                 *
**********************************************************************************/
assign RecEnable = {1'b0, RecordINSTR,  RecordWriteSPR,  RecordReadSPR,  RecordSDATA,  RecordLDATA,  RecordLSEA,  RecordPC};
 
 
endmodule

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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [dbg_interface/] [dbg_trace.v] - Blame information for rev 769

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_trace.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.1.1.1 2001/10/06 10:19:09 igorm`
49			`// no message`
50			`//`
51			`// Revision 1.4 2001/09/20 10:11:25 mohor`
52			`// Working version. Few bugs fixed, comments added.`
53			`//`
54			`// Revision 1.3 2001/09/19 11:55:13 mohor`
55			`// Asynchronous set/reset not used in trace any more.`
56			`//`
57			`// Revision 1.2 2001/09/18 14:13:47 mohor`
58			`// Trace fixed. Some registers changed, trace simplified.`
59			`//`
60			`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
61			`// Initial official release.`
62			`//`
63			`// Revision 1.3 2001/06/01 22:22:35 mohor`
64			`// This is a backup. It is not a fully working version. Not for use, yet.`
65			`//`
66			`// Revision 1.2 2001/05/18 13:10:00 mohor`
67			`// Headers changed. All additional information is now avaliable in the README.txt file.`
68			`//`
69			`// Revision 1.1.1.1 2001/05/18 06:35:06 mohor`
70			`// Initial release`
71			`//`
72			`//`
73
74
75			`include "dbg_timescale.v"
76			`include "dbg_defines.v"
77
78			`// module Trace`
79			`module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,`
80			`Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,`
81			`WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,`
82			`BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,`
83			`RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,`
84			`RecordINSTR,`
85			`WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,`
86			`WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,`
87			`WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,`
88			`LSSStopValid, IStopValid`
89			`);`
90
91			`parameter Tp = 1;`
92
93
94			`input [10:0] Wp; // Watchpoints`
95			`input Bp; // Breakpoint`
96			`input [31:0] DataIn; // Data from the RISC`
97			`input [3:0] LsStatus; // Load/Store status`
98			`input [1:0] IStatus; // Instruction status`
99
100			`input Mclk; // Master clock (RISC clock)`
101			`input Reset; // Reset`
102			`input ReadBuffer; // Instruction for reading a sample from the Buffer`
103
104			`// from registers`
105			`input ContinMode; // Continous mode of the trace`
106			`input TraceEnable_reg; // Trace is enabled (enabled by writing a bit in the register)`
107
108			`input [10:0] WpTrigger; // Signals that come from registers to set the trigger`
109			`input BpTrigger; // Signals that come from registers to set the trigger`
110			`input [3:0] LSSTrigger; // Signals that come from registers to set the trigger`
111			`input [1:0] ITrigger; // Signals that come from registers to set the trigger`
112			`input [1:0] TriggerOper; // Signals that come from registers to set the trigger`
113
114			`input [10:0] WpQualif; // Signals that come from registers to set the qualifier`
115			`input BpQualif; // Signals that come from registers to set the qualifier`
116			`input [3:0] LSSQualif; // Signals that come from registers to set the qualifier`
117			`input [1:0] IQualif; // Signals that come from registers to set the qualifier`
118			`input [1:0] QualifOper; // Signals that come from registers to set the qualifier`
119
120			`input [10:0] WpStop; // Signals that come from registers to set the stop condition`
121			`input BpStop; // Signals that come from registers to set the stop condition`
122			`input [3:0] LSSStop; // Signals that come from registers to set the stop condition`
123			`input [1:0] IStop; // Signals that come from registers to set the stop condition`
124			`input [1:0] StopOper; // Signals that come from registers to set the stop condition`
125
126			`input RecordPC; // Signals that come from registers for defining the sample for recording`
127			`input RecordLSEA; // Signals that come from registers for defining the sample for recording`
128			`input RecordLDATA; // Signals that come from registers for defining the sample for recording`
129			`input RecordSDATA; // Signals that come from registers for defining the sample for recording`
130			`input RecordReadSPR; // Signals that come from registers for defining the sample for recording`
131			`input RecordWriteSPR; // Signals that come from registers for defining the sample for recording`
132			`input RecordINSTR; // Signals that come from registers for defining the sample for recording`
133
134			`input WpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid`
135			`input BpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid`
136			`input LSSTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid`
137			`input ITriggerValid; // Signals that come from registers and indicate which trigger conditions are valid`
138
139			`input WpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid`
140			`input BpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid`
141			`input LSSQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid`
142			`input IQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid`
143
144			`input WpStopValid; // Signals that come from registers and indicate which stop conditions are valid`
145			`input BpStopValid; // Signals that come from registers and indicate which stop conditions are valid`
146			`input LSSStopValid; // Signals that come from registers and indicate which stop conditions are valid`
147			`input IStopValid; // Signals that come from registers and indicate which stop conditions are valid`
148			`// end: from registers`
149
150
151			output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
152			`output RiscStall_O; // CPU stall (stalls the RISC)`
153			`output [39:0] TraceChain; // Scan shain from the trace module`
154
155			`reg TraceEnable_d;`
156			`reg TraceEnable;`
157
158
159
160			reg [`TRACECOUNTERWIDTH:0] Counter;
161			reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
162			reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
163			`reg RiscStall;`
164			`reg RiscStall_q;`
165			reg [`OPSELECTWIDTH-1:0] StallCounter;
166
167			reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
168
169			`reg TriggerLatch;`
170
171
172			`/**********************************************************************************`
173			`* *`
174			`* Generation of the trigger *`
175			`* *`
176			`**********************************************************************************/`
177			`wire TempWpTrigger = \|(Wp[10:0] & WpTrigger[10:0]);`
178			`wire TempBpTrigger = Bp & BpTrigger;`
179			`wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];`
180			`wire TempITrigger = IStatus[1:0] == ITrigger[1:0];`
181
182			`wire TempTriggerAND = ( (TempWpTrigger \| ~WpTriggerValid)`
183			`& (TempBpTrigger \| ~BpTriggerValid)`
184			`& (TempLSSTrigger \| ~LSSTriggerValid)`
185			`& (TempITrigger \| ~ITriggerValid)`
186			`)`
187			`& (WpTriggerValid \| BpTriggerValid \| LSSTriggerValid \| ITriggerValid);`
188
189			`wire TempTriggerOR = ( (TempWpTrigger & WpTriggerValid)`
190			`\| (TempBpTrigger & BpTriggerValid)`
191			`\| (TempLSSTrigger & LSSTriggerValid)`
192			`\| (TempITrigger & ITriggerValid)`
193			`);`
194
195			`wire Trigger = TraceEnable & (~TriggerOper[1]? 1 : // any`
196			`TriggerOper[0]? TempTriggerAND : TempTriggerOR // AND : OR`
197			`);`
198
199			`/**********************************************************************************`
200			`* *`
201			`* Generation of the qualifier *`
202			`* *`
203			`**********************************************************************************/`
204			`wire TempWpQualifier = \|(Wp[10:0] & WpQualif[10:0]);`
205			`wire TempBpQualifier = Bp & BpQualif;`
206			`wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];`
207			`wire TempIQualifier = IStatus[1:0] == IQualif[1:0];`
208
209			`wire TempQualifierAND = ( (TempWpQualifier \| ~WpQualifValid)`
210			`& (TempBpQualifier \| ~BpQualifValid)`
211			`& (TempLSSQualifier \| ~LSSQualifValid)`
212			`& (TempIQualifier \| ~IQualifValid)`
213			`)`
214			`& (WpQualifValid \| BpQualifValid \| LSSQualifValid \| IQualifValid);`
215
216			`wire TempQualifierOR = ( (TempWpQualifier & WpQualifValid)`
217			`\| (TempBpQualifier & BpQualifValid)`
218			`\| (TempLSSQualifier & LSSQualifValid)`
219			`\| (TempIQualifier & IQualifValid)`
220			`);`
221
222
223			`wire Stop;`
224			`wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 : // any`
225			`QualifOper[0]? TempQualifierAND : TempQualifierOR // AND : OR`
226			`);`
227
228			`/**********************************************************************************`
229			`* *`
230			`* Generation of the stop signal *`
231			`* *`
232			`**********************************************************************************/`
233			`wire TempWpStop = \|(Wp[10:0] & WpStop[10:0]);`
234			`wire TempBpStop = Bp & BpStop;`
235			`wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];`
236			`wire TempIStop = IStatus[1:0] == IStop[1:0];`
237
238			`wire TempStopAND = ( (TempWpStop \| ~WpStopValid)`
239			`& (TempBpStop \| ~BpStopValid)`
240			`& (TempLSSStop \| ~LSSStopValid)`
241			`& (TempIStop \| ~IStopValid)`
242			`)`
243			`& (WpStopValid \| BpStopValid \| LSSStopValid \| IStopValid);`
244
245			`wire TempStopOR = ( (TempWpStop & WpStopValid)`
246			`\| (TempBpStop & BpStopValid)`
247			`\| (TempLSSStop & LSSStopValid)`
248			`\| (TempIStop & IStopValid)`
249			`);`
250
251
252			`assign Stop = TraceEnable & (~StopOper[1]? 0 : // nothing`
253			`StopOper[0]? TempStopAND : TempStopOR // AND : OR`
254			`);`
255
256
257
258			`/**********************************************************************************`
259			`* *`
260			`* Generation of the TriggerLatch *`
261			`* *`
262			`**********************************************************************************/`
263			`always @(posedge Mclk or posedge Reset)`
264			`begin`
265			`if(Reset)`
266			`TriggerLatch<=#Tp 0;`
267			`else`
268			`if(TriggerLatch & ~TraceEnable)`
269			`TriggerLatch<=#Tp 0;`
270			`else`
271			`if(Trigger)`
272			`TriggerLatch<=#Tp 1;`
273			`end`
274
275
276
277
278			`/**********************************************************************************`
279			`* *`
280			`* TraceEnable Synchronization *`
281			`* *`
282			`**********************************************************************************/`
283			`always @(posedge Mclk or posedge Reset)`
284			`begin`
285			`if(Reset)`
286			`begin`
287			`TraceEnable_d<=#Tp 0;`
288			`TraceEnable<=#Tp 0;`
289			`end`
290			`else`
291			`begin`
292			`TraceEnable_d<=#Tp TraceEnable_reg;`
293			`TraceEnable<=#Tp TraceEnable_d;`
294			`end`
295			`end`
296
297
298
299
300			`/**********************************************************************************`
301			`* *`
302			`* RiscStall, counter and pointers generation *`
303			`* *`
304			`**********************************************************************************/`
305			`reg BufferFullDetected;`
306			wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
307
308			wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
309			wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
310			`wire IncrementCounter = RiscStall_q & ~(BufferFull \| BufferFullDetected) & Qualifier & RecEnable[StallCounter];`
311			`wire IncrementPointer = RiscStall_q & (~BufferFull \| ContinMode) & Qualifier & RecEnable[StallCounter];`
312
313			`wire WriteSample = IncrementPointer;`
314
315			`wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode \| ContinMode & ~TraceEnable);`
316			`wire CounterEn = IncrementCounter ^ Decrement;`
317
318			`wire SyncResetCpuStall;`
319			`wire ResetStallCounter;`
320			`reg BufferFull_q;`
321			`reg BufferFull_2q;`
322
323			`reg Qualifier_mclk;`
324
325			`always @(posedge Mclk)`
326			`begin`
327			`Qualifier_mclk<=#Tp Qualifier;`
328			`BufferFull_q<=#Tp BufferFull;`
329			`BufferFull_2q<=#Tp BufferFull_q;`
330			`RiscStall_q <=#Tp RiscStall_O;`
331			`end`
332
333
334			`wire FirstCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch \|`
335			`Qualifier_mclk & Trigger & ~TriggerLatch \|`
336			`Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch ;`
337
338
339			`//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &`
340
341			`wire SyncSetCpuStall = RiscStall_O & ~RiscStall_q \|`
342			`Qualifier_mclk & TriggerLatch &`
343			`(`
344			(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) \|
345			`(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) \|`
346			( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
347			`);`
348
349			`assign SyncResetCpuStall = (`
350			(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) \|
351			(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) \|
352			( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
353			`);`
354
355			`assign RiscStall_O = FirstCpuStall \| RiscStall;`
356
357
358			`always @(posedge Mclk or posedge Reset)`
359			`begin`
360			`if(Reset)`
361			`Counter<=#Tp 0;`
362			`else`
363			`if(CounterEn)`
364			`if(IncrementCounter)`
365			Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
366			`else`
367			Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
368			`end`
369
370
371			`always @(posedge Mclk or posedge Reset)`
372			`begin`
373			`if(Reset)`
374			`WritePointer<=#Tp 0;`
375			`else`
376			`if(IncrementPointer)`
377			WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
378			`end`
379
380			`always @(posedge Mclk or posedge Reset)`
381			`begin`
382			`if(Reset)`
383			`ReadPointer<=#Tp 0;`
384			`else`
385			`if(Decrement & ~ContinMode \| Decrement & ContinMode & ~TraceEnable)`
386			ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
387			`else`
388			`if(ContinMode & IncrementPointer & (BufferFull \| BufferFullDetected))`
389			ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
390			`end`
391
392			`always @(posedge Mclk)`
393			`begin`
394			`if(~TraceEnable)`
395			`BufferFullDetected<=#Tp 0;`
396			`else`
397			`if(ContinMode & BufferFull)`
398			`BufferFullDetected<=#Tp 1;`
399			`end`
400
401
402			`always @(posedge Mclk or posedge Reset)`
403			`begin`
404			`if(Reset)`
405			`RiscStall<=#Tp 0;`
406			`else`
407			`if(SyncResetCpuStall)`
408			`RiscStall<=#Tp 0;`
409			`else`
410			`if(SyncSetCpuStall)`
411			`RiscStall<=#Tp 1;`
412			`end`
413
414
415			`always @(posedge Mclk)`
416			`begin`
417			`if(ResetStallCounter)`
418			`StallCounter<=#Tp 0;`
419			`else`
420			`if(RiscStall_q & (~BufferFull \| ContinMode))`
421			`StallCounter<=#Tp StallCounter+1;`
422			`end`
423
424			assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull \| Reset;
425
426
427			`/**********************************************************************************`
428			`* *`
429			`* Valid status *`
430			`* *`
431			`**********************************************************************************/`
432			`wire Valid = ~BufferEmpty;`
433
434
435			`/**********************************************************************************`
436			`* *`
437			`* Writing and reading the sample to/from the buffer *`
438			`* *`
439			`**********************************************************************************/`
440			`always @ (posedge Mclk)`
441			`begin`
442			`if(WriteSample)`
443			Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
444			`end`
445
446			`assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};`
447
448
449
450			`/**********************************************************************************`
451			`* *`
452			`* Operation select (to select which kind of data appears on the DATAIN lines) *`
453			`* *`
454			`**********************************************************************************/`
455			assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
456
457
458
459			`/**********************************************************************************`
460			`* *`
461			`* Selecting which parts are going to be recorded as part of the sample *`
462			`* *`
463			`**********************************************************************************/`
464			`assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};`
465
466
467			`endmodule`