URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [dc_fsm.v] - Blame information for rev 1780

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define DCFSM_IDLE      3'd0
`define DCFSM_DOLOAD    3'd1
`define DCFSM_LREFILL3  3'd2
`define DCFSM_DOSTORE   3'd3
`define DCFSM_SREFILL3  3'd4
`define DCFSM_SMEMWR    3'd5
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        lsu_op, miss, biudata_valid, start_addr, saved_addr,
        refill, refill_first, refill_prepare, dcram_we,
        biu_read, biu_write, refill_rest, cntrbusy
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           miss;
input                           biudata_valid;
input   [31:0]                   start_addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
output  [31:0]                   saved_addr;
output                          refill;
output                          refill_first;
output                          refill_prepare;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          refill_rest;
output                          cntrbusy;
 
//
// Internal wires and regs
//
wire                            dcache_off = 1'b0;
reg     [31:0]                   saved_addr;
reg                             refill;
reg     [3:0]                    dcram_we;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             refill_first;
reg                             refill_prepare;
reg                             biu_read;
reg                             biu_write;
reg                             refill_rest;
reg                             cntrbusy;
 
//
// Generation of DCRAM write enable
//
always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin
        if (refill_first || !refill)
                casex({lsu_op, start_addr[1:0]})
                        {`LSUOP_SB, 2'b00} : dcram_we = 4'b1000 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b01} : dcram_we = 4'b0100 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b10} : dcram_we = 4'b0010 ^ {4{refill_first}};
                        {`LSUOP_SB, 2'b11} : dcram_we = 4'b0001 ^ {4{refill_first}};
                        {`LSUOP_SH, 2'b00} : dcram_we = 4'b1100 ^ {4{refill_first}};
                        {`LSUOP_SH, 2'b10} : dcram_we = 4'b0011 ^ {4{refill_first}};
                        {`LSUOP_SW, 2'b00} : dcram_we = 4'b1111 ^ {4{refill_first}};
                        {`LSUOP_LWZ, 2'bxx}, {`LSUOP_LHZ, 2'bxx}, {`LSUOP_LHS, 2'bxx},
                        {`LSUOP_LBS, 2'bxx}, {`LSUOP_LBZ, 2'bxx} : dcram_we = 4'b0000 ^ {4{refill_first}};
                        default : dcram_we = 4'b0000;
                endcase
        else
                dcram_we = {4{refill & biudata_valid & ~biu_write}};
end
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                refill <= #1 1'b0;
                state <= #1 `DCFSM_IDLE;
                cnt <= #1 3'b000;
                refill_first <= #1 1'b0;
                biu_read <= #1 1'b0;
                biu_write <= #1 1'b0;
                saved_addr <= #1 32'b0;
                refill_prepare <= #1 1'b0;
                refill_rest <= #1 1'b0;
                cntrbusy <= #1 1'b0;
        end
        else
        case (state)    // synopsys full_case parallel_case
                `DCFSM_IDLE :
                        casex(lsu_op)
                                `LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                        $display("%t: DC_FSM Load op %h  start_addr %h", $time, lsu_op, start_addr);
// synopsys translate_on
`endif
                                        state <= #1 `DCFSM_DOLOAD;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                `LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                        $display("%t: DC_FSM Store op %h  start_addr %h", $time, lsu_op, start_addr);
// synopsys translate_on
`endif
                                        state <= #1 `DCFSM_DOSTORE;
                                        refill <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b1;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                                default: begin
                                        state <= #1 `DCFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        refill_prepare <= #1 1'b0;
                                        refill_rest <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        biu_write <= #1 1'b0;
                                        cntrbusy <= #1 1'b0;
                                end
                        endcase
                `DCFSM_DOLOAD:
                        if (dcache_off) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM DCache off", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_DOLOAD;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                refill_rest <= #1 1'b0;
                                biu_read <= #1 1'b1;
                                if (biudata_valid) begin
                                        state <= #1 `DCFSM_IDLE;
                                        refill <= #1 1'b0;
                                        refill_first <= #1 1'b0;
                                        biu_read <= #1 1'b0;
                                        saved_addr <= #1 start_addr;
                                end
                        end else
                        if (miss) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load miss", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_LREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load hit", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
                `DCFSM_LREFILL3 : begin
                        if (biudata_valid && (|cnt)) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load refill %d", $time, cnt);
// synopsys translate_on
`endif
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Load refill end", $time, cnt);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                refill_first <= #1 1'b0;
                                biu_read <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
                `DCFSM_DOSTORE:
                        if (miss) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store miss", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SREFILL3;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b1;
                                refill_prepare <= #1 1'b0;
                                cnt <= #1 3'd3;
                                biu_read <= #1 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store hit", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SMEMWR;
                                refill <= #1 1'b1;
                                refill_first <= #1 1'b0;
                                refill_prepare <= #1 1'b0;
                                biu_write <= #1 1'b1;
                                biu_read <= #1 1'b0;
                        end
                `DCFSM_SREFILL3 : begin
                        if (biudata_valid && (|cnt)) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill %d", $time, cnt);
// synopsys translate_on
`endif
                                cnt <= #1 cnt - 'd1;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                refill_first <= #1 1'b0;
                        end
                        else if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill almost done", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_SMEMWR;
                                saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;
                                biu_write <= #1 1'b1;
                                biu_read <= #1 1'b0;
                        end
                        refill_rest <= #1 ~refill_first & refill;
                end
                `DCFSM_SMEMWR :
                        if (biudata_valid) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);
// synopsys translate_on
`endif
                                state <= #1 `DCFSM_IDLE;
                                refill <= #1 1'b0;
                                biu_write <= #1 1'b0;
                                cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;
                        end
        endcase
end
 
endmodule

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [dc_fsm.v] - Blame information for rev 1780

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:03 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`define DCFSM_IDLE 3'd0
64			`define DCFSM_DOLOAD 3'd1
65			`define DCFSM_LREFILL3 3'd2
66			`define DCFSM_DOSTORE 3'd3
67			`define DCFSM_SREFILL3 3'd4
68			`define DCFSM_SMEMWR 3'd5
69
70			`//`
71			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
72			`//`
73
74			`module dc_fsm(`
75			`// Clock and reset`
76			`clk, rst,`
77
78			`// Internal i/f to top level DC`
79			`lsu_op, miss, biudata_valid, start_addr, saved_addr,`
80			`refill, refill_first, refill_prepare, dcram_we,`
81			`biu_read, biu_write, refill_rest, cntrbusy`
82			`);`
83
84			`//`
85			`// I/O`
86			`//`
87			`input clk;`
88			`input rst;`
89			`input miss;`
90			`input biudata_valid;`
91			`input [31:0] start_addr;`
92			input [`LSUOP_WIDTH-1:0] lsu_op;
93			`output [31:0] saved_addr;`
94			`output refill;`
95			`output refill_first;`
96			`output refill_prepare;`
97			`output [3:0] dcram_we;`
98			`output biu_read;`
99			`output biu_write;`
100			`output refill_rest;`
101			`output cntrbusy;`
102
103			`//`
104			`// Internal wires and regs`
105			`//`
106			`wire dcache_off = 1'b0;`
107			`reg [31:0] saved_addr;`
108			`reg refill;`
109			`reg [3:0] dcram_we;`
110			`reg [2:0] state;`
111			`reg [2:0] cnt;`
112			`reg refill_first;`
113			`reg refill_prepare;`
114			`reg biu_read;`
115			`reg biu_write;`
116			`reg refill_rest;`
117			`reg cntrbusy;`
118
119			`//`
120			`// Generation of DCRAM write enable`
121			`//`
122			`always @(refill_first or refill or biudata_valid or lsu_op or start_addr or biu_write) begin`
123			`if (refill_first \|\| !refill)`
124			`casex({lsu_op, start_addr[1:0]})`
125			{`LSUOP_SB, 2'b00} : dcram_we = 4'b1000 ^ {4{refill_first}};
126			{`LSUOP_SB, 2'b01} : dcram_we = 4'b0100 ^ {4{refill_first}};
127			{`LSUOP_SB, 2'b10} : dcram_we = 4'b0010 ^ {4{refill_first}};
128			{`LSUOP_SB, 2'b11} : dcram_we = 4'b0001 ^ {4{refill_first}};
129			{`LSUOP_SH, 2'b00} : dcram_we = 4'b1100 ^ {4{refill_first}};
130			{`LSUOP_SH, 2'b10} : dcram_we = 4'b0011 ^ {4{refill_first}};
131			{`LSUOP_SW, 2'b00} : dcram_we = 4'b1111 ^ {4{refill_first}};
132			{`LSUOP_LWZ, 2'bxx}, {`LSUOP_LHZ, 2'bxx}, {`LSUOP_LHS, 2'bxx},
133			{`LSUOP_LBS, 2'bxx}, {`LSUOP_LBZ, 2'bxx} : dcram_we = 4'b0000 ^ {4{refill_first}};
134			`default : dcram_we = 4'b0000;`
135			`endcase`
136			`else`
137			`dcram_we = {4{refill & biudata_valid & ~biu_write}};`
138			`end`
139
140			`//`
141			`// Main DC FSM`
142			`//`
143			`always @(posedge clk or posedge rst) begin`
144			`if (rst) begin`
145			`refill <= #1 1'b0;`
146			state <= #1 `DCFSM_IDLE;
147			`cnt <= #1 3'b000;`
148			`refill_first <= #1 1'b0;`
149			`biu_read <= #1 1'b0;`
150			`biu_write <= #1 1'b0;`
151			`saved_addr <= #1 32'b0;`
152			`refill_prepare <= #1 1'b0;`
153			`refill_rest <= #1 1'b0;`
154			`cntrbusy <= #1 1'b0;`
155			`end`
156			`else`
157			`case (state) // synopsys full_case parallel_case`
158			`DCFSM_IDLE :
159			`casex(lsu_op)`
160			`LSUOP_LBZ, `LSUOP_LBS, `LSUOP_LHZ, `LSUOP_LHS, `LSUOP_LWZ: begin
161			`ifdef OR1200_VERBOSE
162			`// synopsys translate_off`
163			`$display("%t: DC_FSM Load op %h start_addr %h", $time, lsu_op, start_addr);`
164			`// synopsys translate_on`
165			`endif
166			state <= #1 `DCFSM_DOLOAD;
167			`refill <= #1 1'b0;`
168			`saved_addr <= #1 start_addr;`
169			`refill_first <= #1 1'b0;`
170			`refill_prepare <= #1 1'b1;`
171			`biu_read <= #1 1'b0;`
172			`biu_write <= #1 1'b0;`
173			`refill_rest <= #1 1'b0;`
174			`cntrbusy <= #1 1'b0;`
175			`end`
176			`LSUOP_SB, `LSUOP_SH, `LSUOP_SW: begin
177			`ifdef OR1200_VERBOSE
178			`// synopsys translate_off`
179			`$display("%t: DC_FSM Store op %h start_addr %h", $time, lsu_op, start_addr);`
180			`// synopsys translate_on`
181			`endif
182			state <= #1 `DCFSM_DOSTORE;
183			`refill <= #1 1'b0;`
184			`saved_addr <= #1 start_addr;`
185			`refill_first <= #1 1'b0;`
186			`refill_prepare <= #1 1'b1;`
187			`biu_read <= #1 1'b0;`
188			`biu_write <= #1 1'b0;`
189			`refill_rest <= #1 1'b0;`
190			`cntrbusy <= #1 1'b0;`
191			`end`
192			`default: begin`
193			state <= #1 `DCFSM_IDLE;
194			`refill <= #1 1'b0;`
195			`refill_first <= #1 1'b0;`
196			`refill_prepare <= #1 1'b0;`
197			`refill_rest <= #1 1'b0;`
198			`biu_read <= #1 1'b0;`
199			`biu_write <= #1 1'b0;`
200			`cntrbusy <= #1 1'b0;`
201			`end`
202			`endcase`
203			`DCFSM_DOLOAD:
204			`if (dcache_off) begin`
205			`ifdef OR1200_VERBOSE
206			`// synopsys translate_off`
207			`$display("%t: DC_FSM DCache off", $time);`
208			`// synopsys translate_on`
209			`endif
210			state <= #1 `DCFSM_DOLOAD;
211			`refill <= #1 1'b1;`
212			`refill_first <= #1 1'b1;`
213			`refill_prepare <= #1 1'b0;`
214			`refill_rest <= #1 1'b0;`
215			`biu_read <= #1 1'b1;`
216			`if (biudata_valid) begin`
217			state <= #1 `DCFSM_IDLE;
218			`refill <= #1 1'b0;`
219			`refill_first <= #1 1'b0;`
220			`biu_read <= #1 1'b0;`
221			`saved_addr <= #1 start_addr;`
222			`end`
223			`end else`
224			`if (miss) begin`
225			`ifdef OR1200_VERBOSE
226			`// synopsys translate_off`
227			`$display("%t: DC_FSM Load miss", $time);`
228			`// synopsys translate_on`
229			`endif
230			state <= #1 `DCFSM_LREFILL3;
231			`refill <= #1 1'b1;`
232			`refill_first <= #1 1'b1;`
233			`refill_prepare <= #1 1'b0;`
234			`cnt <= #1 3'd3;`
235			`biu_read <= #1 1'b1;`
236			`end`
237			`else begin`
238			`ifdef OR1200_VERBOSE
239			`// synopsys translate_off`
240			`$display("%t: DC_FSM Load hit", $time);`
241			`// synopsys translate_on`
242			`endif
243			state <= #1 `DCFSM_IDLE;
244			`refill <= #1 1'b0;`
245			`refill_first <= #1 1'b0;`
246			`refill_prepare <= #1 1'b0;`
247			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
248			`end`
249			`DCFSM_LREFILL3 : begin
250			`if (biudata_valid && (\|cnt)) begin`
251			`ifdef OR1200_VERBOSE
252			`// synopsys translate_off`
253			`$display("%t: DC_FSM Load refill %d", $time, cnt);`
254			`// synopsys translate_on`
255			`endif
256			`cnt <= #1 cnt - 'd1;`
257			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
258			`refill_first <= #1 1'b0;`
259			`end`
260			`else if (biudata_valid) begin`
261			`ifdef OR1200_VERBOSE
262			`// synopsys translate_off`
263			`$display("%t: DC_FSM Load refill end", $time, cnt);`
264			`// synopsys translate_on`
265			`endif
266			state <= #1 `DCFSM_IDLE;
267			`refill <= #1 1'b0;`
268			`refill_first <= #1 1'b0;`
269			`biu_read <= #1 1'b0;`
270			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
271			`end`
272			`refill_rest <= #1 ~refill_first & refill;`
273			`end`
274			`DCFSM_DOSTORE:
275			`if (miss) begin`
276			`ifdef OR1200_VERBOSE
277			`// synopsys translate_off`
278			`$display("%t: DC_FSM Store miss", $time);`
279			`// synopsys translate_on`
280			`endif
281			state <= #1 `DCFSM_SREFILL3;
282			`refill <= #1 1'b1;`
283			`refill_first <= #1 1'b1;`
284			`refill_prepare <= #1 1'b0;`
285			`cnt <= #1 3'd3;`
286			`biu_read <= #1 1'b1;`
287			`end`
288			`else begin`
289			`ifdef OR1200_VERBOSE
290			`// synopsys translate_off`
291			`$display("%t: DC_FSM Store hit", $time);`
292			`// synopsys translate_on`
293			`endif
294			state <= #1 `DCFSM_SMEMWR;
295			`refill <= #1 1'b1;`
296			`refill_first <= #1 1'b0;`
297			`refill_prepare <= #1 1'b0;`
298			`biu_write <= #1 1'b1;`
299			`biu_read <= #1 1'b0;`
300			`end`
301			`DCFSM_SREFILL3 : begin
302			`if (biudata_valid && (\|cnt)) begin`
303			`ifdef OR1200_VERBOSE
304			`// synopsys translate_off`
305			`$display("%t: DC_FSM Store refill %d", $time, cnt);`
306			`// synopsys translate_on`
307			`endif
308			`cnt <= #1 cnt - 'd1;`
309			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
310			`refill_first <= #1 1'b0;`
311			`end`
312			`else if (biudata_valid) begin`
313			`ifdef OR1200_VERBOSE
314			`// synopsys translate_off`
315			`$display("%t: DC_FSM Store refill almost done", $time);`
316			`// synopsys translate_on`
317			`endif
318			state <= #1 `DCFSM_SMEMWR;
319			`saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1;`
320			`biu_write <= #1 1'b1;`
321			`biu_read <= #1 1'b0;`
322			`end`
323			`refill_rest <= #1 ~refill_first & refill;`
324			`end`
325			`DCFSM_SMEMWR :
326			`if (biudata_valid) begin`
327			`ifdef OR1200_VERBOSE
328			`// synopsys translate_off`
329			`$display("%t: DC_FSM Store refill end (just finished store to external mem)", $time);`
330			`// synopsys translate_on`
331			`endif
332			state <= #1 `DCFSM_IDLE;
333			`refill <= #1 1'b0;`
334			`biu_write <= #1 1'b0;`
335			`cntrbusy <= #1 (lsu_op) ? 1'b1 : 1'b0;`
336			`end`
337			`endcase`
338			`end`
339
340			`endmodule`