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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Freeze logic                                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Generates all freezes and stalls inside RISC                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`define NO_FREEZE       3'd0
`define FREEZE_BYDC     3'd1
`define FREEZE_BYMULTICYCLE     3'd2
`define WAIT_LSU_TO_FINISH      3'd3
`define WAIT_IC                 3'd4
 
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module frz_logic(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        multicycle, except_flushpipe, lsu_stall, if_stall,
        dclsu_unstall, branch_stall, du_stall, mac_stall,
        force_dslot_fetch,
        if_freeze, id_freeze, ex_freeze, wb_freeze
);
 
//
// I/O
//
input                           clk;
input                           rst;
input   [`MULTICYCLE_WIDTH-1:0]  multicycle;
input                           except_flushpipe;
input                           lsu_stall;
input                           if_stall;
input                           dclsu_unstall;
input                           branch_stall;
input                           force_dslot_fetch;
input                           du_stall;
input                           mac_stall;
output                          if_freeze;
output                          id_freeze;
output                          ex_freeze;
output                          wb_freeze;
 
//
// Internal wires and regs
//
reg                             multicycle_freeze;
reg     [2:0]                    state2;
reg     [2:0]                    multicycle_cnt;
reg                             done_once;
 
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Frreze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
assign if_freeze = id_freeze;
assign id_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~except_flushpipe | du_stall;
assign ex_freeze = wb_freeze;
assign wb_freeze = (lsu_stall | (~dclsu_unstall & if_stall) | multicycle_freeze) & ~except_flushpipe | du_stall | mac_stall;
 
//
// Freeze FSM2
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state2 <= #1 `NO_FREEZE;
                multicycle_freeze <= #1 1'b1;
                multicycle_cnt <= #1 3'b0;
                done_once <= #1 1'b0;
        end
        else
                case (state2)   // synopsys full_case parallel_case
                `NO_FREEZE :
                        if (done_once && ex_freeze)
                                done_once <= #1 1'b1;
                        else if (multicycle) begin
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
                                done_once <= #1 1'b0;
                        end
                        else
                                multicycle_freeze <= #1 1'b0;
                `FREEZE_BYMULTICYCLE :
                        if (multicycle_cnt) begin
                                multicycle_cnt <= #1 multicycle_cnt - 'd1;
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                        end
                        else if (lsu_stall) begin
                                state2 <= #1 `WAIT_LSU_TO_FINISH;
                                multicycle_freeze <= #1 1'b0;
                        end
                        else if (if_stall) begin
                                state2 <= #1 `NO_FREEZE;
                                done_once <= #1 1'b1;
                                multicycle_freeze <= #1 1'b0;
                        end
                        else begin
                                state2 <= #1 `NO_FREEZE;
                                multicycle_freeze <= #1 1'b0;
                        end
                `WAIT_LSU_TO_FINISH:
                        if (!lsu_stall && !(|multicycle)) begin
                                state2 <= #1 `NO_FREEZE;
                        end
                        else if (!lsu_stall & (|multicycle)) begin
                                state2 <= #1 `FREEZE_BYMULTICYCLE;
                                multicycle_freeze <= #1 1'b1;
                                multicycle_cnt <= #1 multicycle - 'd1;
                        end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Freeze logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Generates all freezes and stalls inside RISC ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:03 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`define NO_FREEZE 3'd0
64			`define FREEZE_BYDC 3'd1
65			`define FREEZE_BYMULTICYCLE 3'd2
66			`define WAIT_LSU_TO_FINISH 3'd3
67			`define WAIT_IC 3'd4
68
69			`//`
70			`// Freeze logic (stalls CPU pipeline, ifetcher etc.)`
71			`//`
72			`module frz_logic(`
73			`// Clock and reset`
74			`clk, rst,`
75
76			`// Internal i/f`
77			`multicycle, except_flushpipe, lsu_stall, if_stall,`
78			`dclsu_unstall, branch_stall, du_stall, mac_stall,`
79			`force_dslot_fetch,`
80			`if_freeze, id_freeze, ex_freeze, wb_freeze`
81			`);`
82
83			`//`
84			`// I/O`
85			`//`
86			`input clk;`
87			`input rst;`
88			input [`MULTICYCLE_WIDTH-1:0] multicycle;
89			`input except_flushpipe;`
90			`input lsu_stall;`
91			`input if_stall;`
92			`input dclsu_unstall;`
93			`input branch_stall;`
94			`input force_dslot_fetch;`
95			`input du_stall;`
96			`input mac_stall;`
97			`output if_freeze;`
98			`output id_freeze;`
99			`output ex_freeze;`
100			`output wb_freeze;`
101
102			`//`
103			`// Internal wires and regs`
104			`//`
105			`reg multicycle_freeze;`
106			`reg [2:0] state2;`
107			`reg [2:0] multicycle_cnt;`
108			`reg done_once;`
109
110			`//`
111			`// Pipeline freeze`
112			`//`
113			`// Rules how to create freeze signals:`
114			`// 1. Not overwriting pipeline stages:`
115			`// Frreze signals at the beginning of pipeline (such as if_freeze) can be asserted more`
116			`// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never`
117			`// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.`
118			`//`
119			`// 2. Inserting NOPs in the middle of pipeline only if supported:`
120			`// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.`
121			`// This way NOP is asserted from stage ID into EX stage.`
122			`//`
123			`assign if_freeze = id_freeze;`
124			`assign id_freeze = (lsu_stall \| (~dclsu_unstall & if_stall) \| multicycle_freeze \| force_dslot_fetch) & ~except_flushpipe \| du_stall;`
125			`assign ex_freeze = wb_freeze;`
126			`assign wb_freeze = (lsu_stall \| (~dclsu_unstall & if_stall) \| multicycle_freeze) & ~except_flushpipe \| du_stall \| mac_stall;`
127
128			`//`
129			`// Freeze FSM2`
130			`//`
131			`always @(posedge clk or posedge rst) begin`
132			`if (rst) begin`
133			state2 <= #1 `NO_FREEZE;
134			`multicycle_freeze <= #1 1'b1;`
135			`multicycle_cnt <= #1 3'b0;`
136			`done_once <= #1 1'b0;`
137			`end`
138			`else`
139			`case (state2) // synopsys full_case parallel_case`
140			`NO_FREEZE :
141			`if (done_once && ex_freeze)`
142			`done_once <= #1 1'b1;`
143			`else if (multicycle) begin`
144			state2 <= #1 `FREEZE_BYMULTICYCLE;
145			`multicycle_freeze <= #1 1'b1;`
146			`multicycle_cnt <= #1 multicycle - 'd1;`
147			`done_once <= #1 1'b0;`
148			`end`
149			`else`
150			`multicycle_freeze <= #1 1'b0;`
151			`FREEZE_BYMULTICYCLE :
152			`if (multicycle_cnt) begin`
153			`multicycle_cnt <= #1 multicycle_cnt - 'd1;`
154			state2 <= #1 `FREEZE_BYMULTICYCLE;
155			`end`
156			`else if (lsu_stall) begin`
157			state2 <= #1 `WAIT_LSU_TO_FINISH;
158			`multicycle_freeze <= #1 1'b0;`
159			`end`
160			`else if (if_stall) begin`
161			state2 <= #1 `NO_FREEZE;
162			`done_once <= #1 1'b1;`
163			`multicycle_freeze <= #1 1'b0;`
164			`end`
165			`else begin`
166			state2 <= #1 `NO_FREEZE;
167			`multicycle_freeze <= #1 1'b0;`
168			`end`
169			`WAIT_LSU_TO_FINISH:
170			`if (!lsu_stall && !(\|multicycle)) begin`
171			state2 <= #1 `NO_FREEZE;
172			`end`
173			`else if (!lsu_stall & (\|multicycle)) begin`
174			state2 <= #1 `FREEZE_BYMULTICYCLE;
175			`multicycle_freeze <= #1 1'b1;`
176			`multicycle_cnt <= #1 multicycle - 'd1;`
177			`end`
178			`endcase`
179			`end`
180
181			`endmodule`

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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [frz_logic.v] - Blame information for rev 1765