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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Two-Port Synchronous RAM                            ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common two-port                ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  two-port synchronous RAM.                                   ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module generic_tpram_32x32(
        // Generic synchronous two-port RAM interface
        clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
        clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous two-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   we_a;   // Write enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
input   [dw-1:0] di_a;   // input data bus
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input                   oe_b;   // Output enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
output  [dw-1:0] do_b;   // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(~we_a),
        .aa(addr_a),
        .da(di_a),
        .oena(~oe_a),
        .qb(do_b),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(~oe_b)
);
 
`else
 
`ifdef AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(do_b),
 
        .ADRA(addr_a),
        .DA(di_a),
        .WEA(we_a),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(adr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(oe_b),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[15:0]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[15:0])
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[31:16]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[31:16])
);
 
`else
 
//
// Generic two-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg_a;               // RAM data output register
reg     [dw-1:0] do_reg_b;               // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk_a)
        if (ce_a && !we_a)
                do_reg_a <= #1 mem[addr_a];
        else if (ce_a && we_a)
                mem[addr_a] <= #1 di_a;
 
//
// RAM read and write
//
always @(posedge clk_b)
        if (ce_b && !we_b)
                do_reg_b <= #1 mem[addr_b];
        else if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
`endif  // !XILINX_RAMB4_S16_S16
`endif  // !VIRAGE_STP
`endif  // !AVANT_ATP
`endif  // !ARTISAN_SDP
 
endmodule

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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [generic_tpram_32x32.v] - Blame information for rev 769

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Two-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common two-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// two-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35			`//// ////`
36			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
37			`//// ////`
38			`//// This source file may be used and distributed without ////`
39			`//// restriction provided that this copyright statement is not ////`
40			`//// removed from the file and that any derivative work contains ////`
41			`//// the original copyright notice and the associated disclaimer. ////`
42			`//// ////`
43			`//// This source file is free software; you can redistribute it ////`
44			`//// and/or modify it under the terms of the GNU Lesser General ////`
45			`//// Public License as published by the Free Software Foundation; ////`
46			`//// either version 2.1 of the License, or (at your option) any ////`
47			`//// later version. ////`
48			`//// ////`
49			`//// This source is distributed in the hope that it will be ////`
50			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
51			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
52			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
53			`//// details. ////`
54			`//// ////`
55			`//// You should have received a copy of the GNU Lesser General ////`
56			`//// Public License along with this source; if not, download it ////`
57			`//// from http://www.opencores.org/lgpl.shtml ////`
58			`//// ////`
59			`//////////////////////////////////////////////////////////////////////`
60			`//`
61			`// CVS Revision History`
62			`//`
63			`// $Log: not supported by cvs2svn $`
64			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
65			`// no message`
66			`//`
67			`// Revision 1.1 2001/08/09 13:39:33 lampret`
68			`// Major clean-up.`
69			`//`
70			`// Revision 1.2 2001/07/30 05:38:02 lampret`
71			`// Adding empty directories required by HDL coding guidelines`
72			`//`
73			`//`
74
75			`// synopsys translate_off`
76			`include "timescale.v"
77			`// synopsys translate_on`
78			`include "defines.v"
79
80			`module generic_tpram_32x32(`
81			`// Generic synchronous two-port RAM interface`
82			`clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,`
83			`clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b`
84			`);`
85
86			`//`
87			`// Default address and data buses width`
88			`//`
89			`parameter aw = 5;`
90			`parameter dw = 32;`
91
92			`//`
93			`// Generic synchronous two-port RAM interface`
94			`//`
95			`input clk_a; // Clock`
96			`input rst_a; // Reset`
97			`input ce_a; // Chip enable input`
98			`input we_a; // Write enable input`
99			`input oe_a; // Output enable input`
100			`input [aw-1:0] addr_a; // address bus inputs`
101			`input [dw-1:0] di_a; // input data bus`
102			`output [dw-1:0] do_a; // output data bus`
103			`input clk_b; // Clock`
104			`input rst_b; // Reset`
105			`input ce_b; // Chip enable input`
106			`input we_b; // Write enable input`
107			`input oe_b; // Output enable input`
108			`input [aw-1:0] addr_b; // address bus inputs`
109			`input [dw-1:0] di_b; // input data bus`
110			`output [dw-1:0] do_b; // output data bus`
111
112			`//`
113			`// Internal wires and registers`
114			`//`
115
116
117			`ifdef ARTISAN_SDP
118
119			`//`
120			`// Instantiation of ASIC memory:`
121			`//`
122			`// Artisan Synchronous Double-Port RAM (ra2sh)`
123			`//`
124			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
125			`.qa(do_a),`
126			`.clka(clk_a),`
127			`.cena(~ce_a),`
128			`.wena(~we_a),`
129			`.aa(addr_a),`
130			`.da(di_a),`
131			`.oena(~oe_a),`
132			`.qb(do_b),`
133			`.clkb(clk_b),`
134			`.cenb(~ce_b),`
135			`.wenb(~we_b),`
136			`.ab(addr_b),`
137			`.db(di_b),`
138			`.oenb(~oe_b)`
139			`);`
140
141			`else
142
143			`ifdef AVANT_ATP
144
145			`//`
146			`// Instantiation of ASIC memory:`
147			`//`
148			`// Avant! Asynchronous Two-Port RAM`
149			`//`
150			`avant_atp avant_atp(`
151			`.web(~we),`
152			`.reb(),`
153			`.oeb(~oe),`
154			`.rcsb(),`
155			`.wcsb(),`
156			`.ra(addr),`
157			`.wa(addr),`
158			`.di(di),`
159			`.do(do)`
160			`);`
161
162			`else
163
164			`ifdef VIRAGE_STP
165
166			`//`
167			`// Instantiation of ASIC memory:`
168			`//`
169			`// Virage Synchronous 2-port R/W RAM`
170			`//`
171			`virage_stp virage_stp(`
172			`.QA(do_a),`
173			`.QB(do_b),`
174
175			`.ADRA(addr_a),`
176			`.DA(di_a),`
177			`.WEA(we_a),`
178			`.OEA(oe_a),`
179			`.MEA(ce_a),`
180			`.CLKA(clk_a),`
181
182			`.ADRB(adr_b),`
183			`.DB(di_b),`
184			`.WEB(we_b),`
185			`.OEB(oe_b),`
186			`.MEB(ce_b),`
187			`.CLKB(clk_b)`
188			`);`
189
190			`else
191
192			`ifdef XILINX_RAMB4
193
194			`//`
195			`// Instantiation of FPGA memory:`
196			`//`
197			`// Virtex/Spartan2`
198			`//`
199
200			`//`
201			`// Block 0`
202			`//`
203			`RAMB4_S16_S16 ramb4_s16_s16_0(`
204			`.CLKA(clk_a),`
205			`.RSTA(rst_a),`
206			`.ADDRA(addr_a),`
207			`.DIA(di_a[15:0]),`
208			`.ENA(ce_a),`
209			`.WEA(we_a),`
210			`.DOA(do_a[15:0]),`
211
212			`.CLKB(clk_b),`
213			`.RSTB(rst_b),`
214			`.ADDRB(addr_b),`
215			`.DIB(di_b[15:0]),`
216			`.ENB(ce_b),`
217			`.WEB(we_b),`
218			`.DOB(do_b[15:0])`
219			`);`
220
221			`//`
222			`// Block 1`
223			`//`
224			`RAMB4_S16_S16 ramb4_s16_s16_1(`
225			`.CLKA(clk_a),`
226			`.RSTA(rst_a),`
227			`.ADDRA(addr_a),`
228			`.DIA(di_a[31:16]),`
229			`.ENA(ce_a),`
230			`.WEA(we_a),`
231			`.DOA(do_a[31:16]),`
232
233			`.CLKB(clk_b),`
234			`.RSTB(rst_b),`
235			`.ADDRB(addr_b),`
236			`.DIB(di_b[31:16]),`
237			`.ENB(ce_b),`
238			`.WEB(we_b),`
239			`.DOB(do_b[31:16])`
240			`);`
241
242			`else
243
244			`//`
245			`// Generic two-port synchronous RAM model`
246			`//`
247
248			`//`
249			`// Generic RAM's registers and wires`
250			`//`
251			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
252			`reg [dw-1:0] do_reg_a; // RAM data output register`
253			`reg [dw-1:0] do_reg_b; // RAM data output register`
254
255			`//`
256			`// Data output drivers`
257			`//`
258			`assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};`
259			`assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};`
260
261			`//`
262			`// RAM read and write`
263			`//`
264			`always @(posedge clk_a)`
265			`if (ce_a && !we_a)`
266			`do_reg_a <= #1 mem[addr_a];`
267			`else if (ce_a && we_a)`
268			`mem[addr_a] <= #1 di_a;`
269
270			`//`
271			`// RAM read and write`
272			`//`
273			`always @(posedge clk_b)`
274			`if (ce_b && !we_b)`
275			`do_reg_b <= #1 mem[addr_b];`
276			`else if (ce_b && we_b)`
277			`mem[addr_b] <= #1 di_b;`
278
279			`endif // !XILINX_RAMB4_S16_S16
280			`endif // !VIRAGE_STP
281			`endif // !AVANT_ATP
282			`endif // !ARTISAN_SDP
283
284			`endmodule`