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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Programmable Interrupt Controller                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PIC according to OR1K architectural specification.          ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module pic(
        // RISC Internal Interface
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        pic_wakeup, int_low, int_high,
 
        // PIC Interface
        pic_int
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          pic_wakeup;     // Wakeup to the PM
output          int_low;        // Low priority interrupt
                                // exception request
output          int_high;       // High priority interrupt
                                // exception request
 
//
// PIC Interface
//
input   [`PIC_INTS-1:0]  pic_int;// Interrupt inputs
 
`ifdef PIC_IMPLEMENTED
 
//
// PIC Mask Register bits (or no register)
//
`ifdef PIC_PICMR
reg     [`PIC_INTS-1:2] picmr;  // PICMR bits
`else
wire    [`PIC_INTS-1:2] picmr;  // No PICMR register
`endif
 
//
// PIC Priority Register bits (or no register)
//
`ifdef PIC_PICPR
reg     [`PIC_INTS-1:2] picpr;  // PICPR bits
`else
wire    [`PIC_INTS-1:2] picpr;  // No PICPR register
`endif
 
//
// PIC Status Register bits (or no register)
//
`ifdef PIC_PICSR
reg     [`PIC_INTS-1:0]  picsr;  // PICSR bits
`else
wire    [`PIC_INTS-1:0]  picsr;  // No PICSR register
`endif
 
//
// Internal wires & regs
//
wire            picmr_sel;      // PICMR select
wire            picpr_sel;      // PICPR select
wire            picsr_sel;      // PICSR select
wire    [`PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picpr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICPR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
 
//
// Write to PICMR
//
`ifdef PIC_PICMR
always @(posedge clk or posedge rst)
        if (rst)
//              picmr <= {`PIC_INTS-2{1'b0}};
                picmr <= {1'b1, {`PIC_INTS-3{1'b0}}};
        else if (picmr_sel && spr_write) begin
                picmr <= #1 spr_dat_i[`PIC_INTS-1:2];
        end
`else
assign picpr = (`PIC_INTS)'b1;
`endif
 
//
// Write to PICPR
//
`ifdef PIC_PICPR
always @(posedge clk or posedge rst)
        if (rst)
                picpr <= {`PIC_INTS-2{1'b0}};
        else if (picpr_sel && spr_write) begin
                picpr <= #1 spr_dat_i[`PIC_INTS-1:2];
        end
`else
assign picpr = 0;
`endif
 
//
// Write to PICSR, both CPU and external ints
//
`ifdef PIC_PICSR
always @(posedge clk or posedge rst)
        if (rst)
                picsr <= {`PIC_INTS-2{1'b0}};
        else if (picsr_sel && spr_write) begin
                picsr <= #1 spr_dat_i[`PIC_INTS-1:0] | um_ints;
        end else
                picsr <= #1 picsr | um_ints;
`else
assign picsr = pic_int;
`endif
 
//
// Read PIC registers
//
always @(spr_addr or picmr or picpr or picsr)
        case (spr_addr[`PICOFS_BITS])   // synopsys full_case parallel_case
`ifdef PIC_READREGS
                `PIC_OFS_PICMR: begin
                                        spr_dat_o[`PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef PIC_UNUSED_ZERO
                                        spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
`endif
                                end
                `PIC_OFS_PICPR: begin
                                        spr_dat_o[`PIC_INTS-1:0] = {picpr, 2'b0};
`ifdef PIC_UNUSED_ZERO
                                        spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
`endif
                                end
`endif
                default: begin
                                spr_dat_o[`PIC_INTS-1:0] = picsr;
`ifdef PIC_UNUSED_ZERO
                                spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
`endif
                        end
        endcase
 
//
// Unmasked interrupts
//
assign um_ints = pic_int & {picmr, 2'b11};
 
//
// Generate int_low
//
assign int_low = (um_ints & {~picpr, 2'b10}) ? 1'b1 : 1'b0;
 
//
// Generate int_high
//
assign int_high = (um_ints & {picpr, 2'b01}) ? 1'b1 : 1'b0;
 
//
// Assert pic_wakeup when either intlow or int_high is asserted
//
assign pic_wakeup = int_low | int_high;
 
`else
 
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign int_low = pic_int[1];
assign int_high = pic_int[0];
assign pic_wakeup= int_low | int_high;
 
//
// Read PIC registers
//
`ifdef PIC_READREGS
assign spr_dat_o[`PIC_INTS-1:0] = `PIC_INTS'b0;
`ifdef PIC_UNUSED_ZERO
assign spr_dat_o[31:`PIC_INTS] = 32-`PIC_INTS'b0;
`endif
`endif
 
`endif
 
endmodule

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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [pic.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Programmable Interrupt Controller ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PIC according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:21 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`module pic(`
64			`// RISC Internal Interface`
65			`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
66			`pic_wakeup, int_low, int_high,`
67
68			`// PIC Interface`
69			`pic_int`
70			`);`
71
72			`//`
73			`// RISC Internal Interface`
74			`//`
75			`input clk; // Clock`
76			`input rst; // Reset`
77			`input spr_cs; // SPR CS`
78			`input spr_write; // SPR Write`
79			`input [31:0] spr_addr; // SPR Address`
80			`input [31:0] spr_dat_i; // SPR Write Data`
81			`output [31:0] spr_dat_o; // SPR Read Data`
82			`output pic_wakeup; // Wakeup to the PM`
83			`output int_low; // Low priority interrupt`
84			`// exception request`
85			`output int_high; // High priority interrupt`
86			`// exception request`
87
88			`//`
89			`// PIC Interface`
90			`//`
91			input [`PIC_INTS-1:0] pic_int;// Interrupt inputs
92
93			`ifdef PIC_IMPLEMENTED
94
95			`//`
96			`// PIC Mask Register bits (or no register)`
97			`//`
98			`ifdef PIC_PICMR
99			reg [`PIC_INTS-1:2] picmr; // PICMR bits
100			`else
101			wire [`PIC_INTS-1:2] picmr; // No PICMR register
102			`endif
103
104			`//`
105			`// PIC Priority Register bits (or no register)`
106			`//`
107			`ifdef PIC_PICPR
108			reg [`PIC_INTS-1:2] picpr; // PICPR bits
109			`else
110			wire [`PIC_INTS-1:2] picpr; // No PICPR register
111			`endif
112
113			`//`
114			`// PIC Status Register bits (or no register)`
115			`//`
116			`ifdef PIC_PICSR
117			reg [`PIC_INTS-1:0] picsr; // PICSR bits
118			`else
119			wire [`PIC_INTS-1:0] picsr; // No PICSR register
120			`endif
121
122			`//`
123			`// Internal wires & regs`
124			`//`
125			`wire picmr_sel; // PICMR select`
126			`wire picpr_sel; // PICPR select`
127			`wire picsr_sel; // PICSR select`
128			wire [`PIC_INTS-1:0] um_ints;// Unmasked interrupts
129			`reg [31:0] spr_dat_o; // SPR data out`
130
131			`//`
132			`// PIC registers address decoder`
133			`//`
134			assign picmr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
135			assign picpr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICPR)) ? 1'b1 : 1'b0;
136			assign picsr_sel = (spr_cs && (spr_addr[`PICOFS_BITS] == `PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
137
138			`//`
139			`// Write to PICMR`
140			`//`
141			`ifdef PIC_PICMR
142			`always @(posedge clk or posedge rst)`
143			`if (rst)`
144			// picmr <= {`PIC_INTS-2{1'b0}};
145			picmr <= {1'b1, {`PIC_INTS-3{1'b0}}};
146			`else if (picmr_sel && spr_write) begin`
147			picmr <= #1 spr_dat_i[`PIC_INTS-1:2];
148			`end`
149			`else
150			assign picpr = (`PIC_INTS)'b1;
151			`endif
152
153			`//`
154			`// Write to PICPR`
155			`//`
156			`ifdef PIC_PICPR
157			`always @(posedge clk or posedge rst)`
158			`if (rst)`
159			picpr <= {`PIC_INTS-2{1'b0}};
160			`else if (picpr_sel && spr_write) begin`
161			picpr <= #1 spr_dat_i[`PIC_INTS-1:2];
162			`end`
163			`else
164			`assign picpr = 0;`
165			`endif
166
167			`//`
168			`// Write to PICSR, both CPU and external ints`
169			`//`
170			`ifdef PIC_PICSR
171			`always @(posedge clk or posedge rst)`
172			`if (rst)`
173			picsr <= {`PIC_INTS-2{1'b0}};
174			`else if (picsr_sel && spr_write) begin`
175			picsr <= #1 spr_dat_i[`PIC_INTS-1:0] \| um_ints;
176			`end else`
177			`picsr <= #1 picsr \| um_ints;`
178			`else
179			`assign picsr = pic_int;`
180			`endif
181
182			`//`
183			`// Read PIC registers`
184			`//`
185			`always @(spr_addr or picmr or picpr or picsr)`
186			case (spr_addr[`PICOFS_BITS]) // synopsys full_case parallel_case
187			`ifdef PIC_READREGS
188			`PIC_OFS_PICMR: begin
189			spr_dat_o[`PIC_INTS-1:0] = {picmr, 2'b0};
190			`ifdef PIC_UNUSED_ZERO
191			spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
192			`endif
193			`end`
194			`PIC_OFS_PICPR: begin
195			spr_dat_o[`PIC_INTS-1:0] = {picpr, 2'b0};
196			`ifdef PIC_UNUSED_ZERO
197			spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
198			`endif
199			`end`
200			`endif
201			`default: begin`
202			spr_dat_o[`PIC_INTS-1:0] = picsr;
203			`ifdef PIC_UNUSED_ZERO
204			spr_dat_o[31:`PIC_INTS] = {32-`PIC_INTS{1'b0}};
205			`endif
206			`end`
207			`endcase`
208
209			`//`
210			`// Unmasked interrupts`
211			`//`
212			`assign um_ints = pic_int & {picmr, 2'b11};`
213
214			`//`
215			`// Generate int_low`
216			`//`
217			`assign int_low = (um_ints & {~picpr, 2'b10}) ? 1'b1 : 1'b0;`
218
219			`//`
220			`// Generate int_high`
221			`//`
222			`assign int_high = (um_ints & {picpr, 2'b01}) ? 1'b1 : 1'b0;`
223
224			`//`
225			`// Assert pic_wakeup when either intlow or int_high is asserted`
226			`//`
227			`assign pic_wakeup = int_low \| int_high;`
228
229			`else
230
231			`//`
232			`// When PIC is not implemented, drive all outputs as would when PIC is disabled`
233			`//`
234			`assign int_low = pic_int[1];`
235			`assign int_high = pic_int[0];`
236			`assign pic_wakeup= int_low \| int_high;`
237
238			`//`
239			`// Read PIC registers`
240			`//`
241			`ifdef PIC_READREGS
242			assign spr_dat_o[`PIC_INTS-1:0] = `PIC_INTS'b0;
243			`ifdef PIC_UNUSED_ZERO
244			assign spr_dat_o[31:`PIC_INTS] = 32-`PIC_INTS'b0;
245			`endif
246			`endif
247
248			`endif
249
250			`endmodule`