URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [rf.v] - Blame information for rev 1765

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file inside CPU                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of register file memories                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module rf(
        // Clock and reset
        clk, rst,
 
        // Write i/f
        addrw, dataw, we,
 
        // Read i/f
        id_freeze, addra, addrb, dataa, datab,
 
        // Debug
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `REGFILE_ADDR_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Write i/f
//
input   [aw-1:0]         addrw;
input   [dw-1:0]         dataw;
input                           we;
 
//
// Read i/f
//
input                           id_freeze;
input   [aw-1:0]         addra;
input   [aw-1:0]         addrb;
output  [dw-1:0]         dataa;
output  [dw-1:0]         datab;
 
//
// SPR access for debugging purposes
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [dw-1:0]         from_rfa;
wire    [dw-1:0]         from_rfb;
reg     [dw:0]                   dataa_saved;
reg     [dw:0]                   datab_saved;
wire    [aw-1:0]         rf_addra;
wire    [aw-1:0]         rf_addrw;
wire    [dw-1:0]         rf_dataw;
wire                            rf_we;
wire                            spr_valid;
 
//
// SPR access is valid when spr_cs is asserted and
// SPR address matches GPR addresses
//
assign spr_valid = spr_cs & (spr_addr[10:5] == `SPR_RF);
 
//
// SPR data output is always from RF A
//
assign spr_dat_o = from_rfa;
 
//
// Operand A comes from RF or from saved A register
//
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
 
//
// Operand B comes from RF or from saved B register
//
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
 
//
// RF A read address is either from SPRS or normal from CPU control
//
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
 
//
// RF write address is either from SPRS or normal from CPU control
//
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
 
//
// RF write data is either from SPRS or normal from CPU datapath
//
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
 
//
// RF write enable is either from SPRS or normal from CPU control
//
assign rf_we = (spr_valid & spr_write) | we;
 
//
// Stores operand from RF_A into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
        if (rst) begin
                dataa_saved <= #1 33'b0;
        end
        else if (id_freeze & !dataa_saved[32]) begin
                dataa_saved <= #1 {1'b1, from_rfa};
        end
        else if (!id_freeze)
                dataa_saved <= #1 33'b0;
 
//
// Stores operand from RF_B into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
        if (rst) begin
                datab_saved <= #1 33'b0;
        end
        else if (id_freeze & !datab_saved[32]) begin
                datab_saved <= #1 {1'b1, from_rfb};
        end
        else if (!id_freeze)
                datab_saved <= #1 33'b0;
 
//
// Instantiation of register file two-port RAM A
//
generic_dpram_32x32 rf_a(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(1'b1),
//      .we_a(1'b0),
        .oe_a(1'b1),
        .addr_a(rf_addra),
//      .di_a(32'h0000_0000),
        .do_a(from_rfa),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(rf_we),
        .we_b(rf_we),
//      .oe_b(1'b0),
        .addr_b(rf_addrw),
        .di_b(rf_dataw)
//      .do_b()
);
 
//
// Instantiation of register file two-port RAM B
//
generic_dpram_32x32 rf_b(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(1'b1),
//      .we_a(1'b0),
        .oe_a(1'b1),
        .addr_a(addrb),
//      .di_a(32'h0000_0000),
        .do_a(from_rfb),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(rf_we),
        .we_b(rf_we),
//      .oe_b(1'b0),
        .addr_b(rf_addrw),
        .di_b(rf_dataw)
//      .do_b()
);
 
endmodule

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [rf.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file inside CPU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of register file memories ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.3 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.2 2001/07/22 03:31:54 lampret`
54			`// Fixed RAM's oen bug. Cache bypass under development.`
55			`//`
56			`// Revision 1.1 2001/07/20 00:46:21 lampret`
57			`// Development version of RTL. Libraries are missing.`
58			`//`
59			`//`
60
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64			`include "defines.v"
65
66			`module rf(`
67			`// Clock and reset`
68			`clk, rst,`
69
70			`// Write i/f`
71			`addrw, dataw, we,`
72
73			`// Read i/f`
74			`id_freeze, addra, addrb, dataa, datab,`
75
76			`// Debug`
77			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
78			`);`
79
80			parameter dw = `OPERAND_WIDTH;
81			parameter aw = `REGFILE_ADDR_WIDTH;
82
83			`//`
84			`// I/O`
85			`//`
86
87			`//`
88			`// Clock and reset`
89			`//`
90			`input clk;`
91			`input rst;`
92
93			`//`
94			`// Write i/f`
95			`//`
96			`input [aw-1:0] addrw;`
97			`input [dw-1:0] dataw;`
98			`input we;`
99
100			`//`
101			`// Read i/f`
102			`//`
103			`input id_freeze;`
104			`input [aw-1:0] addra;`
105			`input [aw-1:0] addrb;`
106			`output [dw-1:0] dataa;`
107			`output [dw-1:0] datab;`
108
109			`//`
110			`// SPR access for debugging purposes`
111			`//`
112			`input spr_cs;`
113			`input spr_write;`
114			`input [31:0] spr_addr;`
115			`input [31:0] spr_dat_i;`
116			`output [31:0] spr_dat_o;`
117
118			`//`
119			`// Internal wires and regs`
120			`//`
121			`wire [dw-1:0] from_rfa;`
122			`wire [dw-1:0] from_rfb;`
123			`reg [dw:0] dataa_saved;`
124			`reg [dw:0] datab_saved;`
125			`wire [aw-1:0] rf_addra;`
126			`wire [aw-1:0] rf_addrw;`
127			`wire [dw-1:0] rf_dataw;`
128			`wire rf_we;`
129			`wire spr_valid;`
130
131			`//`
132			`// SPR access is valid when spr_cs is asserted and`
133			`// SPR address matches GPR addresses`
134			`//`
135			assign spr_valid = spr_cs & (spr_addr[10:5] == `SPR_RF);
136
137			`//`
138			`// SPR data output is always from RF A`
139			`//`
140			`assign spr_dat_o = from_rfa;`
141
142			`//`
143			`// Operand A comes from RF or from saved A register`
144			`//`
145			`assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;`
146
147			`//`
148			`// Operand B comes from RF or from saved B register`
149			`//`
150			`assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;`
151
152			`//`
153			`// RF A read address is either from SPRS or normal from CPU control`
154			`//`
155			`assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;`
156
157			`//`
158			`// RF write address is either from SPRS or normal from CPU control`
159			`//`
160			`assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;`
161
162			`//`
163			`// RF write data is either from SPRS or normal from CPU datapath`
164			`//`
165			`assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;`
166
167			`//`
168			`// RF write enable is either from SPRS or normal from CPU control`
169			`//`
170			`assign rf_we = (spr_valid & spr_write) \| we;`
171
172			`//`
173			`// Stores operand from RF_A into temp reg when pipeline is frozen`
174			`//`
175			`always @(posedge clk or posedge rst)`
176			`if (rst) begin`
177			`dataa_saved <= #1 33'b0;`
178			`end`
179			`else if (id_freeze & !dataa_saved[32]) begin`
180			`dataa_saved <= #1 {1'b1, from_rfa};`
181			`end`
182			`else if (!id_freeze)`
183			`dataa_saved <= #1 33'b0;`
184
185			`//`
186			`// Stores operand from RF_B into temp reg when pipeline is frozen`
187			`//`
188			`always @(posedge clk or posedge rst)`
189			`if (rst) begin`
190			`datab_saved <= #1 33'b0;`
191			`end`
192			`else if (id_freeze & !datab_saved[32]) begin`
193			`datab_saved <= #1 {1'b1, from_rfb};`
194			`end`
195			`else if (!id_freeze)`
196			`datab_saved <= #1 33'b0;`
197
198			`//`
199			`// Instantiation of register file two-port RAM A`
200			`//`
201			`generic_dpram_32x32 rf_a(`
202			`// Port A`
203			`.clk_a(clk),`
204			`.rst_a(rst),`
205			`.ce_a(1'b1),`
206			`// .we_a(1'b0),`
207			`.oe_a(1'b1),`
208			`.addr_a(rf_addra),`
209			`// .di_a(32'h0000_0000),`
210			`.do_a(from_rfa),`
211
212			`// Port B`
213			`.clk_b(clk),`
214			`.rst_b(rst),`
215			`.ce_b(rf_we),`
216			`.we_b(rf_we),`
217			`// .oe_b(1'b0),`
218			`.addr_b(rf_addrw),`
219			`.di_b(rf_dataw)`
220			`// .do_b()`
221			`);`
222
223			`//`
224			`// Instantiation of register file two-port RAM B`
225			`//`
226			`generic_dpram_32x32 rf_b(`
227			`// Port A`
228			`.clk_a(clk),`
229			`.rst_a(rst),`
230			`.ce_a(1'b1),`
231			`// .we_a(1'b0),`
232			`.oe_a(1'b1),`
233			`.addr_a(addrb),`
234			`// .di_a(32'h0000_0000),`
235			`.do_a(from_rfb),`
236
237			`// Port B`
238			`.clk_b(clk),`
239			`.rst_b(rst),`
240			`.ce_b(rf_we),`
241			`.we_b(rf_we),`
242			`// .oe_b(1'b0),`
243			`.addr_b(rf_addrw),`
244			`.di_b(rf_dataw)`
245			`// .do_b()`
246			`);`
247
248			`endmodule`