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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's interface to SPRs                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Decoding of SPR addresses and access to SPRs                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module sprs(
                // Clk & Rst
                clk, rst,
 
                // Internal CPU interface
                flag, addrbase, addrofs, dat_i, alu_op, branch_op,
                epcr, eear, esr, except_start, except_started,
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,
                spr_dat_cfgr, spr_dat_rf, spr_dat_pc,
 
                // From/to other RISC units
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
                spr_addr, spr_dataout, spr_cs, spr_we,
 
                du_addr, du_dat_du, du_read,
                du_write
 
);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O Ports
//
 
//
// Internal CPU interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input                           flag;           // From ALU
input   [width-1:0]              addrbase;       // SPR base address
input   [15:0]                   addrofs;        // SPR offset
input   [width-1:0]              dat_i;          // SPR write data
input   [`ALUOP_WIDTH-1:0]       alu_op;         // ALU operation
input   [`BRANCHOP_WIDTH-1:0]    branch_op;      // Branch operation
input   [width-1:0]              epcr;           // EPCR0
input   [width-1:0]              eear;           // EEAR0
input   [`SR_WIDTH-1:0]  esr;            // ESR0
input                           except_start;   // Start of exception
input                           except_started; // Exception was started
output  [width-1:0]              to_wbmux;       // For l.mfspr
output                          epcr_we;        // EPCR0 write enable
output                          eear_we;        // EEAR0 write enable
output                          esr_we;         // ESR0 write enable
output                          pc_we;          // PC write enable
output  [`SR_WIDTH-1:0]          sr;             // SR
input   [31:0]                   spr_dat_cfgr;   // Data from CFGR
input   [31:0]                   spr_dat_rf;     // Data from RF
input   [31:0]                   spr_dat_pc;     // Data from PC
 
//
// To/from other RISC units
//
input   [31:0]                   spr_dat_pic;    // Data from PIC
input   [31:0]                   spr_dat_tt;     // Data from TT
input   [31:0]                   spr_dat_pm;     // Data from PM
input   [31:0]                   spr_dat_dmmu;   // Data from DMMU
input   [31:0]                   spr_dat_immu;   // Data from IMMU
input   [31:0]                   spr_dat_du;     // Data from DU
output  [31:0]                   spr_addr;       // SPR Address
output  [31:0]                   spr_dataout;    // Data to unit
output  [31:0]                   spr_cs;         // Unit select
output                          spr_we;         // SPR write enable
 
//
// To/from Debug Unit
//
input   [width-1:0]              du_addr;        // Address
input   [width-1:0]              du_dat_du;      // Data from DU to SPRS
input                           du_read;        // Read qualifier
input                           du_write;       // Write qualifier
 
//
// Internal regs & wires
//
reg     [`SR_WIDTH-1:0]          sr;             // SR
reg                             write_spr;      // Write SPR
reg                             read_spr;       // Read SPR
reg     [width-1:0]              to_wbmux;       // For l.mfspr
wire                            sr_we;          // Write enable SR
wire                            cfgr_sel;       // Select for cfg regs
wire                            rf_sel;         // Select for RF
wire                            pc_sel;         // Select for PC
wire                            sr_sel;         // Select for SR        
wire                            epcr_sel;       // Select for EPCR0
wire                            eear_sel;       // Select for EEAR0
wire                            esr_sel;        // Select for ESR0
wire    [31:0]                   sys_data;       // Read data from system SPRs
wire    [`SR_WIDTH-1:0]          to_sr;          // Data to SR
wire                            du_access;      // Debug unit access
wire    [`ALUOP_WIDTH-1:0]       sprs_op;        // ALU operation
reg     [31:0]                   unqualified_cs; // Unqualified chip selects
 
//
// Decide if it is debug unit access
//
assign du_access = du_read | du_write;
 
//
// Generate sprs opcode
//
assign sprs_op = du_write ? `ALUOP_MTSR : du_read ? `ALUOP_MFSR : alu_op;
 
//
// Generate SPR address from base address and offset
// OR from debug unit address
//
assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};
 
//
// SPR is written with dat_i from l.mtspr
// OR by debug unit
//
assign spr_dataout = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
 
//
// Write into SPRs when l.mtspr
//
assign spr_we = du_write | write_spr;
 
//
// Qualify chip selects
//
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
 
//
// Decoding of groups
//
always @(spr_addr)
        case (spr_addr[`SPR_GROUP_BITS])        // synopsys parallel_case
                `SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
                `SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
                `SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
                `SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
                `SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
                `SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
                `SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
                `SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
                `SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
                `SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
                `SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
                `SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
                `SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
                `SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
                `SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
                `SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
                `SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
                `SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
                `SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
                `SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
                `SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
                `SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
                `SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
                `SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
        endcase
 
//
// SPRs System Group
//
 
//
// What to write into SR
//
assign to_sr = (branch_op == `BRANCHOP_RFE) ? esr : spr_dataout[`SR_WIDTH-1:0];
 
//
// Selects for system SPRs
//
assign cfgr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:4] == `SPR_CFGR));
assign rf_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:5] == `SPR_RF));
assign pc_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_PC));
assign sr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_SR));
assign epcr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_EPCR));
assign eear_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_EEAR));
assign esr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_ESR));
 
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `BRANCHOP_RFE);
assign pc_we = (write_spr && pc_sel);
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
assign esr_we = (write_spr && esr_sel);
 
//
// Output from system SPRs
//
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
                  (spr_dat_rf & {32{read_spr & rf_sel}}) |
                  (spr_dat_pc & {32{read_spr & pc_sel}}) |
                  ({{32-`SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
                  (epcr & {32{read_spr & epcr_sel}}) |
                  (eear & {32{read_spr & eear_sel}}) |
                  ({{32-`SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
 
//
// Supervision register
//
always @(posedge clk or posedge rst)
        if (rst)
                sr <= #1 `SR_WIDTH'b001;
        else if (except_started) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display(" INFO: exception started. SR[SUPV] set and SR[EXR] cleared.");
// synopsys translate_on
`endif
                sr[`SR_SUPV] <= #1 1'b1;
                sr[`SR_EXR] <= #1 1'b0;
                sr[`SR_WIDTH-1:2] <= #1 {`SR_WIDTH-2{1'b0}};
        end
        else if (sr_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                $display(" INFO: writing into SR register: %h", spr_dataout);
// synopsys translate_on
`endif
                sr <= #1 to_sr;
        end
 
//
// MTSPR/MFSPR interface
//
always @(sprs_op or spr_addr or spr_dataout or sys_data or spr_dat_pic or spr_dat_pm or
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
        case (sprs_op)  // synopsys full_case parallel_case
                `ALUOP_MTSR : begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, spr_dataout);
// synopsys translate_on
`endif
                        write_spr = 1'b1;
                        read_spr = 1'b0;
                        to_wbmux = 32'b0;
                end
                `ALUOP_MFSR : begin
                        casex (spr_addr[`SPR_GROUP_BITS])
                                `SPR_GROUP_TT:
                                        to_wbmux = spr_dat_tt;
                                `SPR_GROUP_PIC:
                                        to_wbmux = spr_dat_pic;
                                `SPR_GROUP_PM:
                                        to_wbmux = spr_dat_pm;
                                `SPR_GROUP_DMMU:
                                        to_wbmux = spr_dat_dmmu;
                                `SPR_GROUP_IMMU:
                                        to_wbmux = spr_dat_immu;
                                `SPR_GROUP_DU:
                                        to_wbmux = spr_dat_du;
                                `SPR_GROUP_SYS:
                                        to_wbmux = sys_data;
                                default:
                                        to_wbmux = 32'b0;
                        endcase
                        write_spr = 1'b0;
                        read_spr = 1'b1;
                end
                default : begin
                        write_spr = 1'b0;
                        read_spr = 1'b0;
                        to_wbmux = 32'b0;
                end
        endcase
end
 
endmodule

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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [sprs.v] - Blame information for rev 266

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's interface to SPRs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Decoding of SPR addresses and access to SPRs ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.3 2001/08/13 03:36:20 lampret`
51			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
52			`//`
53			`// Revision 1.2 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`// Revision 1.1 2001/07/20 00:46:21 lampret`
57			`// Development version of RTL. Libraries are missing.`
58			`//`
59			`//`
60
61			`include "timescale.v"
62			`include "defines.v"
63
64			`module sprs(`
65			`// Clk & Rst`
66			`clk, rst,`
67
68			`// Internal CPU interface`
69			`flag, addrbase, addrofs, dat_i, alu_op, branch_op,`
70			`epcr, eear, esr, except_start, except_started,`
71			`to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,`
72			`spr_dat_cfgr, spr_dat_rf, spr_dat_pc,`
73
74			`// From/to other RISC units`
75			`spr_dat_pic, spr_dat_tt, spr_dat_pm,`
76			`spr_dat_dmmu, spr_dat_immu, spr_dat_du,`
77			`spr_addr, spr_dataout, spr_cs, spr_we,`
78
79			`du_addr, du_dat_du, du_read,`
80			`du_write`
81
82			`);`
83
84			parameter width = `OPERAND_WIDTH;
85
86			`//`
87			`// I/O Ports`
88			`//`
89
90			`//`
91			`// Internal CPU interface`
92			`//`
93			`input clk; // Clock`
94			`input rst; // Reset`
95			`input flag; // From ALU`
96			`input [width-1:0] addrbase; // SPR base address`
97			`input [15:0] addrofs; // SPR offset`
98			`input [width-1:0] dat_i; // SPR write data`
99			input [`ALUOP_WIDTH-1:0] alu_op; // ALU operation
100			input [`BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
101			`input [width-1:0] epcr; // EPCR0`
102			`input [width-1:0] eear; // EEAR0`
103			input [`SR_WIDTH-1:0] esr; // ESR0
104			`input except_start; // Start of exception`
105			`input except_started; // Exception was started`
106			`output [width-1:0] to_wbmux; // For l.mfspr`
107			`output epcr_we; // EPCR0 write enable`
108			`output eear_we; // EEAR0 write enable`
109			`output esr_we; // ESR0 write enable`
110			`output pc_we; // PC write enable`
111			output [`SR_WIDTH-1:0] sr; // SR
112			`input [31:0] spr_dat_cfgr; // Data from CFGR`
113			`input [31:0] spr_dat_rf; // Data from RF`
114			`input [31:0] spr_dat_pc; // Data from PC`
115
116			`//`
117			`// To/from other RISC units`
118			`//`
119			`input [31:0] spr_dat_pic; // Data from PIC`
120			`input [31:0] spr_dat_tt; // Data from TT`
121			`input [31:0] spr_dat_pm; // Data from PM`
122			`input [31:0] spr_dat_dmmu; // Data from DMMU`
123			`input [31:0] spr_dat_immu; // Data from IMMU`
124			`input [31:0] spr_dat_du; // Data from DU`
125			`output [31:0] spr_addr; // SPR Address`
126			`output [31:0] spr_dataout; // Data to unit`
127			`output [31:0] spr_cs; // Unit select`
128			`output spr_we; // SPR write enable`
129
130			`//`
131			`// To/from Debug Unit`
132			`//`
133			`input [width-1:0] du_addr; // Address`
134			`input [width-1:0] du_dat_du; // Data from DU to SPRS`
135			`input du_read; // Read qualifier`
136			`input du_write; // Write qualifier`
137
138			`//`
139			`// Internal regs & wires`
140			`//`
141			reg [`SR_WIDTH-1:0] sr; // SR
142			`reg write_spr; // Write SPR`
143			`reg read_spr; // Read SPR`
144			`reg [width-1:0] to_wbmux; // For l.mfspr`
145			`wire sr_we; // Write enable SR`
146			`wire cfgr_sel; // Select for cfg regs`
147			`wire rf_sel; // Select for RF`
148			`wire pc_sel; // Select for PC`
149			`wire sr_sel; // Select for SR`
150			`wire epcr_sel; // Select for EPCR0`
151			`wire eear_sel; // Select for EEAR0`
152			`wire esr_sel; // Select for ESR0`
153			`wire [31:0] sys_data; // Read data from system SPRs`
154			wire [`SR_WIDTH-1:0] to_sr; // Data to SR
155			`wire du_access; // Debug unit access`
156			wire [`ALUOP_WIDTH-1:0] sprs_op; // ALU operation
157			`reg [31:0] unqualified_cs; // Unqualified chip selects`
158
159			`//`
160			`// Decide if it is debug unit access`
161			`//`
162			`assign du_access = du_read \| du_write;`
163
164			`//`
165			`// Generate sprs opcode`
166			`//`
167			assign sprs_op = du_write ? `ALUOP_MTSR : du_read ? `ALUOP_MFSR : alu_op;
168
169			`//`
170			`// Generate SPR address from base address and offset`
171			`// OR from debug unit address`
172			`//`
173			`assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};`
174
175			`//`
176			`// SPR is written with dat_i from l.mtspr`
177			`// OR by debug unit`
178			`//`
179			`assign spr_dataout = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;`
180
181			`//`
182			`// Write into SPRs when l.mtspr`
183			`//`
184			`assign spr_we = du_write \| write_spr;`
185
186			`//`
187			`// Qualify chip selects`
188			`//`
189			`assign spr_cs = unqualified_cs & {32{read_spr \| write_spr}};`
190
191			`//`
192			`// Decoding of groups`
193			`//`
194			`always @(spr_addr)`
195			case (spr_addr[`SPR_GROUP_BITS]) // synopsys parallel_case
196			`SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
197			`SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
198			`SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
199			`SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
200			`SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
201			`SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
202			`SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
203			`SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
204			`SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
205			`SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
206			`SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
207			`SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
208			`SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
209			`SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
210			`SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
211			`SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
212			`SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
213			`SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
214			`SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
215			`SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
216			`SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
217			`SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
218			`SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
219			`SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
220			`SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
221			`SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
222			`SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
223			`SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
224			`SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
225			`SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
226			`SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
227			`SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
228			`endcase`
229
230			`//`
231			`// SPRs System Group`
232			`//`
233
234			`//`
235			`// What to write into SR`
236			`//`
237			assign to_sr = (branch_op == `BRANCHOP_RFE) ? esr : spr_dataout[`SR_WIDTH-1:0];
238
239			`//`
240			`// Selects for system SPRs`
241			`//`
242			assign cfgr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:4] == `SPR_CFGR));
243			assign rf_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:5] == `SPR_RF));
244			assign pc_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_PC));
245			assign sr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_SR));
246			assign epcr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_EPCR));
247			assign eear_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_EEAR));
248			assign esr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_ESR));
249
250			`//`
251			`// Write enables for system SPRs`
252			`//`
253			assign sr_we = (write_spr && sr_sel) \| (branch_op == `BRANCHOP_RFE);
254			`assign pc_we = (write_spr && pc_sel);`
255			`assign epcr_we = (write_spr && epcr_sel);`
256			`assign eear_we = (write_spr && eear_sel);`
257			`assign esr_we = (write_spr && esr_sel);`
258
259			`//`
260			`// Output from system SPRs`
261			`//`
262			`assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) \|`
263			`(spr_dat_rf & {32{read_spr & rf_sel}}) \|`
264			`(spr_dat_pc & {32{read_spr & pc_sel}}) \|`
265			({{32-`SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) \|
266			`(epcr & {32{read_spr & epcr_sel}}) \|`
267			`(eear & {32{read_spr & eear_sel}}) \|`
268			({{32-`SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
269
270			`//`
271			`// Supervision register`
272			`//`
273			`always @(posedge clk or posedge rst)`
274			`if (rst)`
275			sr <= #1 `SR_WIDTH'b001;
276			`else if (except_started) begin`
277			`ifdef OR1200_VERBOSE
278			`// synopsys translate_off`
279			`$display(" INFO: exception started. SR[SUPV] set and SR[EXR] cleared.");`
280			`// synopsys translate_on`
281			`endif
282			sr[`SR_SUPV] <= #1 1'b1;
283			sr[`SR_EXR] <= #1 1'b0;
284			sr[`SR_WIDTH-1:2] <= #1 {`SR_WIDTH-2{1'b0}};
285			`end`
286			`else if (sr_we) begin`
287			`ifdef OR1200_VERBOSE
288			`// synopsys translate_off`
289			`$display(" INFO: writing into SR register: %h", spr_dataout);`
290			`// synopsys translate_on`
291			`endif
292			`sr <= #1 to_sr;`
293			`end`
294
295			`//`
296			`// MTSPR/MFSPR interface`
297			`//`
298			`always @(sprs_op or spr_addr or spr_dataout or sys_data or spr_dat_pic or spr_dat_pm or`
299			`spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin`
300			`case (sprs_op) // synopsys full_case parallel_case`
301			`ALUOP_MTSR : begin
302			`ifdef OR1200_VERBOSE
303			`// synopsys translate_off`
304			`$display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, spr_dataout);`
305			`// synopsys translate_on`
306			`endif
307			`write_spr = 1'b1;`
308			`read_spr = 1'b0;`
309			`to_wbmux = 32'b0;`
310			`end`
311			`ALUOP_MFSR : begin
312			casex (spr_addr[`SPR_GROUP_BITS])
313			`SPR_GROUP_TT:
314			`to_wbmux = spr_dat_tt;`
315			`SPR_GROUP_PIC:
316			`to_wbmux = spr_dat_pic;`
317			`SPR_GROUP_PM:
318			`to_wbmux = spr_dat_pm;`
319			`SPR_GROUP_DMMU:
320			`to_wbmux = spr_dat_dmmu;`
321			`SPR_GROUP_IMMU:
322			`to_wbmux = spr_dat_immu;`
323			`SPR_GROUP_DU:
324			`to_wbmux = spr_dat_du;`
325			`SPR_GROUP_SYS:
326			`to_wbmux = sys_data;`
327			`default:`
328			`to_wbmux = 32'b0;`
329			`endcase`
330			`write_spr = 1'b0;`
331			`read_spr = 1'b1;`
332			`end`
333			`default : begin`
334			`write_spr = 1'b0;`
335			`read_spr = 1'b0;`
336			`to_wbmux = 32'b0;`
337			`end`
338			`endcase`
339			`end`
340
341			`endmodule`