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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Write-back Mux                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  CPU's write-back stage of the pipeline                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module wbmux(
        // Clock and reset
        clk, rst,
 
        // Internal i/f
        wb_freeze, rfwb_op,
        muxin_a, muxin_b, muxin_c, muxin_d,
        muxout, muxreg, muxreg_valid
);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Internal i/f
//
input                           wb_freeze;
input   [`RFWBOP_WIDTH-1:0]      rfwb_op;
input   [width-1:0]              muxin_a;
input   [width-1:0]              muxin_b;
input   [width-1:0]              muxin_c;
input   [width-1:0]              muxin_d;
output  [width-1:0]              muxout;
output  [width-1:0]              muxreg;
output                          muxreg_valid;
 
//
// Internal wires and regs
//
reg     [width-1:0]              muxout;
reg     [width-1:0]              muxreg;
reg                             muxreg_valid;
 
//
// Registered output from the write-back multiplexer
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                muxreg <= #1 32'd0;
                muxreg_valid <= #1 1'b0;
        end
        else if (!wb_freeze) begin
                muxreg <= #1 muxout;
                muxreg_valid <= #1 rfwb_op[0];
        end
end
 
//
// Write-back multiplexer
//
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
        case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux
                2'b00: muxout = muxin_a;
                2'b01: begin
                        muxout = muxin_b;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_b %h", muxin_b);
// synopsys translate_on
`endif
                end
                2'b10: begin
                        muxout = muxin_c;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_c %h", muxin_c);
// synopsys translate_on
`endif
                end
                2'b11: begin
                        muxout = muxin_d + 4'h8;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("  WBMUX: muxin_d %h", muxin_d + 4'h8);
// synopsys translate_on
`endif
                end
        endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Write-back Mux ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// CPU's write-back stage of the pipeline ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:23 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`module wbmux(`
64			`// Clock and reset`
65			`clk, rst,`
66
67			`// Internal i/f`
68			`wb_freeze, rfwb_op,`
69			`muxin_a, muxin_b, muxin_c, muxin_d,`
70			`muxout, muxreg, muxreg_valid`
71			`);`
72
73			parameter width = `OPERAND_WIDTH;
74
75			`//`
76			`// I/O`
77			`//`
78
79			`//`
80			`// Clock and reset`
81			`//`
82			`input clk;`
83			`input rst;`
84
85			`//`
86			`// Internal i/f`
87			`//`
88			`input wb_freeze;`
89			input [`RFWBOP_WIDTH-1:0] rfwb_op;
90			`input [width-1:0] muxin_a;`
91			`input [width-1:0] muxin_b;`
92			`input [width-1:0] muxin_c;`
93			`input [width-1:0] muxin_d;`
94			`output [width-1:0] muxout;`
95			`output [width-1:0] muxreg;`
96			`output muxreg_valid;`
97
98			`//`
99			`// Internal wires and regs`
100			`//`
101			`reg [width-1:0] muxout;`
102			`reg [width-1:0] muxreg;`
103			`reg muxreg_valid;`
104
105			`//`
106			`// Registered output from the write-back multiplexer`
107			`//`
108			`always @(posedge clk or posedge rst) begin`
109			`if (rst) begin`
110			`muxreg <= #1 32'd0;`
111			`muxreg_valid <= #1 1'b0;`
112			`end`
113			`else if (!wb_freeze) begin`
114			`muxreg <= #1 muxout;`
115			`muxreg_valid <= #1 rfwb_op[0];`
116			`end`
117			`end`
118
119			`//`
120			`// Write-back multiplexer`
121			`//`
122			`always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin`
123			case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux
124			`2'b00: muxout = muxin_a;`
125			`2'b01: begin`
126			`muxout = muxin_b;`
127			`ifdef OR1200_VERBOSE
128			`// synopsys translate_off`
129			`$display(" WBMUX: muxin_b %h", muxin_b);`
130			`// synopsys translate_on`
131			`endif
132			`end`
133			`2'b10: begin`
134			`muxout = muxin_c;`
135			`ifdef OR1200_VERBOSE
136			`// synopsys translate_off`
137			`$display(" WBMUX: muxin_c %h", muxin_c);`
138			`// synopsys translate_on`
139			`endif
140			`end`
141			`2'b11: begin`
142			`muxout = muxin_d + 4'h8;`
143			`ifdef OR1200_VERBOSE
144			`// synopsys translate_off`
145			`$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);`
146			`// synopsys translate_on`
147			`endif
148			`end`
149			`endcase`
150			`end`
151
152			`endmodule`

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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [wbmux.v] - Blame information for rev 266