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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`ifdef XILINX_RAM32X1D
 
module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
 
`endif

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Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.1 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`//`
54
55			`// synopsys translate_off`
56			`include "timescale.v"
57			`// synopsys translate_on`
58			`include "defines.v"
59
60			`ifdef XILINX_RAM32X1D
61
62			`module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
63
64			`//`
65			`// I/O`
66			`//`
67			`output [7:0] DPO;`
68			`output [7:0] SPO;`
69			`input [4:0] A;`
70			`input [4:0] DPRA;`
71			`input [7:0] D;`
72			`input WCLK;`
73			`input WE;`
74
75			`//`
76			`// Instantiation of block 0`
77			`//`
78			`RAM32X1D ram32x1d_0(`
79			`.DPO(DPO[0]),`
80			`.SPO(SPO[0]),`
81			`.A0(A[0]),`
82			`.A1(A[1]),`
83			`.A2(A[2]),`
84			`.A3(A[3]),`
85			`.A4(A[4]),`
86			`.D(D[0]),`
87			`.DPRA0(DPRA[0]),`
88			`.DPRA1(DPRA[1]),`
89			`.DPRA2(DPRA[2]),`
90			`.DPRA3(DPRA[3]),`
91			`.DPRA4(DPRA[4]),`
92			`.WCLK(WCLK),`
93			`.WE(WE)`
94			`);`
95
96			`//`
97			`// Instantiation of block 1`
98			`//`
99			`RAM32X1D ram32x1d_1(`
100			`.DPO(DPO[1]),`
101			`.SPO(SPO[1]),`
102			`.A0(A[0]),`
103			`.A1(A[1]),`
104			`.A2(A[2]),`
105			`.A3(A[3]),`
106			`.A4(A[4]),`
107			`.D(D[1]),`
108			`.DPRA0(DPRA[0]),`
109			`.DPRA1(DPRA[1]),`
110			`.DPRA2(DPRA[2]),`
111			`.DPRA3(DPRA[3]),`
112			`.DPRA4(DPRA[4]),`
113			`.WCLK(WCLK),`
114			`.WE(WE)`
115			`);`
116
117			`//`
118			`// Instantiation of block 2`
119			`//`
120			`RAM32X1D ram32x1d_2(`
121			`.DPO(DPO[2]),`
122			`.SPO(SPO[2]),`
123			`.A0(A[0]),`
124			`.A1(A[1]),`
125			`.A2(A[2]),`
126			`.A3(A[3]),`
127			`.A4(A[4]),`
128			`.D(D[2]),`
129			`.DPRA0(DPRA[0]),`
130			`.DPRA1(DPRA[1]),`
131			`.DPRA2(DPRA[2]),`
132			`.DPRA3(DPRA[3]),`
133			`.DPRA4(DPRA[4]),`
134			`.WCLK(WCLK),`
135			`.WE(WE)`
136			`);`
137
138			`//`
139			`// Instantiation of block 3`
140			`//`
141			`RAM32X1D ram32x1d_3(`
142			`.DPO(DPO[3]),`
143			`.SPO(SPO[3]),`
144			`.A0(A[0]),`
145			`.A1(A[1]),`
146			`.A2(A[2]),`
147			`.A3(A[3]),`
148			`.A4(A[4]),`
149			`.D(D[3]),`
150			`.DPRA0(DPRA[0]),`
151			`.DPRA1(DPRA[1]),`
152			`.DPRA2(DPRA[2]),`
153			`.DPRA3(DPRA[3]),`
154			`.DPRA4(DPRA[4]),`
155			`.WCLK(WCLK),`
156			`.WE(WE)`
157			`);`
158
159			`//`
160			`// Instantiation of block 4`
161			`//`
162			`RAM32X1D ram32x1d_4(`
163			`.DPO(DPO[4]),`
164			`.SPO(SPO[4]),`
165			`.A0(A[0]),`
166			`.A1(A[1]),`
167			`.A2(A[2]),`
168			`.A3(A[3]),`
169			`.A4(A[4]),`
170			`.D(D[4]),`
171			`.DPRA0(DPRA[0]),`
172			`.DPRA1(DPRA[1]),`
173			`.DPRA2(DPRA[2]),`
174			`.DPRA3(DPRA[3]),`
175			`.DPRA4(DPRA[4]),`
176			`.WCLK(WCLK),`
177			`.WE(WE)`
178			`);`
179
180			`//`
181			`// Instantiation of block 5`
182			`//`
183			`RAM32X1D ram32x1d_5(`
184			`.DPO(DPO[5]),`
185			`.SPO(SPO[5]),`
186			`.A0(A[0]),`
187			`.A1(A[1]),`
188			`.A2(A[2]),`
189			`.A3(A[3]),`
190			`.A4(A[4]),`
191			`.D(D[5]),`
192			`.DPRA0(DPRA[0]),`
193			`.DPRA1(DPRA[1]),`
194			`.DPRA2(DPRA[2]),`
195			`.DPRA3(DPRA[3]),`
196			`.DPRA4(DPRA[4]),`
197			`.WCLK(WCLK),`
198			`.WE(WE)`
199			`);`
200
201			`//`
202			`// Instantiation of block 6`
203			`//`
204			`RAM32X1D ram32x1d_6(`
205			`.DPO(DPO[6]),`
206			`.SPO(SPO[6]),`
207			`.A0(A[0]),`
208			`.A1(A[1]),`
209			`.A2(A[2]),`
210			`.A3(A[3]),`
211			`.A4(A[4]),`
212			`.D(D[6]),`
213			`.DPRA0(DPRA[0]),`
214			`.DPRA1(DPRA[1]),`
215			`.DPRA2(DPRA[2]),`
216			`.DPRA3(DPRA[3]),`
217			`.DPRA4(DPRA[4]),`
218			`.WCLK(WCLK),`
219			`.WE(WE)`
220			`);`
221
222			`//`
223			`// Instantiation of block 7`
224			`//`
225			`RAM32X1D ram32x1d_7(`
226			`.DPO(DPO[7]),`
227			`.SPO(SPO[7]),`
228			`.A0(A[0]),`
229			`.A1(A[1]),`
230			`.A2(A[2]),`
231			`.A3(A[3]),`
232			`.A4(A[4]),`
233			`.D(D[7]),`
234			`.DPRA0(DPRA[0]),`
235			`.DPRA1(DPRA[1]),`
236			`.DPRA2(DPRA[2]),`
237			`.DPRA3(DPRA[3]),`
238			`.DPRA4(DPRA[4]),`
239			`.WCLK(WCLK),`
240			`.WE(WE)`
241			`);`
242
243			`endmodule`
244
245			`endif