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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [ssvga/] [ssvga_crtc.v] - Blame information for rev 1780

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Simple Small VGA IP Core                                    ////
////                                                              ////
////  This file is part of the Simple Small VGA project           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Hsync/Vsync generator.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:19:09  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "ssvga_defines.v"
 
module ssvga_crtc(
        clk, rst, hsync, vsync, hblank, vblank
);
 
//
// I/O ports
//
input                           clk;    // Pixel Clock
input                           rst;    // Reset
output                          hsync;  // H sync
output                          vsync;  // V sync
output                          hblank; // H blank
output                          vblank; // V blank
 
//
// Internal wires and regs
//
reg     [`SSVGA_HCW-1:0] hcntr;  // Horizontal counter
reg     [`SSVGA_VCW-1:0] vcntr;  // Vertical counter
reg                             hsync;  // Horizontal sync
reg                             vsync;  // Vertical sync
 
// flip - flops for decoding end of one line
reg line_end1 ;
reg line_end2 ;
 
always@(posedge clk or posedge rst)
begin
    if (rst)
    begin
        line_end1 <= #1 1'b0 ;
        line_end2 <= #1 1'b0 ;
    end
    else
    begin
        line_end1 <= #1 hsync ;
        line_end2 <= #1 line_end1 ;
    end
end
 
wire line_end = ~line_end2 && line_end1 ;
 
//
// Assert hblank when hsync is not asserted
//
reg hblank ;
always@(posedge clk or posedge rst)
begin
    if (rst)
        hblank <= #1 1'b0 ;
    else
    if ( hcntr == (`SSVGA_HPULSE + `SSVGA_HBACKP) )
        hblank <= #1 1'b0 ;
    else
    if ( hcntr == (`SSVGA_HTOT - `SSVGA_HFRONTP) )
        hblank <= #1 1'b1 ;
end
 
reg vblank ;
always@(posedge clk or posedge rst)
begin
    if ( rst )
        vblank <= #1 1'b0 ;
    else
    if ((vcntr == (`SSVGA_VPULSE + `SSVGA_VBACKP)) && line_end)
        vblank <= #1 1'b0 ;
    else
    if ((vcntr == (`SSVGA_VTOT - `SSVGA_VFRONTP)) && line_end)
        vblank <= #1 1'b1 ;
end
 
//
// Horizontal counter
//
always @(posedge clk or posedge rst)
                if (rst)
                        hcntr <= #1 `SSVGA_HCW'h0;
                else if (hcntr == `SSVGA_HTOT - 1)
                        hcntr <= #1 `SSVGA_HCW'h0;
                else
                        hcntr <= #1 hcntr + 1;
//
// Horizontal sync
//
always @(posedge clk or posedge rst)
                if (rst)
                        hsync <= #1 1'b0;
                else if (hcntr == `SSVGA_HCW'h0)
                        hsync <= #1 1'b1;
                else if (hcntr == `SSVGA_HPULSE)
                        hsync <= #1 1'b0 ;
 
//
// Vertical counter
//
always @(posedge clk or posedge rst)
                if (rst)
                        vcntr <= #1 `SSVGA_VCW'h0;
                else if ((vcntr == `SSVGA_VTOT - 1) && line_end)
                        vcntr <= #1 `SSVGA_VCW'h0;
                else if ( line_end )
                        vcntr <= #1 vcntr + 1;
//
// Vertical sync
//
always @(posedge clk or posedge rst)
                if (rst)
                        vsync <= #1 1'b0;
                else if ((vcntr == `SSVGA_VCW'd0) && line_end)
                        vsync <= #1 1'b1;
                else if ((vcntr == `SSVGA_VPULSE) && line_end)
                        vsync <= #1 1'b0;
endmodule

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Simple Small VGA IP Core ////`
4			`//// ////`
5			`//// This file is part of the Simple Small VGA project ////`
6			`//// ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Hsync/Vsync generator. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:19:09 igorm`
48			`// no message`
49			`//`
50			`//`
51
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55
56			`include "ssvga_defines.v"
57
58			`module ssvga_crtc(`
59			`clk, rst, hsync, vsync, hblank, vblank`
60			`);`
61
62			`//`
63			`// I/O ports`
64			`//`
65			`input clk; // Pixel Clock`
66			`input rst; // Reset`
67			`output hsync; // H sync`
68			`output vsync; // V sync`
69			`output hblank; // H blank`
70			`output vblank; // V blank`
71
72			`//`
73			`// Internal wires and regs`
74			`//`
75			reg [`SSVGA_HCW-1:0] hcntr; // Horizontal counter
76			reg [`SSVGA_VCW-1:0] vcntr; // Vertical counter
77			`reg hsync; // Horizontal sync`
78			`reg vsync; // Vertical sync`
79
80			`// flip - flops for decoding end of one line`
81			`reg line_end1 ;`
82			`reg line_end2 ;`
83
84			`always@(posedge clk or posedge rst)`
85			`begin`
86			`if (rst)`
87			`begin`
88			`line_end1 <= #1 1'b0 ;`
89			`line_end2 <= #1 1'b0 ;`
90			`end`
91			`else`
92			`begin`
93			`line_end1 <= #1 hsync ;`
94			`line_end2 <= #1 line_end1 ;`
95			`end`
96			`end`
97
98			`wire line_end = ~line_end2 && line_end1 ;`
99
100			`//`
101			`// Assert hblank when hsync is not asserted`
102			`//`
103			`reg hblank ;`
104			`always@(posedge clk or posedge rst)`
105			`begin`
106			`if (rst)`
107			`hblank <= #1 1'b0 ;`
108			`else`
109			if ( hcntr == (`SSVGA_HPULSE + `SSVGA_HBACKP) )
110			`hblank <= #1 1'b0 ;`
111			`else`
112			if ( hcntr == (`SSVGA_HTOT - `SSVGA_HFRONTP) )
113			`hblank <= #1 1'b1 ;`
114			`end`
115
116			`reg vblank ;`
117			`always@(posedge clk or posedge rst)`
118			`begin`
119			`if ( rst )`
120			`vblank <= #1 1'b0 ;`
121			`else`
122			if ((vcntr == (`SSVGA_VPULSE + `SSVGA_VBACKP)) && line_end)
123			`vblank <= #1 1'b0 ;`
124			`else`
125			if ((vcntr == (`SSVGA_VTOT - `SSVGA_VFRONTP)) && line_end)
126			`vblank <= #1 1'b1 ;`
127			`end`
128
129			`//`
130			`// Horizontal counter`
131			`//`
132			`always @(posedge clk or posedge rst)`
133			`if (rst)`
134			hcntr <= #1 `SSVGA_HCW'h0;
135			else if (hcntr == `SSVGA_HTOT - 1)
136			hcntr <= #1 `SSVGA_HCW'h0;
137			`else`
138			`hcntr <= #1 hcntr + 1;`
139			`//`
140			`// Horizontal sync`
141			`//`
142			`always @(posedge clk or posedge rst)`
143			`if (rst)`
144			`hsync <= #1 1'b0;`
145			else if (hcntr == `SSVGA_HCW'h0)
146			`hsync <= #1 1'b1;`
147			else if (hcntr == `SSVGA_HPULSE)
148			`hsync <= #1 1'b0 ;`
149
150			`//`
151			`// Vertical counter`
152			`//`
153			`always @(posedge clk or posedge rst)`
154			`if (rst)`
155			vcntr <= #1 `SSVGA_VCW'h0;
156			else if ((vcntr == `SSVGA_VTOT - 1) && line_end)
157			vcntr <= #1 `SSVGA_VCW'h0;
158			`else if ( line_end )`
159			`vcntr <= #1 vcntr + 1;`
160			`//`
161			`// Vertical sync`
162			`//`
163			`always @(posedge clk or posedge rst)`
164			`if (rst)`
165			`vsync <= #1 1'b0;`
166			else if ((vcntr == `SSVGA_VCW'd0) && line_end)
167			`vsync <= #1 1'b1;`
168			else if ((vcntr == `SSVGA_VPULSE) && line_end)
169			`vsync <= #1 1'b0;`
170			`endmodule`

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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [ssvga/] [ssvga_crtc.v] - Blame information for rev 1780