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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Simple Small VGA IP Core                                    ////
////                                                              ////
////  This file is part of the Simple Small VGA project           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  LITTLE-ENDIAN WISHBONE slave interface.                     ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:19:09  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`define SEL_PAL 10
`define SEL_ADDRESS 2
 
module ssvga_wbs_if(
        // Clock and reset
        wb_clk_i, wb_rst_i,
 
        // WISHBONE Slave I/F
        wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,
        wbs_adr_i, wbs_dat_i, wbs_cab_i,
        wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
 
        // Other signals
        ssvga_en, pal_wr_en, pal_rd_en, pal_dat,
    pix_start_addr, misc
);
 
//
// I/O ports
//
 
//
// Clock and reset
//
input                   wb_clk_i;       // Pixel Clock
input                   wb_rst_i;       // Reset
 
//
// WISHBONE Slave I/F
//
input                   wbs_cyc_i;
input                   wbs_stb_i;
input   [3:0]            wbs_sel_i;
input                   wbs_we_i;
input   [31:0]           wbs_adr_i;
input   [31:0]           wbs_dat_i;
input                   wbs_cab_i;
output  [31:0]           wbs_dat_o;
output                  wbs_ack_o;
output                  wbs_err_o;
output                  wbs_rty_o;
 
//
// Other signals
//
output                  ssvga_en;       // Global enable
output                  pal_wr_en;      // Palette write enable
output                  pal_rd_en;      // Palette read enable
input   [15:0]           pal_dat;        // Palette data
output  [31:2] pix_start_addr ;
input   [15:0]   misc;
 
//
// Internal regs and wires
//
reg                     wbs_ack_o;      // WISHBONE ack
reg                     wbs_err_o;      // WISHBONE err
reg     [0:0]             ctrl_r;         // Control register
wire                    valid_access;   // Access to SSVGA
 
//
// Control register
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                ctrl_r <= #1 1'b0;
        else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & !wbs_adr_i[`SEL_ADDRESS])
                ctrl_r <= #1 wbs_dat_i[0];
 
reg [31:2] pix_start_addr ;
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                pix_start_addr <= #1 30'h0000_0000 ;
        else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & wbs_adr_i[`SEL_ADDRESS] )
                pix_start_addr <= #1 wbs_dat_i[31:2] ;
 
//
// Generate delayed WISHBONE ack/err
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i) begin
                wbs_ack_o <= #1 1'b0;
                wbs_err_o <= #1 1'b0;
        end
        else if (valid_access) begin
                wbs_ack_o <= #1 1'b1;
                wbs_err_o <= #1 1'b0;
        end
        else if (wbs_cyc_i & wbs_stb_i) begin
                wbs_ack_o <= #1 1'b0;
                wbs_err_o <= #1 1'b1;
        end
        else begin
                wbs_ack_o <= #1 1'b0;
                wbs_err_o <= #1 1'b0;
        end
 
//
// Generate WISHBONE output signals
//
reg [31:0] wbs_dat_o ;
always@(wbs_adr_i or pal_dat or ctrl_r or pix_start_addr or misc)
begin
    if ( wbs_adr_i[`SEL_PAL] )
        wbs_dat_o = {16'h0000, pal_dat} ;
    else
    if ( wbs_adr_i[`SEL_ADDRESS] )
        wbs_dat_o = {pix_start_addr, 2'b00} ;
    else
        wbs_dat_o = {{15{1'b0}}, misc, ctrl_r};
end
 
assign wbs_rty_o = 1'b0;
 
//
// Generate other signals
//
assign valid_access = wbs_cyc_i & wbs_stb_i & (wbs_sel_i == 4'b1111);
assign ssvga_en = ctrl_r[0];
assign pal_wr_en = valid_access & wbs_we_i & wbs_adr_i[`SEL_PAL];
assign pal_rd_en = valid_access & ~wbs_we_i & wbs_adr_i[`SEL_PAL];
 
endmodule

Line No.	Rev	Author	Line
1	266	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Simple Small VGA IP Core ////`
4			`//// ////`
5			`//// This file is part of the Simple Small VGA project ////`
6			`//// ////`
7			`//// ////`
8			`//// Description ////`
9			`//// LITTLE-ENDIAN WISHBONE slave interface. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:19:09 igorm`
48			`// no message`
49			`//`
50			`//`
51
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55
56			`define SEL_PAL 10
57			`define SEL_ADDRESS 2
58
59			`module ssvga_wbs_if(`
60			`// Clock and reset`
61			`wb_clk_i, wb_rst_i,`
62
63			`// WISHBONE Slave I/F`
64			`wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,`
65			`wbs_adr_i, wbs_dat_i, wbs_cab_i,`
66			`wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,`
67
68			`// Other signals`
69			`ssvga_en, pal_wr_en, pal_rd_en, pal_dat,`
70			`pix_start_addr, misc`
71			`);`
72
73			`//`
74			`// I/O ports`
75			`//`
76
77			`//`
78			`// Clock and reset`
79			`//`
80			`input wb_clk_i; // Pixel Clock`
81			`input wb_rst_i; // Reset`
82
83			`//`
84			`// WISHBONE Slave I/F`
85			`//`
86			`input wbs_cyc_i;`
87			`input wbs_stb_i;`
88			`input [3:0] wbs_sel_i;`
89			`input wbs_we_i;`
90			`input [31:0] wbs_adr_i;`
91			`input [31:0] wbs_dat_i;`
92			`input wbs_cab_i;`
93			`output [31:0] wbs_dat_o;`
94			`output wbs_ack_o;`
95			`output wbs_err_o;`
96			`output wbs_rty_o;`
97
98			`//`
99			`// Other signals`
100			`//`
101			`output ssvga_en; // Global enable`
102			`output pal_wr_en; // Palette write enable`
103			`output pal_rd_en; // Palette read enable`
104			`input [15:0] pal_dat; // Palette data`
105			`output [31:2] pix_start_addr ;`
106			`input [15:0] misc;`
107
108			`//`
109			`// Internal regs and wires`
110			`//`
111			`reg wbs_ack_o; // WISHBONE ack`
112			`reg wbs_err_o; // WISHBONE err`
113			`reg [0:0] ctrl_r; // Control register`
114			`wire valid_access; // Access to SSVGA`
115
116			`//`
117			`// Control register`
118			`//`
119			`always @(posedge wb_clk_i or posedge wb_rst_i)`
120			`if (wb_rst_i)`
121			`ctrl_r <= #1 1'b0;`
122			else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & !wbs_adr_i[`SEL_ADDRESS])
123			`ctrl_r <= #1 wbs_dat_i[0];`
124
125			`reg [31:2] pix_start_addr ;`
126			`always @(posedge wb_clk_i or posedge wb_rst_i)`
127			`if (wb_rst_i)`
128			`pix_start_addr <= #1 30'h0000_0000 ;`
129			else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & wbs_adr_i[`SEL_ADDRESS] )
130			`pix_start_addr <= #1 wbs_dat_i[31:2] ;`
131
132			`//`
133			`// Generate delayed WISHBONE ack/err`
134			`//`
135			`always @(posedge wb_clk_i or posedge wb_rst_i)`
136			`if (wb_rst_i) begin`
137			`wbs_ack_o <= #1 1'b0;`
138			`wbs_err_o <= #1 1'b0;`
139			`end`
140			`else if (valid_access) begin`
141			`wbs_ack_o <= #1 1'b1;`
142			`wbs_err_o <= #1 1'b0;`
143			`end`
144			`else if (wbs_cyc_i & wbs_stb_i) begin`
145			`wbs_ack_o <= #1 1'b0;`
146			`wbs_err_o <= #1 1'b1;`
147			`end`
148			`else begin`
149			`wbs_ack_o <= #1 1'b0;`
150			`wbs_err_o <= #1 1'b0;`
151			`end`
152
153			`//`
154			`// Generate WISHBONE output signals`
155			`//`
156			`reg [31:0] wbs_dat_o ;`
157			`always@(wbs_adr_i or pal_dat or ctrl_r or pix_start_addr or misc)`
158			`begin`
159			if ( wbs_adr_i[`SEL_PAL] )
160			`wbs_dat_o = {16'h0000, pal_dat} ;`
161			`else`
162			if ( wbs_adr_i[`SEL_ADDRESS] )
163			`wbs_dat_o = {pix_start_addr, 2'b00} ;`
164			`else`
165			`wbs_dat_o = {{15{1'b0}}, misc, ctrl_r};`
166			`end`
167
168			`assign wbs_rty_o = 1'b0;`
169
170			`//`
171			`// Generate other signals`
172			`//`
173			`assign valid_access = wbs_cyc_i & wbs_stb_i & (wbs_sel_i == 4'b1111);`
174			`assign ssvga_en = ctrl_r[0];`
175			assign pal_wr_en = valid_access & wbs_we_i & wbs_adr_i[`SEL_PAL];
176			assign pal_rd_en = valid_access & ~wbs_we_i & wbs_adr_i[`SEL_PAL];
177
178			`endmodule`

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[/] [or1k/] [tags/] [first/] [mp3/] [rtl/] [verilog/] [ssvga/] [ssvga_wbs_if.v] - Blame information for rev 1780