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#!/bin/csh -f
 
ncprep -f ../bin/nc.scr
#debussy -f ../bin/nc.scr
#nLint -f ../bin/nc.scr
#verilog -f ../bin/nc.scr
# mv ncverilog.log ../log/ncverilog.log
 
ncvlog -f ncvlog.args
if ($status != 0) then
  exit
endif
 
# Run the NC-Verilog elaborator (build the design hierarchy)
ncelab -f ncelab.args
if ($status != 0) then
  exit
endif
 
# Run the NC-Verilog simulator (simulate the design)
ncsim -f ncsim.args && \
mv flash.log ../log && \
mv executed.log ../log && \
mv sram.log ../log

Line No.	Rev	Author	Line
1	266	lampret	`#!/bin/csh -f`
2
3			`ncprep -f ../bin/nc.scr`
4			`#debussy -f ../bin/nc.scr`
5			`#nLint -f ../bin/nc.scr`
6			`#verilog -f ../bin/nc.scr`
7			`# mv ncverilog.log ../log/ncverilog.log`
8
9			`ncvlog -f ncvlog.args`
10			`if ($status != 0) then`
11			`exit`
12			`endif`
13
14			`# Run the NC-Verilog elaborator (build the design hierarchy)`
15			`ncelab -f ncelab.args`
16			`if ($status != 0) then`
17			`exit`
18			`endif`
19
20			`# Run the NC-Verilog simulator (simulate the design)`
21			`ncsim -f ncsim.args && \`
22			`mv flash.log ../log && \`
23			`mv executed.log ../log && \`
24			`mv sram.log ../log`

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[/] [or1k/] [tags/] [first/] [mp3/] [sim/] [run/] [run_sim] - Blame information for rev 266