OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [first/] [mp3/] [sw/] [console-xess/] [support.c] - Blame information for rev 1780

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 268 lampret
/* Support */
2
 
3
#include <stdarg.h>
4
 
5
#if OR1K
6
 
7
void __dummy() {} /* to fix RTL simulator bug */
8
void reset_support()
9
{
10
        main();
11
        exit(0);
12
}
13
 
14
void printf(const char *fmt, ...)
15
{
16
        va_list args;
17
        va_start(args, fmt);
18
        asm("l.addi\tr3,%0,0": :"r" (fmt));
19
        asm("l.addi\tr4,%0,0": :"r" (args));
20
        asm("l.sys 202");
21
}
22
 
23
void exit(int x)
24
{
25
  asm("l.sys 203");
26
}
27
 
28
void report(unsigned long value)
29
{
30
        unsigned long spr = 0x1234;
31
        asm("l.mtspr\t\t%0,%1,0x0" : : "r" (spr), "r" (value));
32
        return;
33
}
34
 
35
void __main()
36
{
37
}
38
 
39
void bcopy(const void *srcvoid, void * dstvoid, int length)
40
{
41
  char *dst = dstvoid;
42
  const char *src = srcvoid;
43
 
44
  while (length--)
45
          *dst++ = *src++;
46
}
47
 
48
#else
49
void report(unsigned long value)
50
{
51
        unsigned long spr = 0x1234;
52
        printf("l.mtspr %x,%x\n", spr, value);
53
        return;
54
}
55
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.