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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_sync_clk1_clk2.v                                        ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/11/26 10:47:09  mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.2  2001/10/19 11:40:01  mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
//
//
//
// 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// FF in clock domain 1 is being set by a signal from the clock domain 2
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
 
parameter   Tp = 1;
 
input   clk1;
input   clk2;
input   reset1;
input   reset2;
input   set2;
 
output  sync_out;
 
reg     set2_q;
reg     set2_q2;
reg     set1_q;
reg     set1_q2;
reg     clear2_q;
reg     clear2_q2;
reg     sync_out;
 
wire    z;
 
assign z = set2 | set2_q & ~clear2_q2;
 
 
// Latching and synchronizing "set" to clk2
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    set2_q <=#Tp 1'b0;
  else
    set2_q <=#Tp z;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    set2_q2 <=#Tp 1'b0;
  else
    set2_q2 <=#Tp set2_q;
end
 
 
// Synchronizing "set" to clk1
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    set1_q <=#Tp 1'b0;
  else
    set1_q <=#Tp set2_q2;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    set1_q2 <=#Tp 1'b0;
  else
    set1_q2 <=#Tp set1_q;
end
 
 
// Synchronizing "clear" to clk2
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    clear2_q <=#Tp 1'b0;
  else
    clear2_q <=#Tp set1_q2;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    clear2_q2 <=#Tp 1'b0;
  else
    clear2_q2 <=#Tp clear2_q;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    sync_out <=#Tp 1'b0;
  else
    sync_out <=#Tp set1_q2;
end
 
endmodule

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_sync_clk1_clk2.v ////`
4			`//// ////`
5			`//// This file is part of the SoC/OpenRISC Development Interface ////`
6			`//// http://www.opencores.org/cores/DebugInterface/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.3 2001/11/26 10:47:09 mohor`
45			`// Crc generation is different for read or write commands. Small synthesys fixes.`
46			`//`
47			`// Revision 1.2 2001/10/19 11:40:01 mohor`
48			`// dbg_timescale.v changed to timescale.v This is done for the simulation of`
49			`// few different cores in a single project.`
50			`//`
51			`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
52			`// Initial official release.`
53			`//`
54			`//`
55			`//`
56			`//`
57			`//`
58
59			`// synopsys translate_off`
60			`include "timescale.v"
61			`// synopsys translate_on`
62
63			`// FF in clock domain 1 is being set by a signal from the clock domain 2`
64			`module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);`
65
66			`parameter Tp = 1;`
67
68			`input clk1;`
69			`input clk2;`
70			`input reset1;`
71			`input reset2;`
72			`input set2;`
73
74			`output sync_out;`
75
76			`reg set2_q;`
77			`reg set2_q2;`
78			`reg set1_q;`
79			`reg set1_q2;`
80			`reg clear2_q;`
81			`reg clear2_q2;`
82			`reg sync_out;`
83
84			`wire z;`
85
86			`assign z = set2 \| set2_q & ~clear2_q2;`
87
88
89			`// Latching and synchronizing "set" to clk2`
90			`always @ (posedge clk2 or posedge reset2)`
91			`begin`
92			`if(reset2)`
93			`set2_q <=#Tp 1'b0;`
94			`else`
95			`set2_q <=#Tp z;`
96			`end`
97
98
99			`always @ (posedge clk2 or posedge reset2)`
100			`begin`
101			`if(reset2)`
102			`set2_q2 <=#Tp 1'b0;`
103			`else`
104			`set2_q2 <=#Tp set2_q;`
105			`end`
106
107
108			`// Synchronizing "set" to clk1`
109			`always @ (posedge clk1 or posedge reset1)`
110			`begin`
111			`if(reset1)`
112			`set1_q <=#Tp 1'b0;`
113			`else`
114			`set1_q <=#Tp set2_q2;`
115			`end`
116
117
118			`always @ (posedge clk1 or posedge reset1)`
119			`begin`
120			`if(reset1)`
121			`set1_q2 <=#Tp 1'b0;`
122			`else`
123			`set1_q2 <=#Tp set1_q;`
124			`end`
125
126
127			`// Synchronizing "clear" to clk2`
128			`always @ (posedge clk2 or posedge reset2)`
129			`begin`
130			`if(reset2)`
131			`clear2_q <=#Tp 1'b0;`
132			`else`
133			`clear2_q <=#Tp set1_q2;`
134			`end`
135
136
137			`always @ (posedge clk2 or posedge reset2)`
138			`begin`
139			`if(reset2)`
140			`clear2_q2 <=#Tp 1'b0;`
141			`else`
142			`clear2_q2 <=#Tp clear2_q;`
143			`end`
144
145
146			`always @ (posedge clk1 or posedge reset1)`
147			`begin`
148			`if(reset1)`
149			`sync_out <=#Tp 1'b0;`
150			`else`
151			`sync_out <=#Tp set1_q2;`
152			`end`
153
154			`endmodule`

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[/] [or1k/] [tags/] [first/] [orp/] [orp_soc/] [rtl/] [verilog/] [dbg_interface/] [dbg_sync_clk1_clk2.v] - Blame information for rev 1765