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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides a behavioral model of generic    ////
////  single-port synchronous RAM.                                ////
////  It also contains a synthesizeable model for FPGAs.          ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Generic FPGA (VENDOR_FPGA)                                ////
////    Tested RAMs: Altera, Xilinx                               ////
////    Synthesis tools: LeonardoSpectrum, Synplicity             ////
////  - Xilinx (VENDOR_XILINX)                                    ////
////  - Altera (VENDOR_ALTERA)                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Richard Herveille, richard@asics.ws                   ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/11/09 00:34:19  samg
// minor changes: unified with all common rams
//
// Revision 1.2  2001/11/08 19:32:59  samg
// corrected output: output not valid if ce low
//
// Revision 1.1.1.1  2001/09/14 09:57:09  rherveille
// Major cleanup.
// Files are now compliant to Altera & Xilinx memories.
// Memories are now compatible, i.e. drop-in replacements.
// Added synthesizeable generic FPGA description.
// Created "generic_memories" cvs entry.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
//`include "timescale.v"
 
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
//`define VENDOR_FPGA
 
module generic_spram(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
        //
        // Default address and data buses width
        //
        parameter aw = 6; //number of address-bits
        parameter dw = 8; //number of data-bits
 
        //
        // Generic synchronous single-port RAM interface
        //
        input           clk;  // Clock, rising edge
        input           rst;  // Reset, active high
        input           ce;   // Chip enable input, active high
        input           we;   // Write enable input, active high
        input           oe;   // Output enable input, active high
        input  [aw-1:0] addr; // address bus inputs
        input  [dw-1:0] di;   // input data bus
        output [dw-1:0] do;   // output data bus
 
        //
        // Module body
        //
 
`ifdef VENDOR_FPGA
        //
        // Instantiation synthesizeable FPGA memory
        //
        // This code has been tested using LeonardoSpectrum and Synplicity.
        // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
        //
        reg [dw-1 :0] mem [(1<<aw) -1:0];
        reg [aw-1:0] raddr;
 
        always@(posedge clk)
        begin
                // read operation
                raddr <= #1 addr;    // read address needs to be registered to read clock
 
                // write operation
                if (we && ce)
                        mem[addr] <= #1 di;
        end
 
        assign #1 do = mem[raddr];
 
`else
 
`ifdef VENDOR_XILINX
 
        wire [dw-1:0] q;  // output from xilinx ram
        //
        // Instantiation of FPGA memory:
        //
        // Virtex/Spartan2 BlockRAMs
        //
        xilinx_ram_sp xilinx_ram(
                .clk(clk),
                .rst(rst),
                .addr(addr),
                .di(di),
                .en(ce),
                .we(we),
                .do(do)
        );
 
        defparam
                xilinx_ram.dwidth = dw,
                xilinx_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ALTERA
 
        //
        // Instantiation of FPGA memory:
        //
        // Altera FLEX EABs
        //
 
        altera_ram_sp altera_ram(
                .inclock(clk),
                .address(addr),
                .data(di),
                .we(we && ce),
                .q(do)
        );
 
        defparam
                altera_ram.dwidth = dw,
                altera_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ARTISAN
 
        //
        // Instantiation of ASIC memory:
        //
        // Artisan Synchronous Single-Port RAM (ra1sh)
        //
        artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(
                .CLK(clk),
                .CEN(~ce),
                .WEN(~we),
                .A(addr),
                .D(di),
                .OEN(~oe),
                .Q(do)
        );
 
`else
 
`ifdef VENDOR_AVANT
 
        //
        // Instantiation of ASIC memory:
        //
        // Avant! Asynchronous Two-Port RAM
        //
        avant_atp avant_atp(
                .web(~we),
                .reb(),
                .oeb(~oe),
                .rcsb(),
                .wcsb(),
                .ra(addr),
                .wa(addr),
                .di(di),
                .do(do)
        );
 
`else
 
`ifdef VENDOR_VIRAGE
 
        //
        // Instantiation of ASIC memory:
        //
        // Virage Synchronous 1-port R/W RAM
        //
        virage_ssp virage_ssp(
                .clk(clk),
                .adr(addr),
                .d(di),
                .we(we),
                .oe(oe),
                .me(ce),
                .q(do)
        );
 
`else
 
`ifdef VENDOR_VIRTUALSILICON
 
        //
        // Instantiation of ASIC memory:
        //
        // Virtual Silicon Single-Port Synchronous SRAM
        //
        virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(
                .CK(clk),
                .ADR(addr),
                .DI(di),
                .WEN(~we),
                .CEN(~ce),
                .OEN(~oe),
                .DOUT(do)
        );
 
`else
 
        //
        // Generic single-port synchronous RAM model
        //
 
        //
        // Generic RAM's registers and wires
        //
        reg  [dw-1:0] mem [(1<<aw)-1:0];  // RAM content
        wire [dw-1:0] q;                 // RAM output
        reg  [aw-1:0] raddr;             // RAM read address
        //
        // Data output drivers
        //
        assign do = (oe & ce) ? q : {dw{1'bz}};
 
        //
        // RAM read and write
        //
 
        // read operation
        always@(posedge clk)
        if (ce) // && !we)
                raddr <= #1 addr;    // read address needs to be registered to read clock
 
        assign #1 q = rst ? {dw{1'b0}} : mem[raddr];
 
        // write operation
        always@(posedge clk)
                if (ce && we)
                        mem[addr] <= #1 di;
 
        // Task prints range of memory
        // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. 
        task print_ram;
        input [aw-1:0] start;
        input [aw-1:0] finish;
        integer rnum;
        begin
                for (rnum=start;rnum<=finish;rnum=rnum+1)
                        $display("Addr %h = %h",rnum,mem[rnum]);
        end
        endtask
 
`endif // !VIRTUALSILICON_SSP
`endif // !VIRAGE_SSP
`endif // !AVANT_ATP
`endif // !ARTISAN_SSP
`endif // !VENDOR_ALTERA
`endif // !VENDOR_XILINX
`endif // !VENDOR_FPGA
 
endmodule
 
 
//
// Black-box modules
//
 
`ifdef VENDOR_ALTERA
        module altera_ram_sp (
                address,
                inclock,
                we,
                data,
                q) /* synthesis black_box */;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input  [awidth -1:0] address;
                input                inclock;
                input                we;
                input  [dwidth -1:0] data;
                output [dwidth -1:0] q;
 
                // synopsis translate_off
                // exemplar translate_off
 
                syn_ram_irou #(
                        "UNUSED",
                        dwidth,
                        awidth,
                        1 << awidth
                )
                altera_spram_model (
                        .Inclock(inclock),
                        .Address(address),
                        .Data(data),
                        .WE(we),
                        .Q(q)
                );
 
                // exemplar translate_on
                // synopsis translate_on
 
        endmodule
`endif // VENDOR_ALTERA
 
`ifdef VENDOR_XILINX
        module xilinx_ram_sp (
                        clk,
                        rst,
                        addr,
                        di,
                        en,
                        we,
                        do) /* synthesis black_box */ ;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input                clk;
                input                rst;
                input  [awidth -1:0] addr;
                input  [dwidth -1:0] di;
                input                en;
                input                we;
                output [dwidth -1:0] do;
 
                // insert simulation model
 
 
                // synopsys translate_off
                // exemplar translate_off
 
                C_MEM_SP_BLOCK_V1_0 #(
                        awidth,
                        1,
                        "0",
                        1 << awidth,
                        1,
                        1,
                        1,
                        1,
                        1,
                        1,
                        1,
                        "",
                        16,
                        0,
                        0,
                        1,
                        1,
                        dwidth
                )
                xilinx_spram_model (
                        .CLK(clk),
                        .RST(rst),
                        .ADDR(addr),
                        .DI(di),
                        .EN(en),
                        .WE(we),
                        .DO(do)
                );
 
                // exemplar translate_on
                // synopsys translate_on
 
        endmodule
`endif // VENDOR_XILINX
 

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[/] [or1k/] [tags/] [first/] [orp/] [orp_soc/] [rtl/] [verilog/] [ethernet.old/] [generic_spram.v] - Blame information for rev 1778

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides a behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It also contains a synthesizeable model for FPGAs. ////`
15			`//// It should be used in all OPENCORES designs that want to be ////`
16			`//// portable accross different target technologies and ////`
17			`//// independent of target memory. ////`
18			`//// ////`
19			`//// Supported ASIC RAMs are: ////`
20			`//// - Artisan Single-Port Sync RAM ////`
21			`//// - Avant! Two-Port Sync RAM (*) ////`
22			`//// - Virage Single-Port Sync RAM ////`
23			`//// - Virtual Silicon Single-Port Sync RAM ////`
24			`//// ////`
25			`//// Supported FPGA RAMs are: ////`
26			`//// - Generic FPGA (VENDOR_FPGA) ////`
27			`//// Tested RAMs: Altera, Xilinx ////`
28			`//// Synthesis tools: LeonardoSpectrum, Synplicity ////`
29			`//// - Xilinx (VENDOR_XILINX) ////`
30			`//// - Altera (VENDOR_ALTERA) ////`
31			`//// ////`
32			`//// To Do: ////`
33			`//// - fix avant! two-port ram ////`
34			`//// - add additional RAMs ////`
35			`//// ////`
36			`//// Author(s): ////`
37			`//// - Richard Herveille, richard@asics.ws ////`
38			`//// - Damjan Lampret, lampret@opencores.org ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//// ////`
42			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
43			`//// ////`
44			`//// This source file may be used and distributed without ////`
45			`//// restriction provided that this copyright statement is not ////`
46			`//// removed from the file and that any derivative work contains ////`
47			`//// the original copyright notice and the associated disclaimer. ////`
48			`//// ////`
49			`//// This source file is free software; you can redistribute it ////`
50			`//// and/or modify it under the terms of the GNU Lesser General ////`
51			`//// Public License as published by the Free Software Foundation; ////`
52			`//// either version 2.1 of the License, or (at your option) any ////`
53			`//// later version. ////`
54			`//// ////`
55			`//// This source is distributed in the hope that it will be ////`
56			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
57			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
58			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
59			`//// details. ////`
60			`//// ////`
61			`//// You should have received a copy of the GNU Lesser General ////`
62			`//// Public License along with this source; if not, download it ////`
63			`//// from http://www.opencores.org/lgpl.shtml ////`
64			`//// ////`
65			`//////////////////////////////////////////////////////////////////////`
66			`//`
67			`// CVS Revision History`
68			`//`
69			`// $Log: not supported by cvs2svn $`
70			`// Revision 1.3 2001/11/09 00:34:19 samg`
71			`// minor changes: unified with all common rams`
72			`//`
73			`// Revision 1.2 2001/11/08 19:32:59 samg`
74			`// corrected output: output not valid if ce low`
75			`//`
76			`// Revision 1.1.1.1 2001/09/14 09:57:09 rherveille`
77			`// Major cleanup.`
78			`// Files are now compliant to Altera & Xilinx memories.`
79			`// Memories are now compatible, i.e. drop-in replacements.`
80			`// Added synthesizeable generic FPGA description.`
81			`// Created "generic_memories" cvs entry.`
82			`//`
83			`// Revision 1.2 2001/07/30 05:38:02 lampret`
84			`// Adding empty directories required by HDL coding guidelines`
85			`//`
86			`//`
87
88			//`include "timescale.v"
89
90			//`define VENDOR_XILINX
91			//`define VENDOR_ALTERA
92			//`define VENDOR_FPGA
93
94			`module generic_spram(`
95			`// Generic synchronous single-port RAM interface`
96			`clk, rst, ce, we, oe, addr, di, do`
97			`);`
98
99			`//`
100			`// Default address and data buses width`
101			`//`
102			`parameter aw = 6; //number of address-bits`
103			`parameter dw = 8; //number of data-bits`
104
105			`//`
106			`// Generic synchronous single-port RAM interface`
107			`//`
108			`input clk; // Clock, rising edge`
109			`input rst; // Reset, active high`
110			`input ce; // Chip enable input, active high`
111			`input we; // Write enable input, active high`
112			`input oe; // Output enable input, active high`
113			`input [aw-1:0] addr; // address bus inputs`
114			`input [dw-1:0] di; // input data bus`
115			`output [dw-1:0] do; // output data bus`
116
117			`//`
118			`// Module body`
119			`//`
120
121			`ifdef VENDOR_FPGA
122			`//`
123			`// Instantiation synthesizeable FPGA memory`
124			`//`
125			`// This code has been tested using LeonardoSpectrum and Synplicity.`
126			`// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.`
127			`//`
128			`reg [dw-1 :0] mem [(1<<aw) -1:0];`
129			`reg [aw-1:0] raddr;`
130
131			`always@(posedge clk)`
132			`begin`
133			`// read operation`
134			`raddr <= #1 addr; // read address needs to be registered to read clock`
135
136			`// write operation`
137			`if (we && ce)`
138			`mem[addr] <= #1 di;`
139			`end`
140
141			`assign #1 do = mem[raddr];`
142
143			`else
144
145			`ifdef VENDOR_XILINX
146
147			`wire [dw-1:0] q; // output from xilinx ram`
148			`//`
149			`// Instantiation of FPGA memory:`
150			`//`
151			`// Virtex/Spartan2 BlockRAMs`
152			`//`
153			`xilinx_ram_sp xilinx_ram(`
154			`.clk(clk),`
155			`.rst(rst),`
156			`.addr(addr),`
157			`.di(di),`
158			`.en(ce),`
159			`.we(we),`
160			`.do(do)`
161			`);`
162
163			`defparam`
164			`xilinx_ram.dwidth = dw,`
165			`xilinx_ram.awidth = aw;`
166
167			`else
168
169			`ifdef VENDOR_ALTERA
170
171			`//`
172			`// Instantiation of FPGA memory:`
173			`//`
174			`// Altera FLEX EABs`
175			`//`
176
177			`altera_ram_sp altera_ram(`
178			`.inclock(clk),`
179			`.address(addr),`
180			`.data(di),`
181			`.we(we && ce),`
182			`.q(do)`
183			`);`
184
185			`defparam`
186			`altera_ram.dwidth = dw,`
187			`altera_ram.awidth = aw;`
188
189			`else
190
191			`ifdef VENDOR_ARTISAN
192
193			`//`
194			`// Instantiation of ASIC memory:`
195			`//`
196			`// Artisan Synchronous Single-Port RAM (ra1sh)`
197			`//`
198			`artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(`
199			`.CLK(clk),`
200			`.CEN(~ce),`
201			`.WEN(~we),`
202			`.A(addr),`
203			`.D(di),`
204			`.OEN(~oe),`
205			`.Q(do)`
206			`);`
207
208			`else
209
210			`ifdef VENDOR_AVANT
211
212			`//`
213			`// Instantiation of ASIC memory:`
214			`//`
215			`// Avant! Asynchronous Two-Port RAM`
216			`//`
217			`avant_atp avant_atp(`
218			`.web(~we),`
219			`.reb(),`
220			`.oeb(~oe),`
221			`.rcsb(),`
222			`.wcsb(),`
223			`.ra(addr),`
224			`.wa(addr),`
225			`.di(di),`
226			`.do(do)`
227			`);`
228
229			`else
230
231			`ifdef VENDOR_VIRAGE
232
233			`//`
234			`// Instantiation of ASIC memory:`
235			`//`
236			`// Virage Synchronous 1-port R/W RAM`
237			`//`
238			`virage_ssp virage_ssp(`
239			`.clk(clk),`
240			`.adr(addr),`
241			`.d(di),`
242			`.we(we),`
243			`.oe(oe),`
244			`.me(ce),`
245			`.q(do)`
246			`);`
247
248			`else
249
250			`ifdef VENDOR_VIRTUALSILICON
251
252			`//`
253			`// Instantiation of ASIC memory:`
254			`//`
255			`// Virtual Silicon Single-Port Synchronous SRAM`
256			`//`
257			`virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(`
258			`.CK(clk),`
259			`.ADR(addr),`
260			`.DI(di),`
261			`.WEN(~we),`
262			`.CEN(~ce),`
263			`.OEN(~oe),`
264			`.DOUT(do)`
265			`);`
266
267			`else
268
269			`//`
270			`// Generic single-port synchronous RAM model`
271			`//`
272
273			`//`
274			`// Generic RAM's registers and wires`
275			`//`
276			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
277			`wire [dw-1:0] q; // RAM output`
278			`reg [aw-1:0] raddr; // RAM read address`
279			`//`
280			`// Data output drivers`
281			`//`
282			`assign do = (oe & ce) ? q : {dw{1'bz}};`
283
284			`//`
285			`// RAM read and write`
286			`//`
287
288			`// read operation`
289			`always@(posedge clk)`
290			`if (ce) // && !we)`
291			`raddr <= #1 addr; // read address needs to be registered to read clock`
292
293			`assign #1 q = rst ? {dw{1'b0}} : mem[raddr];`
294
295			`// write operation`
296			`always@(posedge clk)`
297			`if (ce && we)`
298			`mem[addr] <= #1 di;`
299
300			`// Task prints range of memory`
301			`// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.`
302			`task print_ram;`
303			`input [aw-1:0] start;`
304			`input [aw-1:0] finish;`
305			`integer rnum;`
306			`begin`
307			`for (rnum=start;rnum<=finish;rnum=rnum+1)`
308			`$display("Addr %h = %h",rnum,mem[rnum]);`
309			`end`
310			`endtask`
311
312			`endif // !VIRTUALSILICON_SSP
313			`endif // !VIRAGE_SSP
314			`endif // !AVANT_ATP
315			`endif // !ARTISAN_SSP
316			`endif // !VENDOR_ALTERA
317			`endif // !VENDOR_XILINX
318			`endif // !VENDOR_FPGA
319
320			`endmodule`
321
322
323			`//`
324			`// Black-box modules`
325			`//`
326
327			`ifdef VENDOR_ALTERA
328			`module altera_ram_sp (`
329			`address,`
330			`inclock,`
331			`we,`
332			`data,`
333			`q) /* synthesis black_box */;`
334
335			`parameter awidth = 7;`
336			`parameter dwidth = 8;`
337
338			`input [awidth -1:0] address;`
339			`input inclock;`
340			`input we;`
341			`input [dwidth -1:0] data;`
342			`output [dwidth -1:0] q;`
343
344			`// synopsis translate_off`
345			`// exemplar translate_off`
346
347			`syn_ram_irou #(`
348			`"UNUSED",`
349			`dwidth,`
350			`awidth,`
351			`1 << awidth`
352			`)`
353			`altera_spram_model (`
354			`.Inclock(inclock),`
355			`.Address(address),`
356			`.Data(data),`
357			`.WE(we),`
358			`.Q(q)`
359			`);`
360
361			`// exemplar translate_on`
362			`// synopsis translate_on`
363
364			`endmodule`
365			`endif // VENDOR_ALTERA
366
367			`ifdef VENDOR_XILINX
368			`module xilinx_ram_sp (`
369			`clk,`
370			`rst,`
371			`addr,`
372			`di,`
373			`en,`
374			`we,`
375			`do) /* synthesis black_box */ ;`
376
377			`parameter awidth = 7;`
378			`parameter dwidth = 8;`
379
380			`input clk;`
381			`input rst;`
382			`input [awidth -1:0] addr;`
383			`input [dwidth -1:0] di;`
384			`input en;`
385			`input we;`
386			`output [dwidth -1:0] do;`
387
388			`// insert simulation model`
389
390
391			`// synopsys translate_off`
392			`// exemplar translate_off`
393
394			`C_MEM_SP_BLOCK_V1_0 #(`
395			`awidth,`
396			`1,`
397			`"0",`
398			`1 << awidth,`
399			`1,`
400			`1,`
401			`1,`
402			`1,`
403			`1,`
404			`1,`
405			`1,`
406			`"",`
407			`16,`
408			`0,`
409			`0,`
410			`1,`
411			`1,`
412			`dwidth`
413			`)`
414			`xilinx_spram_model (`
415			`.CLK(clk),`
416			`.RST(rst),`
417			`.ADDR(addr),`
418			`.DI(di),`
419			`.EN(en),`
420			`.WE(we),`
421			`.DO(do)`
422			`);`
423
424			`// exemplar translate_on`
425			`// synopsys translate_on`
426
427			`endmodule`
428			`endif // VENDOR_XILINX
429