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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs (Altera etc)                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/27 21:24:04  lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9  2001/11/27 19:45:04  lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_256x21(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 21;
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
wire    [10:0]           unconnected;
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(
`else
art_hssp_256x21 artisan_ssp(
`endif
        .clk(clk),
        .cen(~ce),
        .wen(~we),
        .a(addr),
        .d(di),
        .oen(~oe),
        .q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdsp_256x21 vs_ssp(
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(do[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI({11'b00000000000, di[20:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, do[20:16]})
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [tags/] [first/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_spram_256x21.v] - Blame information for rev 1780

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// ////`
27			`//// To Do: ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - fix avant! two-port ram ////`
30			`//// - add additional RAMs (Altera etc) ////`
31			`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65			`// Revision 1.1 2002/01/03 08:16:15 lampret`
66			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
67			`//`
68			`// Revision 1.10 2001/11/27 21:24:04 lampret`
69			`// Changed instantiation name of VS RAMs.`
70			`//`
71			`// Revision 1.9 2001/11/27 19:45:04 lampret`
72			`// Fixed VS RAM instantiation - again.`
73			`//`
74			`// Revision 1.8 2001/11/23 21:42:31 simons`
75			`// Program counter divided to PPC and NPC.`
76			`//`
77			`// Revision 1.6 2001/10/21 17:57:16 lampret`
78			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
79			`//`
80			`// Revision 1.5 2001/10/14 13:12:09 lampret`
81			`// MP3 version.`
82			`//`
83			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
84			`// no message`
85			`//`
86			`// Revision 1.1 2001/08/09 13:39:33 lampret`
87			`// Major clean-up.`
88			`//`
89			`// Revision 1.2 2001/07/30 05:38:02 lampret`
90			`// Adding empty directories required by HDL coding guidelines`
91			`//`
92			`//`
93
94			`// synopsys translate_off`
95			`include "timescale.v"
96			`// synopsys translate_on`
97			`include "or1200_defines.v"
98
99			`module or1200_spram_256x21(`
100			`// Generic synchronous single-port RAM interface`
101			`clk, rst, ce, we, oe, addr, di, do`
102			`);`
103
104			`//`
105			`// Default address and data buses width`
106			`//`
107			`parameter aw = 8;`
108			`parameter dw = 21;`
109
110			`//`
111			`// Generic synchronous single-port RAM interface`
112			`//`
113			`input clk; // Clock`
114			`input rst; // Reset`
115			`input ce; // Chip enable input`
116			`input we; // Write enable input`
117			`input oe; // Output enable input`
118			`input [aw-1:0] addr; // address bus inputs`
119			`input [dw-1:0] di; // input data bus`
120			`output [dw-1:0] do; // output data bus`
121
122			`//`
123			`// Internal wires and registers`
124			`//`
125			`wire [10:0] unconnected;`
126
127			`ifdef OR1200_ARTISAN_SSP
128
129			`//`
130			`// Instantiation of ASIC memory:`
131			`//`
132			`// Artisan Synchronous Single-Port RAM (ra1sh)`
133			`//`
134			`ifdef UNUSED
135			`art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(`
136			`else
137			`art_hssp_256x21 artisan_ssp(`
138			`endif
139			`.clk(clk),`
140			`.cen(~ce),`
141			`.wen(~we),`
142			`.a(addr),`
143			`.d(di),`
144			`.oen(~oe),`
145			`.q(do)`
146			`);`
147
148			`else
149
150			`ifdef OR1200_AVANT_ATP
151
152			`//`
153			`// Instantiation of ASIC memory:`
154			`//`
155			`// Avant! Asynchronous Two-Port RAM`
156			`//`
157			`avant_atp avant_atp(`
158			`.web(~we),`
159			`.reb(),`
160			`.oeb(~oe),`
161			`.rcsb(),`
162			`.wcsb(),`
163			`.ra(addr),`
164			`.wa(addr),`
165			`.di(di),`
166			`.do(do)`
167			`);`
168
169			`else
170
171			`ifdef OR1200_VIRAGE_SSP
172
173			`//`
174			`// Instantiation of ASIC memory:`
175			`//`
176			`// Virage Synchronous 1-port R/W RAM`
177			`//`
178			`virage_ssp virage_ssp(`
179			`.clk(clk),`
180			`.adr(addr),`
181			`.d(di),`
182			`.we(we),`
183			`.oe(oe),`
184			`.me(ce),`
185			`.q(do)`
186			`);`
187
188			`else
189
190			`ifdef OR1200_VIRTUALSILICON_SSP
191
192			`//`
193			`// Instantiation of ASIC memory:`
194			`//`
195			`// Virtual Silicon Single-Port Synchronous SRAM`
196			`//`
197			`ifdef UNUSED
198			`vs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(`
199			`else
200			`vs_hdsp_256x21 vs_ssp(`
201			`endif
202			`.CK(clk),`
203			`.ADR(addr),`
204			`.DI(di),`
205			`.WEN(~we),`
206			`.CEN(~ce),`
207			`.OEN(~oe),`
208			`.DOUT(do)`
209			`);`
210
211			`else
212
213			`ifdef OR1200_XILINX_RAMB4
214
215			`//`
216			`// Instantiation of FPGA memory:`
217			`//`
218			`// Virtex/Spartan2`
219			`//`
220
221			`//`
222			`// Block 0`
223			`//`
224			`RAMB4_S16 ramb4_s16_0(`
225			`.CLK(clk),`
226			`.RST(rst),`
227			`.ADDR(addr),`
228			`.DI(di[15:0]),`
229			`.EN(ce),`
230			`.WE(we),`
231			`.DO(do[15:0])`
232			`);`
233
234			`//`
235			`// Block 1`
236			`//`
237			`RAMB4_S16 ramb4_s16_1(`
238			`.CLK(clk),`
239			`.RST(rst),`
240			`.ADDR(addr),`
241			`.DI({11'b00000000000, di[20:16]}),`
242			`.EN(ce),`
243			`.WE(we),`
244			`.DO({unconnected, do[20:16]})`
245			`);`
246
247			`else
248
249			`//`
250			`// Generic single-port synchronous RAM model`
251			`//`
252
253			`//`
254			`// Generic RAM's registers and wires`
255			`//`
256			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
257			`reg [dw-1:0] do_reg; // RAM data output register`
258
259			`//`
260			`// Data output drivers`
261			`//`
262			`assign do = (oe) ? do_reg : {dw{1'bz}};`
263
264			`//`
265			`// RAM read and write`
266			`//`
267			`always @(posedge clk)`
268			`if (ce && !we)`
269			`do_reg <= #1 mem[addr];`
270			`else if (ce && we)`
271			`mem[addr] <= #1 di;`
272
273			`endif // !OR1200_XILINX_RAMB4_S16
274			`endif // !OR1200_VIRTUALSILICON_SSP
275			`endif // !OR1200_VIRAGE_SSP
276			`endif // !OR1200_AVANT_ATP
277			`endif // !OR1200_ARTISAN_SSP
278
279			`endmodule`