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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`ifdef OR1200_XILINX_RAM32X1D
 
module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
 
`endif

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[/] [or1k/] [tags/] [first/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_xcv_ram32x8d.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50			`// Revision 1.7 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.6 2001/10/14 13:12:10 lampret`
54			`// MP3 version.`
55			`//`
56			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
57			`// no message`
58			`//`
59			`// Revision 1.1 2001/08/09 13:39:33 lampret`
60			`// Major clean-up.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "or1200_defines.v"
68
69			`ifdef OR1200_XILINX_RAM32X1D
70
71			`module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
72
73			`//`
74			`// I/O`
75			`//`
76			`output [7:0] DPO;`
77			`output [7:0] SPO;`
78			`input [4:0] A;`
79			`input [4:0] DPRA;`
80			`input [7:0] D;`
81			`input WCLK;`
82			`input WE;`
83
84			`//`
85			`// Instantiation of block 0`
86			`//`
87			`RAM32X1D ram32x1d_0(`
88			`.DPO(DPO[0]),`
89			`.SPO(SPO[0]),`
90			`.A0(A[0]),`
91			`.A1(A[1]),`
92			`.A2(A[2]),`
93			`.A3(A[3]),`
94			`.A4(A[4]),`
95			`.D(D[0]),`
96			`.DPRA0(DPRA[0]),`
97			`.DPRA1(DPRA[1]),`
98			`.DPRA2(DPRA[2]),`
99			`.DPRA3(DPRA[3]),`
100			`.DPRA4(DPRA[4]),`
101			`.WCLK(WCLK),`
102			`.WE(WE)`
103			`);`
104
105			`//`
106			`// Instantiation of block 1`
107			`//`
108			`RAM32X1D ram32x1d_1(`
109			`.DPO(DPO[1]),`
110			`.SPO(SPO[1]),`
111			`.A0(A[0]),`
112			`.A1(A[1]),`
113			`.A2(A[2]),`
114			`.A3(A[3]),`
115			`.A4(A[4]),`
116			`.D(D[1]),`
117			`.DPRA0(DPRA[0]),`
118			`.DPRA1(DPRA[1]),`
119			`.DPRA2(DPRA[2]),`
120			`.DPRA3(DPRA[3]),`
121			`.DPRA4(DPRA[4]),`
122			`.WCLK(WCLK),`
123			`.WE(WE)`
124			`);`
125
126			`//`
127			`// Instantiation of block 2`
128			`//`
129			`RAM32X1D ram32x1d_2(`
130			`.DPO(DPO[2]),`
131			`.SPO(SPO[2]),`
132			`.A0(A[0]),`
133			`.A1(A[1]),`
134			`.A2(A[2]),`
135			`.A3(A[3]),`
136			`.A4(A[4]),`
137			`.D(D[2]),`
138			`.DPRA0(DPRA[0]),`
139			`.DPRA1(DPRA[1]),`
140			`.DPRA2(DPRA[2]),`
141			`.DPRA3(DPRA[3]),`
142			`.DPRA4(DPRA[4]),`
143			`.WCLK(WCLK),`
144			`.WE(WE)`
145			`);`
146
147			`//`
148			`// Instantiation of block 3`
149			`//`
150			`RAM32X1D ram32x1d_3(`
151			`.DPO(DPO[3]),`
152			`.SPO(SPO[3]),`
153			`.A0(A[0]),`
154			`.A1(A[1]),`
155			`.A2(A[2]),`
156			`.A3(A[3]),`
157			`.A4(A[4]),`
158			`.D(D[3]),`
159			`.DPRA0(DPRA[0]),`
160			`.DPRA1(DPRA[1]),`
161			`.DPRA2(DPRA[2]),`
162			`.DPRA3(DPRA[3]),`
163			`.DPRA4(DPRA[4]),`
164			`.WCLK(WCLK),`
165			`.WE(WE)`
166			`);`
167
168			`//`
169			`// Instantiation of block 4`
170			`//`
171			`RAM32X1D ram32x1d_4(`
172			`.DPO(DPO[4]),`
173			`.SPO(SPO[4]),`
174			`.A0(A[0]),`
175			`.A1(A[1]),`
176			`.A2(A[2]),`
177			`.A3(A[3]),`
178			`.A4(A[4]),`
179			`.D(D[4]),`
180			`.DPRA0(DPRA[0]),`
181			`.DPRA1(DPRA[1]),`
182			`.DPRA2(DPRA[2]),`
183			`.DPRA3(DPRA[3]),`
184			`.DPRA4(DPRA[4]),`
185			`.WCLK(WCLK),`
186			`.WE(WE)`
187			`);`
188
189			`//`
190			`// Instantiation of block 5`
191			`//`
192			`RAM32X1D ram32x1d_5(`
193			`.DPO(DPO[5]),`
194			`.SPO(SPO[5]),`
195			`.A0(A[0]),`
196			`.A1(A[1]),`
197			`.A2(A[2]),`
198			`.A3(A[3]),`
199			`.A4(A[4]),`
200			`.D(D[5]),`
201			`.DPRA0(DPRA[0]),`
202			`.DPRA1(DPRA[1]),`
203			`.DPRA2(DPRA[2]),`
204			`.DPRA3(DPRA[3]),`
205			`.DPRA4(DPRA[4]),`
206			`.WCLK(WCLK),`
207			`.WE(WE)`
208			`);`
209
210			`//`
211			`// Instantiation of block 6`
212			`//`
213			`RAM32X1D ram32x1d_6(`
214			`.DPO(DPO[6]),`
215			`.SPO(SPO[6]),`
216			`.A0(A[0]),`
217			`.A1(A[1]),`
218			`.A2(A[2]),`
219			`.A3(A[3]),`
220			`.A4(A[4]),`
221			`.D(D[6]),`
222			`.DPRA0(DPRA[0]),`
223			`.DPRA1(DPRA[1]),`
224			`.DPRA2(DPRA[2]),`
225			`.DPRA3(DPRA[3]),`
226			`.DPRA4(DPRA[4]),`
227			`.WCLK(WCLK),`
228			`.WE(WE)`
229			`);`
230
231			`//`
232			`// Instantiation of block 7`
233			`//`
234			`RAM32X1D ram32x1d_7(`
235			`.DPO(DPO[7]),`
236			`.SPO(SPO[7]),`
237			`.A0(A[0]),`
238			`.A1(A[1]),`
239			`.A2(A[2]),`
240			`.A3(A[3]),`
241			`.A4(A[4]),`
242			`.D(D[7]),`
243			`.DPRA0(DPRA[0]),`
244			`.DPRA1(DPRA[1]),`
245			`.DPRA2(DPRA[2]),`
246			`.DPRA3(DPRA[3]),`
247			`.DPRA4(DPRA[4]),`
248			`.WCLK(WCLK),`
249			`.WE(WE)`
250			`);`
251
252			`endmodule`
253
254			`endif