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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Simple Small VGA IP Core                                    ////
////                                                              ////
////  This file is part of the Simple Small VGA project           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  LITTLE-ENDIAN WISHBONE slave interface.                     ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/02/01 15:24:46  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.1.1.1  2001/10/02 15:33:33  mihad
// New project directory structure
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`define SEL_PAL 10
`define SEL_ADDRESS 2
 
module ssvga_wbs_if(
        // Clock and reset
        wb_clk_i, wb_rst_i,
 
        // WISHBONE Slave I/F
        wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,
        wbs_adr_i, wbs_dat_i, wbs_cab_i,
        wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
 
        // Other signals
        ssvga_en, pal_wr_en, pal_rd_en, pal_dat,
    pix_start_addr
);
 
//
// I/O ports
//
 
//
// Clock and reset
//
input                   wb_clk_i;       // Pixel Clock
input                   wb_rst_i;       // Reset
 
//
// WISHBONE Slave I/F
//
input                   wbs_cyc_i;
input                   wbs_stb_i;
input   [3:0]            wbs_sel_i;
input                   wbs_we_i;
input   [31:0]           wbs_adr_i;
input   [31:0]           wbs_dat_i;
input                   wbs_cab_i;
output  [31:0]           wbs_dat_o;
output                  wbs_ack_o;
output                  wbs_err_o;
output                  wbs_rty_o;
 
//
// Other signals
//
output                  ssvga_en;       // Global enable
output                  pal_wr_en;      // Palette write enable
output                  pal_rd_en;      // Palette read enable
input   [15:0]           pal_dat;        // Palette data
output  [31:2] pix_start_addr ;
 
//
// Internal regs and wires
//
reg                     wbs_ack_o;      // WISHBONE ack
reg                     wbs_err_o;      // WISHBONE err
reg     [0:0]             ctrl_r;         // Control register
wire                    valid_access;   // Access to SSVGA
 
//
// Control register
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                ctrl_r <= #1 1'b0;
        else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & !wbs_adr_i[`SEL_ADDRESS])
                ctrl_r <= #1 wbs_dat_i[0];
 
reg [31:2] pix_start_addr ;
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                pix_start_addr <= #1 30'h0000_0000 ;
        else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & wbs_adr_i[`SEL_ADDRESS] )
                pix_start_addr <= #1 wbs_dat_i[31:2] ;
 
//
// Generate delayed WISHBONE ack/err
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i) begin
                wbs_ack_o <= #1 1'b0;
                wbs_err_o <= #1 1'b0;
        end
        else if (valid_access) begin
                wbs_ack_o <= #1 1'b1;
                wbs_err_o <= #1 1'b0;
        end
        else if (wbs_cyc_i & wbs_stb_i) begin
                wbs_ack_o <= #1 1'b0;
                wbs_err_o <= #1 1'b1;
        end
        else begin
                wbs_ack_o <= #1 1'b0;
                wbs_err_o <= #1 1'b0;
        end
 
//
// Generate WISHBONE output signals
//
reg [31:0] wbs_dat_o ;
always@(wbs_adr_i or pal_dat or ctrl_r or pix_start_addr)
begin
    if ( wbs_adr_i[`SEL_PAL] )
        wbs_dat_o = {16'h0000, pal_dat} ;
    else
    if ( wbs_adr_i[`SEL_ADDRESS] )
        wbs_dat_o = {pix_start_addr, 2'b00} ;
    else
        wbs_dat_o = {{31{1'b0}}, ctrl_r};
end
 
assign wbs_rty_o = 1'b0;
 
//
// Generate other signals
//
assign valid_access = wbs_cyc_i & wbs_stb_i & (wbs_sel_i == 4'b1111);
assign ssvga_en = ctrl_r[0];
assign pal_wr_en = valid_access & wbs_we_i & wbs_adr_i[`SEL_PAL];
assign pal_rd_en = valid_access & ~wbs_we_i & wbs_adr_i[`SEL_PAL];
 
endmodule

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Simple Small VGA IP Core ////`
4			`//// ////`
5			`//// This file is part of the Simple Small VGA project ////`
6			`//// ////`
7			`//// ////`
8			`//// Description ////`
9			`//// LITTLE-ENDIAN WISHBONE slave interface. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.2 2002/02/01 15:24:46 mihad`
48			`// Repaired a few bugs, updated specification, added test bench files and design document`
49			`//`
50			`// Revision 1.1.1.1 2001/10/02 15:33:33 mihad`
51			`// New project directory structure`
52			`//`
53			`//`
54
55			`// synopsys translate_off`
56			`include "timescale.v"
57			`// synopsys translate_on`
58
59			`define SEL_PAL 10
60			`define SEL_ADDRESS 2
61
62			`module ssvga_wbs_if(`
63			`// Clock and reset`
64			`wb_clk_i, wb_rst_i,`
65
66			`// WISHBONE Slave I/F`
67			`wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,`
68			`wbs_adr_i, wbs_dat_i, wbs_cab_i,`
69			`wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,`
70
71			`// Other signals`
72			`ssvga_en, pal_wr_en, pal_rd_en, pal_dat,`
73			`pix_start_addr`
74			`);`
75
76			`//`
77			`// I/O ports`
78			`//`
79
80			`//`
81			`// Clock and reset`
82			`//`
83			`input wb_clk_i; // Pixel Clock`
84			`input wb_rst_i; // Reset`
85
86			`//`
87			`// WISHBONE Slave I/F`
88			`//`
89			`input wbs_cyc_i;`
90			`input wbs_stb_i;`
91			`input [3:0] wbs_sel_i;`
92			`input wbs_we_i;`
93			`input [31:0] wbs_adr_i;`
94			`input [31:0] wbs_dat_i;`
95			`input wbs_cab_i;`
96			`output [31:0] wbs_dat_o;`
97			`output wbs_ack_o;`
98			`output wbs_err_o;`
99			`output wbs_rty_o;`
100
101			`//`
102			`// Other signals`
103			`//`
104			`output ssvga_en; // Global enable`
105			`output pal_wr_en; // Palette write enable`
106			`output pal_rd_en; // Palette read enable`
107			`input [15:0] pal_dat; // Palette data`
108			`output [31:2] pix_start_addr ;`
109
110			`//`
111			`// Internal regs and wires`
112			`//`
113			`reg wbs_ack_o; // WISHBONE ack`
114			`reg wbs_err_o; // WISHBONE err`
115			`reg [0:0] ctrl_r; // Control register`
116			`wire valid_access; // Access to SSVGA`
117
118			`//`
119			`// Control register`
120			`//`
121			`always @(posedge wb_clk_i or posedge wb_rst_i)`
122			`if (wb_rst_i)`
123			`ctrl_r <= #1 1'b0;`
124			else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & !wbs_adr_i[`SEL_ADDRESS])
125			`ctrl_r <= #1 wbs_dat_i[0];`
126
127			`reg [31:2] pix_start_addr ;`
128			`always @(posedge wb_clk_i or posedge wb_rst_i)`
129			`if (wb_rst_i)`
130			`pix_start_addr <= #1 30'h0000_0000 ;`
131			else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & wbs_adr_i[`SEL_ADDRESS] )
132			`pix_start_addr <= #1 wbs_dat_i[31:2] ;`
133
134			`//`
135			`// Generate delayed WISHBONE ack/err`
136			`//`
137			`always @(posedge wb_clk_i or posedge wb_rst_i)`
138			`if (wb_rst_i) begin`
139			`wbs_ack_o <= #1 1'b0;`
140			`wbs_err_o <= #1 1'b0;`
141			`end`
142			`else if (valid_access) begin`
143			`wbs_ack_o <= #1 1'b1;`
144			`wbs_err_o <= #1 1'b0;`
145			`end`
146			`else if (wbs_cyc_i & wbs_stb_i) begin`
147			`wbs_ack_o <= #1 1'b0;`
148			`wbs_err_o <= #1 1'b1;`
149			`end`
150			`else begin`
151			`wbs_ack_o <= #1 1'b0;`
152			`wbs_err_o <= #1 1'b0;`
153			`end`
154
155			`//`
156			`// Generate WISHBONE output signals`
157			`//`
158			`reg [31:0] wbs_dat_o ;`
159			`always@(wbs_adr_i or pal_dat or ctrl_r or pix_start_addr)`
160			`begin`
161			if ( wbs_adr_i[`SEL_PAL] )
162			`wbs_dat_o = {16'h0000, pal_dat} ;`
163			`else`
164			if ( wbs_adr_i[`SEL_ADDRESS] )
165			`wbs_dat_o = {pix_start_addr, 2'b00} ;`
166			`else`
167			`wbs_dat_o = {{31{1'b0}}, ctrl_r};`
168			`end`
169
170			`assign wbs_rty_o = 1'b0;`
171
172			`//`
173			`// Generate other signals`
174			`//`
175			`assign valid_access = wbs_cyc_i & wbs_stb_i & (wbs_sel_i == 4'b1111);`
176			`assign ssvga_en = ctrl_r[0];`
177			assign pal_wr_en = valid_access & wbs_we_i & wbs_adr_i[`SEL_PAL];
178			assign pal_rd_en = valid_access & ~wbs_we_i & wbs_adr_i[`SEL_PAL];
179
180			`endmodule`

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[/] [or1k/] [tags/] [first/] [orp/] [orp_soc/] [rtl/] [verilog/] [ssvga/] [ssvga_wbs_if.v] - Blame information for rev 1765