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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  TDM slave controller, high speed version                    ////
////                                                              ////
////  This file is part of the OR1K test application              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  This block connectes the FPGA and CPLD on XESS XSV board    ////
////  using high speed time division multiplexing over serial     ////
////  connection. This block implements the slave part.           ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////      - Simon Srot, simons@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 OpenCores                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module tdm_slave_if(
        clk, rst, tdmfrm, tdmrx, tdmtx,
        din, dout
);
 
//
// I/O ports
//
 
//
// Global signals
//
input           clk;
input           rst;
 
//
// External CPLD signals
//
input           tdmfrm;
input           tdmrx;
output          tdmtx;
 
//
// Internal demuxed 8-bit buses
//
input   [7:0]    din;
output  [7:0]    dout;
 
//
// Internal regs and wires
//
reg     [2:0]    clk_cnt;
reg     [7:0]    dout;
reg             tdmtx;
 
//
// Counter for low speed clock and incoming JTAG data slots
// 
always @(posedge clk or posedge rst)
        if (rst)
                clk_cnt <= #1 3'b000;
        else if (tdmfrm)
                clk_cnt <= #1 3'b001;
        else
                clk_cnt <= #1 clk_cnt + 1;
 
//
// RX Data slot extraction
//
always @(posedge clk or posedge rst)
        if (rst) begin
                dout <= #1 8'b0000_0000;
        end else
        case (clk_cnt[2:0])
                3'd0:   dout[0] <= #1 tdmrx;
                3'd1:   dout[1] <= #1 tdmrx;
                3'd2:   dout[2] <= #1 tdmrx;
                3'd3:   dout[3] <= #1 tdmrx;
                3'd4:   dout[4] <= #1 tdmrx;
                3'd5:   dout[5] <= #1 tdmrx;
                3'd6:   dout[6] <= #1 tdmrx;
                3'd7:   dout[7] <= #1 tdmrx;
        endcase
 
//
// TX Data slot insertion
//
always @(clk_cnt or din)
        case (clk_cnt[2:0])
                3'd0:   tdmtx = din[0];
                3'd1:   tdmtx = din[1];
                3'd2:   tdmtx = din[2];
                3'd3:   tdmtx = din[3];
                3'd4:   tdmtx = din[4];
                3'd5:   tdmtx = din[5];
                3'd6:   tdmtx = din[6];
                3'd7:   tdmtx = din[7];
        endcase
 
endmodule
 

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// TDM slave controller, high speed version ////`
4			`//// ////`
5			`//// This file is part of the OR1K test application ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block connectes the FPGA and CPLD on XESS XSV board ////`
10			`//// using high speed time division multiplexing over serial ////`
11			`//// connection. This block implements the slave part. ////`
12			`//// ////`
13			`//// To Do: ////`
14			`//// - nothing really ////`
15			`//// ////`
16			`//// Author(s): ////`
17			`//// - Damjan Lampret, lampret@opencores.org ////`
18			`//// - Simon Srot, simons@opencores.org ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2002 OpenCores ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46
47
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52
53			`module tdm_slave_if(`
54			`clk, rst, tdmfrm, tdmrx, tdmtx,`
55			`din, dout`
56			`);`
57
58			`//`
59			`// I/O ports`
60			`//`
61
62			`//`
63			`// Global signals`
64			`//`
65			`input clk;`
66			`input rst;`
67
68			`//`
69			`// External CPLD signals`
70			`//`
71			`input tdmfrm;`
72			`input tdmrx;`
73			`output tdmtx;`
74
75			`//`
76			`// Internal demuxed 8-bit buses`
77			`//`
78			`input [7:0] din;`
79			`output [7:0] dout;`
80
81			`//`
82			`// Internal regs and wires`
83			`//`
84			`reg [2:0] clk_cnt;`
85			`reg [7:0] dout;`
86			`reg tdmtx;`
87
88			`//`
89			`// Counter for low speed clock and incoming JTAG data slots`
90			`//`
91			`always @(posedge clk or posedge rst)`
92			`if (rst)`
93			`clk_cnt <= #1 3'b000;`
94			`else if (tdmfrm)`
95			`clk_cnt <= #1 3'b001;`
96			`else`
97			`clk_cnt <= #1 clk_cnt + 1;`
98
99			`//`
100			`// RX Data slot extraction`
101			`//`
102			`always @(posedge clk or posedge rst)`
103			`if (rst) begin`
104			`dout <= #1 8'b0000_0000;`
105			`end else`
106			`case (clk_cnt[2:0])`
107			`3'd0: dout[0] <= #1 tdmrx;`
108			`3'd1: dout[1] <= #1 tdmrx;`
109			`3'd2: dout[2] <= #1 tdmrx;`
110			`3'd3: dout[3] <= #1 tdmrx;`
111			`3'd4: dout[4] <= #1 tdmrx;`
112			`3'd5: dout[5] <= #1 tdmrx;`
113			`3'd6: dout[6] <= #1 tdmrx;`
114			`3'd7: dout[7] <= #1 tdmrx;`
115			`endcase`
116
117			`//`
118			`// TX Data slot insertion`
119			`//`
120			`always @(clk_cnt or din)`
121			`case (clk_cnt[2:0])`
122			`3'd0: tdmtx = din[0];`
123			`3'd1: tdmtx = din[1];`
124			`3'd2: tdmtx = din[2];`
125			`3'd3: tdmtx = din[3];`
126			`3'd4: tdmtx = din[4];`
127			`3'd5: tdmtx = din[5];`
128			`3'd6: tdmtx = din[6];`
129			`3'd7: tdmtx = din[7];`
130			`endcase`
131
132			`endmodule`
133

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[/] [or1k/] [tags/] [first/] [orp/] [orp_soc/] [rtl/] [verilog/] [tdm_slave_if.v] - Blame information for rev 1780