OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [first/] [orp/] [orp_soc/] [sw/] [orp_mon/] [board.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 748 lampret
#define REG8(x) (*(volatile unsigned char *)(x))
2
#define REG32(x) (*(volatile unsigned long *)(x))
3
 
4
#ifdef XESS
5
#define MC_ENABLED          0
6
#else
7
#define MC_ENABLED          1
8
#endif
9
#define IC_ENABLE           0
10
 
11
#define MC_CSR_VAL      0x0B000300
12
#define MC_MASK_VAL     0x000000e0
13
#define FLASH_BASE_ADD  0x04000000
14
#define FLASH_TMS_VAL   0x0010a10a
15
#define SDRAM_BASE_ADD  0x00000000
16
#define SDRAM_TMS_VAL   0x07248230
17
 
18
#ifdef XESS
19
#define IN_CLK                12500000
20
#else
21
#define IN_CLK                25000000
22
#endif
23
 
24
#ifdef XESS
25
#define UART_BAUD_RATE  19200
26
#else
27
#define UART_BAUD_RATE  9600 /* 115200 */
28
#endif
29
 
30
#define UART_BASE           0x90000000
31
#ifdef XESS
32
#define ETH_BASE        0x92000000
33
#else
34
#define ETH_BASE        0xD0000000
35
#endif
36
#define MC_BASE_ADD     0x60000000
37
 
38
#define ETH0_INT        _int_main       /* was:    0x00080000 */  /* Not correct */
39
 
40
/*#define ETH_DATA_BASE   0x00020000   Address for ETH_DATA */
41
 #define ETH_DATA_BASE   0xa8000000 /*  Address for ETH_DATA */
42
#define ETH_MACADDR0    0x00
43
#define ETH_MACADDR1    0x09
44
#define ETH_MACADDR2    0x12
45
#define ETH_MACADDR3    0x34
46
#define ETH_MACADDR4    0x56
47
#define ETH_MACADDR5    0x00
48
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.