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#-- Synplicity, Inc.

#-- Version 7.0.3

#-- Project file G:\mp3.cop\syn\synplify\xsv_fpga_top.prj

#-- Written on Thu Mar 21 17:53:21 2002

#add_file options

add_file -verilog "$LIB/xilinx/virtex.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/audio/fifo_empty_16.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/audio/audio_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/audio/audio_wb_if.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/audio/fifo_4095_16.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/audio/audio_codec_if.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/dbg_interface/dbg_trace.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/dbg_interface/dbg_register.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/dbg_interface/dbg_registers.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/dbg_interface/dbg_sync_clk1_clk2.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/dbg_interface/dbg_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/dbg_interface/dbg_crc8_d1.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/generic_tpram.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_crc.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_fifo.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_maccontrol.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_macstatus.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_miim.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_outputcontrol.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_random.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_receivecontrol.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_register.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_registers.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_rxaddrcheck.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_rxcounters.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_rxethmac.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_rxstatem.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_shiftreg.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_sync_clk1_clk2.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_transmitcontrol.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_txcounters.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_txethmac.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_txstatem.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_wishbone.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_wishbonedma.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/generic_spram.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ethernet/eth_clockgen.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/mem_if/sram_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/mem_if/flash_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_xcv_ram32x8d.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_amultp2_32x32.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_cfgr.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_cpu.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_ctrl.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_dc_fsm.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_dc_ram.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_dc_tag.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_dc_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_defines.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_dmmu_tlb.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_dmmu_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_dpram_32x32.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_du.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_except.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_freeze.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_genpc.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_gmultp2_32x32.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_ic_fsm.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_ic_ram.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_ic_tag.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_ic_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_if.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_immu_tlb.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_immu_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_lsu.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_mem2reg.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_mult_mac.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_operandmuxes.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_pic.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_pm.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_reg2mem.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_rf.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_1024x32.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_1024x8.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_2048x32.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_2048x8.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_256x21.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_512x20.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_64x14.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_64x22.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_spram_64x24.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_sprs.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_tpram_32x32.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_tt.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_wb_biu.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_wbmux.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/or1200/or1200_alu.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ps2/ps2_wb_if.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ps2/ps2_io_ctrl.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ps2/ps2_keyboard.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ps2/ps2_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ps2/ps2_translation_table.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ssvga/crtc_iob.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ssvga/ssvga_crtc.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ssvga/ssvga_fifo.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ssvga/ssvga_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ssvga/ssvga_wbm_if.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/ssvga/ssvga_wbs_if.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/uart16550/uart_wb.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/uart16550/uart_fifo.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/uart16550/uart_receiver.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/uart16550/uart_regs.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/uart16550/uart_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/uart16550/uart_transmitter.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/uart16550/uart_debug_if.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/tc_top.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/tdm_slave_if.v"

add_file -verilog "G:/projects/mp3.cop/rtl/verilog/xfpga_top.v"

#reporting options

#implementation: "xfpga_top_1"

impl -add xfpga_top_1

#device options

set_option -technology VIRTEX

set_option -part XCV800

set_option -package HQ240

set_option -speed_grade -6

#compilation/mapping options

set_option -default_enum_encoding default

set_option -symbolic_fsm_compiler 0

set_option -resource_sharing 0

set_option -top_module "xfpga_top"

#map options

set_option -frequency 25.000

set_option -fanout_limit 100

set_option -disable_io_insertion 0

set_option -pipe 0

set_option -modular 0

set_option -retiming 0

#simulation options

set_option -write_verilog 0

set_option -write_vhdl 0

#automatic place and route (vendor) options

set_option -write_apr_constraint 1

#set result format/file last

project -result_file "xfpga_top_1/xfpga_top.edf"

set_option -include_path "/projects/mp3.cop/rtl/verilog/;/projects/mp3.cop/rl/verilog/dbg_interface;/projects/mp3.cop/rtl/verilog/audio/;/projects/mp3.cop/rtl/verilog/ethernet/;/projects/mp3.cop/rtl/verilog/mem_if/;/projects/mp3.cop/rtl/verilog/or1200/;/projects/mp3.cop/rtl/verilog/ps2/;/projects/mp3.cop/rtl/verilog/ssvga/;/projects/mp3.cop/rtl/verilog/uart16550/"

#implementation: "xfpga_top_2"

impl -add xfpga_top_2

#device options

set_option -technology VIRTEX2

set_option -part XC2V1000

set_option -package BG575

set_option -speed_grade -6

#compilation/mapping options

set_option -default_enum_encoding default

set_option -symbolic_fsm_compiler 0

set_option -resource_sharing 0

set_option -top_module "xfpga_top"

#map options

set_option -frequency 35.000

set_option -fanout_limit 100

set_option -disable_io_insertion 0

set_option -pipe 0

set_option -modular 0

set_option -retiming 0

#simulation options

set_option -write_verilog 0

set_option -write_vhdl 0

#automatic place and route (vendor) options

set_option -write_apr_constraint 1

#set result format/file last

project -result_file "xfpga_top_2/xfpga_top.edf"

set_option -include_path "/projects/mp3.cop/rtl/verilog/;/projects/mp3.cop/rl/verilog/dbg_interface;/projects/mp3.cop/rtl/verilog/audio/;/projects/mp3.cop/rtl/verilog/ethernet/;/projects/mp3.cop/rtl/verilog/mem_if/;/projects/mp3.cop/rtl/verilog/or1200/;/projects/mp3.cop/rtl/verilog/ps2/;/projects/mp3.cop/rtl/verilog/ssvga/;/projects/mp3.cop/rtl/verilog/uart16550/"

#implementation: "xfpga_top_5"

impl -add xfpga_top_5

#device options

set_option -technology VIRTEX

set_option -part XCV800

set_option -package HQ240

set_option -speed_grade -6

#compilation/mapping options

set_option -default_enum_encoding default

set_option -symbolic_fsm_compiler 0

set_option -resource_sharing 0

set_option -top_module "xfpga_top"

#map options

set_option -frequency 25.000

set_option -fanout_limit 100

set_option -disable_io_insertion 0

set_option -pipe 0

set_option -modular 0

set_option -retiming 0

#simulation options

set_option -write_verilog 0

set_option -write_vhdl 0

#automatic place and route (vendor) options

set_option -write_apr_constraint 1

#set result format/file last

project -result_file "xfpga_top_5/xfpga_top.edf"

set_option -include_path "/projects/mp3.cop/rtl/verilog/;/projects/mp3.cop/rl/verilog/dbg_interface;/projects/mp3.cop/rtl/verilog/audio/;/projects/mp3.cop/rtl/verilog/ethernet/;/projects/mp3.cop/rtl/verilog/mem_if/;/projects/mp3.cop/rtl/verilog/or1200/;/projects/mp3.cop/rtl/verilog/ps2/;/projects/mp3.cop/rtl/verilog/ssvga/;/projects/mp3.cop/rtl/verilog/uart16550/"

impl -active "xfpga_top_5"